[PATCH] D117355: [PowerPC] Fix the undef virtual register reading failure for PPC backend trap optimization

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

Ping


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[PATCH] D117355: [PowerPC] Fix the undef virtual register reading failure for PPC backend trap optimization

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 407877.
NeHuang marked an inline comment as done.
NeHuang added a comment.

Address review comments.


Repository:
  rG LLVM Github Monorepo

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Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/mi-peephole-trap-opt-dominated-block.mir

Index: llvm/test/CodeGen/PowerPC/mi-peephole-trap-opt-dominated-block.mir
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mi-peephole-trap-opt-dominated-block.mir
@@ -0,0 +1,152 @@
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes \
+# RUN:   -stop-after=ppc-mi-peepholes -ppc-opt-conditional-trap \
+# RUN:   | FileCheck --check-prefix=CHECK-MIR %s
+
+# RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes \
+# RUN:   -stop-after=ppc-mi-peepholes -ppc-opt-conditional-trap \
+# RUN:   | FileCheck --check-prefix=CHECK-MIR %s
+
+# RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes \
+# RUN:   -stop-after=ppc-mi-peepholes -ppc-opt-conditional-trap \
+# RUN:   | FileCheck --check-prefix=CHECK-MIR %s
+
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes \
+# RUN:   -ppc-opt-conditional-trap | FileCheck %s
+
+
+--- |
+  define dso_local signext i32 @callee(i32 signext %ic, i32 signext %id) {
+  entry:
+%add = add nsw i32 %id, %ic
+ret i32 %add
+  }
+  define dso_local signext i32 @test_MBB_dominated(i32 signext %ia, i32 signext %ib) {
+  entry:
+tail call void @llvm.ppc.MBB_dominated(i32 3, i32 3, i32 4)
+%cmp.not = icmp slt i32 %ia, %ib
+br i1 %cmp.not, label %cleanup, label %if.then
+  if.then:  ; preds = %entry
+%add = add nsw i32 %ia, 1
+%call = tail call signext i32 @callee(i32 signext %add, i32 signext %ib)
+%add1 = add nsw i32 %call, 1
+br label %cleanup
+  cleanup:  ; preds = %if.then, %entry
+%retval.0 = phi i32 [ %add1, %if.then ], [ 0, %entry ]
+ret i32 %retval.0
+  }
+  declare void @llvm.ppc.MBB_dominated(i32, i32, i32 immarg) #2
+...
+
+---
+name:callee
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+liveins: $x3, $x4
+%1:g8rc = COPY $x4
+%0:g8rc = COPY $x3
+%2:gprc = COPY %0.sub_32
+%3:gprc = COPY %1.sub_32
+%4:gprc = nsw ADD4 killed %3, killed %2
+%5:g8rc = EXTSW_32_64 killed %4
+$x3 = COPY %5
+BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+...
+
+---
+name:test_MBB_dominated
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+successors: %bb.2(0x4000), %bb.1(0x4000)
+liveins: $x3, $x4
+%3:g8rc = COPY $x4
+%2:g8rc = COPY $x3
+%5:gprc = COPY %3.sub_32
+%4:gprc_and_gprc_nor0 = COPY %2.sub_32
+%7:gprc = LI 3
+TW 4, %7, %7
+%6:gprc = LI 0
+%8:crrc = CMPW %4, %5
+BCC 12, killed %8, %bb.2
+B %bb.1
+  bb.1.if.then:
+successors: %bb.2(0x8000)
+%9:gprc = nsw ADDI %4, 1
+ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+%10:g8rc = EXTSW_32_64 %5
+%11:g8rc = EXTSW_32_64 killed %9
+$x3 = COPY %11
+$x4 = COPY %10
+BL8 @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit-def $r1, implicit-def $x3
+ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+%12:g8rc = COPY $x3
+%13:gprc_and_gprc_nor0 = COPY %12.sub_32
+%0:gprc = nsw ADDI killed %13, 1
+  bb.2.cleanup:
+%1:gprc = PHI %6, %bb.0, %0, %bb.1
+%14:g8rc = EXTSW_32_64 %1
+$x3 = COPY %14
+BLR8 implicit $lr8, implicit $rm, implicit $x3
+...
+# CHECK-MIR-LABEL: test_MBB_dominated
+# CHECK-MIR:   bb.0.entry:
+# CHECK-MIR:   successors: %bb.2(0x4000), %bb.1(0x4000)
+# CHECK-MIR:   liveins: $x3, $x4
+# CHECK-MIR:   %0:g8rc = COPY $x4
+# CHECK-MIR-NEXT:  %1:g8rc = COPY $x3
+# CHECK-MIR-NEXT:  %2:gprc = COPY %0.sub_32
+# CHECK-MIR-NEXT:  %3:gprc_and_gprc_nor0 = COPY %1.sub_32
+# CHECK-MIR-NEXT:  %4:gprc = LI 3
+# CHECK-MIR-NEXT:  %5:gprc = IMPLICIT_DEF
+# CHECK-MIR-NEXT:  %6:crrc = IMPLICIT_DEF
+# CHECK-MIR-NEXT:  TRAP
+
+# CHECK-MIR:   bb.1.if.then:
+# CHECK-MIR-NEXT:  successors: %bb.2(0x8000)
+# CHECK-MIR:   %7:gprc = nsw ADDI %3, 1
+# CHECK-MIR-NEXT:  ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+# CHECK-MIR-NEXT:  %8:g8rc = EXTSW_32_64 %2
+# CHECK-MIR-NEXT:  %9:g8rc = EXTSW_32_64 killed %7
+# CHECK-MIR-NEXT:  $x3 = COPY 

[PATCH] D117355: [PowerPC] Fix the undef virtual register reading failure for PPC backend trap optimization

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, amyk, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, hiraditya.
NeHuang requested review of this revision.

This patch adds the fix for undef virtual register reading failure when trap 
optimization is enabled.

Failure scenario as below:

1. In a machine basic block A, the definition of a virtual register MI was 
eliminated due to trap optimization (TRAP inserted before the MI)
2. The same virtual register is still used in another machine basic block B 
(dominated by A) will trigger undef vr reading failure

Idea of the fix

1. Detect and set all virtual register definition after the conditional trap to 
`IMPLICIT_DEF`
2. Remove all the other machine instructions after the conditional trap and 
change the terminator machine instruction to an unconditional trap


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117355

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/mi-peephole-trap-opt-dominated-block.mir

Index: llvm/test/CodeGen/PowerPC/mi-peephole-trap-opt-dominated-block.mir
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mi-peephole-trap-opt-dominated-block.mir
@@ -0,0 +1,142 @@
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes \
+# RUN:   -stop-after=ppc-mi-peepholes -ppc-opt-conditional-trap \
+# RUN:   | FileCheck --check-prefix=CHECK-MIR %s
+
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes \
+# RUN:   -ppc-opt-conditional-trap | FileCheck %s
+
+
+--- |
+  define dso_local signext i32 @callee(i32 signext %ic, i32 signext %id) {
+  entry:
+%add = add nsw i32 %id, %ic
+ret i32 %add
+  }
+  define dso_local signext i32 @test_MBB_dominated(i32 signext %ia, i32 signext %ib) {
+  entry:
+tail call void @llvm.ppc.MBB_dominated(i32 3, i32 3, i32 4)
+%cmp.not = icmp slt i32 %ia, %ib
+br i1 %cmp.not, label %cleanup, label %if.then
+  if.then:  ; preds = %entry
+%add = add nsw i32 %ia, 1
+%call = tail call signext i32 @callee(i32 signext %add, i32 signext %ib)
+%add1 = add nsw i32 %call, 1
+br label %cleanup
+  cleanup:  ; preds = %if.then, %entry
+%retval.0 = phi i32 [ %add1, %if.then ], [ 0, %entry ]
+ret i32 %retval.0
+  }
+  declare void @llvm.ppc.MBB_dominated(i32, i32, i32 immarg) #2
+...
+
+---
+name:callee
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+liveins: $x3, $x4
+%1:g8rc = COPY $x4
+%0:g8rc = COPY $x3
+%2:gprc = COPY %0.sub_32
+%3:gprc = COPY %1.sub_32
+%4:gprc = nsw ADD4 killed %3, killed %2
+%5:g8rc = EXTSW_32_64 killed %4
+$x3 = COPY %5
+BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+...
+
+---
+name:test_MBB_dominated
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+successors: %bb.2(0x4000), %bb.1(0x4000)
+liveins: $x3, $x4
+%3:g8rc = COPY $x4
+%2:g8rc = COPY $x3
+%5:gprc = COPY %3.sub_32
+%4:gprc_and_gprc_nor0 = COPY %2.sub_32
+%7:gprc = LI 3
+TW 4, %7, %7
+%6:gprc = LI 0
+%8:crrc = CMPW %4, %5
+BCC 12, killed %8, %bb.2
+B %bb.1
+  bb.1.if.then:
+successors: %bb.2(0x8000)
+%9:gprc = nsw ADDI %4, 1
+ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+%10:g8rc = EXTSW_32_64 %5
+%11:g8rc = EXTSW_32_64 killed %9
+$x3 = COPY %11
+$x4 = COPY %10
+BL8 @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit-def $r1, implicit-def $x3
+ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+%12:g8rc = COPY $x3
+%13:gprc_and_gprc_nor0 = COPY %12.sub_32
+%0:gprc = nsw ADDI killed %13, 1
+  bb.2.cleanup:
+%1:gprc = PHI %6, %bb.0, %0, %bb.1
+%14:g8rc = EXTSW_32_64 %1
+$x3 = COPY %14
+BLR8 implicit $lr8, implicit $rm, implicit $x3
+...
+# CHECK-MIR-LABEL: test_MBB_dominated
+# CHECK-MIR:   bb.0.entry:
+# CHECK-MIR:   successors: %bb.2(0x4000), %bb.1(0x4000)
+# CHECK-MIR:   liveins: $x3, $x4
+# CHECK-MIR:   %0:g8rc = COPY $x4
+# CHECK-MIR-NEXT:  %1:g8rc = COPY $x3
+# CHECK-MIR-NEXT:  %2:gprc = COPY %0.sub_32
+# CHECK-MIR-NEXT:  %3:gprc_and_gprc_nor0 = COPY %1.sub_32
+# CHECK-MIR-NEXT:  %4:gprc = LI 3
+# CHECK-MIR-NEXT:  %5:gprc = IMPLICIT_DEF
+# CHECK-MIR-NEXT:  %6:crrc = IMPLICIT_DEF
+# CHECK-MIR-NEXT:  TRAP
+
+# CHECK-MIR:   bb.1.if.then:
+# CHECK-MIR-NEXT:  successors: %bb.2(0x8000)
+# CHECK-MIR:   %7:gprc = nsw ADDI %3, 1
+# CHECK-MIR-NEXT:  ADJCALLSTACKDOWN 112, 0, 

[PATCH] D114088: [PowerPC] Add BCD add/sub/cmp builtins

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

-




Comment at: clang/lib/Headers/altivec.h:19050
+}
+
+static __inline__ long __bcdcmpeq(vector unsigned char __a,

Do we need to add a case for "__CR6_SO_REV"? It is defined in line 25 but not 
used.



Comment at: llvm/lib/Target/PowerPC/P10InstrResources.td:2078
 )>;
+

nit: unrelated change



Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:5096
+SubReg = PPC::sub_un;
+ShiftVal = 0;
+break;

can we remove this as default is 0?



Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:5100
+SubReg = PPC::sub_un;
+ShiftVal = 0;
+Reverse = true;

ditto


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[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

[Victor Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGae27ca9a6783: [PowerPC] PPC backend optimization on 
conditional trap intrustions (authored by NeHuang).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111434/new/

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Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir

Index: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
@@ -0,0 +1,747 @@
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s
+
+---
+name:conditional_trap_opt_reg_implicit_def
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = IMPLICIT_DEF
+%1:gprc = IMPLICIT_DEF
+%2:g8rc = IMPLICIT_DEF
+%3:g8rc = IMPLICIT_DEF
+TW 8, %0, %1
+TD 8, %2, %3
+TWI 24, %0, 0
+TDI 24, %2, 0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_reg_implicit_def
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  twgt3, 3
+  # CHECK-NEXT:  tdgt3, 3
+  # CHECK-NEXT:  twnei   3, 0
+  # CHECK-NEXT:  tdnei   3, 0
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_31
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 0
+TW 31, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_31
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_24
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 0
+TW 24, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_24
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_no_trap_TW_24
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 3
+TW 24, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_no_trap_TW_24
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_20
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 3
+TW 20, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_20
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_no_trap_TW_20
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 5
+TW 20, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_no_trap_TW_20
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_no_trap_TW_16
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TW 16, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_no_trap_TW_16
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_16
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TW 16, %1, %0
+TW 16, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_16
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_8
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 10
+TW 8, %1, %0
+TW 8, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_8
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_2
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 2
+TW 2, %1, %0
+TW 2, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_2
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_1
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -3
+%1:gprc = LI 4
+TW 1, %1, %0
+TW 1, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: 

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 387652.
NeHuang added a comment.

Addressed review comments


Repository:
  rG LLVM Github Monorepo

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Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir

Index: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
@@ -0,0 +1,747 @@
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s
+
+---
+name:conditional_trap_opt_reg_implicit_def
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = IMPLICIT_DEF
+%1:gprc = IMPLICIT_DEF
+%2:g8rc = IMPLICIT_DEF
+%3:g8rc = IMPLICIT_DEF
+TW 8, %0, %1
+TD 8, %2, %3
+TWI 24, %0, 0
+TDI 24, %2, 0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_reg_implicit_def
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  twgt3, 3
+  # CHECK-NEXT:  tdgt3, 3
+  # CHECK-NEXT:  twnei   3, 0
+  # CHECK-NEXT:  tdnei   3, 0
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_31
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 0
+TW 31, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_31
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_24
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 0
+TW 24, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_24
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_no_trap_TW_24
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 3
+TW 24, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_no_trap_TW_24
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_20
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 3
+TW 20, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_20
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_no_trap_TW_20
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 5
+TW 20, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_no_trap_TW_20
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_no_trap_TW_16
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TW 16, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_no_trap_TW_16
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_16
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TW 16, %1, %0
+TW 16, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_16
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_8
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 10
+TW 8, %1, %0
+TW 8, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_8
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_2
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 2
+TW 2, %1, %0
+TW 2, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_2
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_1
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -3
+%1:gprc = LI 4
+TW 1, %1, %0
+TW 1, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_1
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_4
+alignment:   

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

[Victor Huang via Phabricator via cfe-commits]

NeHuang marked 7 inline comments as done.
NeHuang added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1020
+// We can only do the optimization for the "reg + reg" form.
+if (!(LiMI1 && (Opcode1 == PPC::LI || Opcode1 == PPC::LI8)))
+  break;

amyk wrote:
> Do we still need to take into account of the lis+ori that Nemanja mentioned?
IIUC, the optimization will be triggered if the immediate is a s16Immediate. We 
had the similar check and conversion in this patch 
https://reviews.llvm.org/D112285 


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[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

[Victor Huang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
NeHuang marked 5 inline comments as done.
Closed by commit rG18fe0a0d9eb1: [PowerPC] PPC backend optimization to lower 
int_ppc_tdw/int_ppc_tw intrinsics… (authored by NeHuang).

Changed prior to commit:
  https://reviews.llvm.org/D112285?vs=384768=386517#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112285/new/

https://reviews.llvm.org/D112285

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -127,6 +127,213 @@
   ret void
 }
 
+; tw -> twi
+define dso_local void @test__twi_boundary_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twi_boundary_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, 32767
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 32767, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twi_boundary_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, 32767
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 32767, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary1_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, -32768
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 -32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary1_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, -32768
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 -32768, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary2_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, 0
+; CHECK-NEXT:ori r4, r4, 32768
+; CHECK-NEXT:tw 3, r3, r4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary2_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, 0
+; CHECK-NEXT:ori r4, r4, 32768
+; CHECK-NEXT:tw 3, r4, r3
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 32768, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary3_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, -1
+; CHECK-NEXT:ori r4, r4, 32767
+; CHECK-NEXT:tw 3, r3, r4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 -32769, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary3_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, -1
+; CHECK-NEXT:ori r4, r4, 32767
+; CHECK-NEXT:tw 3, r4, r3
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 -32769, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__twlgti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twlgti_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgti r3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 0, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twllti_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllti r3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 0, i32 %a, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twllti_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllti r3, 1
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 1, i32 2)
+  ret void
+}
+
+define dso_local void @test__twlgti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twlgti_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgti r3, 1
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 1, i32 %a, i32 2)
+  ret void
+}
+
+define dso_local void @test__tweqi_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tweqi_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweqi r3, 2
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 2, i32 4)
+  ret void
+}
+
+define dso_local void @test__tweqi_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tweqi_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweqi r3, 2
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 2, i32 %a, i32 4)
+  ret void
+}
+
+define dso_local void @test__twgti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twgti_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgti r3, 16
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 16, i32 8)
+  ret void
+}
+
+define 

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 385282.
NeHuang marked 3 inline comments as done.
NeHuang added a comment.

Address review comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111434/new/

https://reviews.llvm.org/D111434

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir

Index: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
@@ -0,0 +1,448 @@
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s
+
+---
+name:conditional_trap_opt_reg_implicit_def
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = IMPLICIT_DEF
+%1:gprc = IMPLICIT_DEF
+%2:g8rc = IMPLICIT_DEF
+%3:g8rc = IMPLICIT_DEF
+TW 8, %0, %1
+TD 8, %2, %3
+TWI 24, %0, 0
+TDI 24, %2, 0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_reg_implicit_def
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  twgt3, 3
+  # CHECK-NEXT:  tdgt3, 3
+  # CHECK-NEXT:  twnei   3, 0
+  # CHECK-NEXT:  tdnei   3, 0
+  # CHECK-NEXT:  blr
+---
+name:conditional_trap_opt_TW_31
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 0
+TW 31, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_31
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_16
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TW 16, %1, %0
+TW 16, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_16
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_8
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 10
+TW 8, %1, %0
+TW 8, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_8
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_2
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 2
+TW 2, %1, %0
+TW 2, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_2
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_1
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -3
+%1:gprc = LI 4
+TW 1, %1, %0
+TW 1, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_1
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_4
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TW 4, %1, %0
+TW 4, %1, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_4
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_31
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+TWI 31, %0, 0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_31
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_16
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TWI 16, %1, 5
+TWI 16, %0, 1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_16
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_8
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 10
+TWI 8, %1, -1
+TWI 8, %0, 10
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_8
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_2
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 2
+TWI 2, %1, -1
+TWI 2, %0, 2
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_2
+  # CHECK: # %bb.0: # 

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 384768.
NeHuang marked 3 inline comments as done.
NeHuang added a comment.

Address review comments from @nemanjai


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112285/new/

https://reviews.llvm.org/D112285

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -127,6 +127,213 @@
   ret void
 }
 
+; tw -> twi
+define dso_local void @test__twi_boundary_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twi_boundary_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, 32767
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 32767, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twi_boundary_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, 32767
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 32767, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary1_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, -32768
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 -32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary1_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, -32768
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 -32768, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary2_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, 0
+; CHECK-NEXT:ori r4, r4, 32768
+; CHECK-NEXT:tw 3, r3, r4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary2_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, 0
+; CHECK-NEXT:ori r4, r4, 32768
+; CHECK-NEXT:tw 3, r4, r3
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 32768, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary3_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, -1
+; CHECK-NEXT:ori r4, r4, 32767
+; CHECK-NEXT:tw 3, r3, r4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 -32769, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary3_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, -1
+; CHECK-NEXT:ori r4, r4, 32767
+; CHECK-NEXT:tw 3, r4, r3
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 -32769, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__twlgti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twlgti_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgti r3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 0, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twllti_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllti r3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 0, i32 %a, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twllti_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllti r3, 1
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 1, i32 2)
+  ret void
+}
+
+define dso_local void @test__twlgti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twlgti_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgti r3, 1
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 1, i32 %a, i32 2)
+  ret void
+}
+
+define dso_local void @test__tweqi_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tweqi_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweqi r3, 2
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 2, i32 4)
+  ret void
+}
+
+define dso_local void @test__tweqi_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tweqi_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweqi r3, 2
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 2, i32 %a, i32 4)
+  ret void
+}
+
+define dso_local void @test__twgti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twgti_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgti r3, 16
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 16, i32 8)
+  ret void
+}
+
+define dso_local void @test__twlti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twlti_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlti r3, 16
+; CHECK-NEXT:blr
+  call void 

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 384479.
NeHuang marked 5 inline comments as done.
NeHuang added a comment.

Addressed review comments from @amy


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -127,6 +127,213 @@
   ret void
 }
 
+; tw -> twi
+define dso_local void @test__twi_boundary_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twi_boundary_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, 32767
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 32767, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twi_boundary_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, 32767
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 32767, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary1_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, -32768
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 -32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary1_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, r3, -32768
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 -32768, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary2_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, 0
+; CHECK-NEXT:ori r4, r4, 32768
+; CHECK-NEXT:tw 3, r3, r4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary2_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, 0
+; CHECK-NEXT:ori r4, r4, 32768
+; CHECK-NEXT:tw 3, r4, r3
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 32768, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary3_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, -1
+; CHECK-NEXT:ori r4, r4, 32767
+; CHECK-NEXT:tw 3, r3, r4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 -32769, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary3_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis r4, -1
+; CHECK-NEXT:ori r4, r4, 32767
+; CHECK-NEXT:tw 3, r4, r3
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 -32769, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__twlgti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twlgti_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgti r3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 0, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twllti_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllti r3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 0, i32 %a, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twllti_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllti r3, 1
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 1, i32 2)
+  ret void
+}
+
+define dso_local void @test__twlgti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twlgti_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgti r3, 1
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 1, i32 %a, i32 2)
+  ret void
+}
+
+define dso_local void @test__tweqi_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tweqi_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweqi r3, 2
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 2, i32 4)
+  ret void
+}
+
+define dso_local void @test__tweqi_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tweqi_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweqi r3, 2
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 2, i32 %a, i32 4)
+  ret void
+}
+
+define dso_local void @test__twgti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twgti_reg_imm:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgti r3, 16
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 16, i32 8)
+  ret void
+}
+
+define dso_local void @test__twlti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twlti_imm_reg:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlti r3, 16
+; CHECK-NEXT:blr
+  call void 

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll:131
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdi 3, 3, 32767
+; CHECK-NEXT:blr

amyk wrote:
> amyk wrote:
> > nemanjai wrote:
> > > Can we add `-ppc-asm-full-reg-names` to the RUN lines so it is more clear 
> > > which operand is a register and which is an immediate. This works on AIX 
> > > now since https://reviews.llvm.org/D94282 landed.
> > Maybe it would be good to pre-commit the change with 
> > `-ppc-asm-full-reg-names` added to the run lines so then this patch can 
> > only contain the pertinent `td`/`tdi`/`tw`/`twi` changes.
> I meant, maybe it is a better idea to commit the test cases with 
> `-ppc-asm-full-reg-names` first, so then this revision does not contain the 
> additional updates of adding the registers in places that is not affected by 
> your patch. However, perhaps if Nemanja thinks adding the option to this 
> patch is OK, then that's fine with me, too. 
Good catch. Let me rebase this patch with ToT. The NFC patch was committed at 
40cad47fd82ecaf253ba9b11fcd34f67dd557e9d.


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[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 383506.
NeHuang added a comment.

Addressed review comments from @nemanjai  and @amyk


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112285/new/

https://reviews.llvm.org/D112285

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -1,19 +1,19 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
-; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
-; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
 
 ; tw
 declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
 define dso_local void @test__twlgt(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__twlgt:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:twlgt 3, 4
+; CHECK-NEXT:twlgt r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
   ret void
@@ -22,7 +22,7 @@
 define dso_local void @test__twllt(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__twllt:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:twllt 3, 4
+; CHECK-NEXT:twllt r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
   ret void
@@ -31,7 +31,7 @@
 define dso_local void @test__tw3(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__tw3:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:tw 3, 3, 4
+; CHECK-NEXT:tw 3, r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
   ret void
@@ -40,7 +40,7 @@
 define dso_local void @test__tweq(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__tweq:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:tweq r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
   ret void
@@ -49,7 +49,7 @@
 define dso_local void @test__twlge(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__twlge:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:tw 5, 3, 4
+; CHECK-NEXT:tw 5, r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
   ret void
@@ -58,7 +58,7 @@
 define dso_local void @test__twlle(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__twlle:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:tw 6, 3, 4
+; CHECK-NEXT:tw 6, r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
   ret void
@@ -67,7 +67,7 @@
 define dso_local void @test__twgt(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__twgt:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:twgt 3, 4
+; CHECK-NEXT:twgt r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
   ret void
@@ -76,7 +76,7 @@
 define dso_local void @test__twge(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__twge:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:tw 12, 3, 4
+; CHECK-NEXT:tw 12, r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
   ret void
@@ -85,7 +85,7 @@
 define dso_local void @test__twlt(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__twlt:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:twlt 3, 4
+; CHECK-NEXT:twlt r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
   ret void
@@ -94,7 +94,7 @@
 define dso_local void @test__twle(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__twle:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:tw 20, 3, 4
+; CHECK-NEXT:tw 20, r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
   ret void
@@ -103,7 +103,7 @@
 define dso_local void @test__twne24(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__twne24:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:twne r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
   ret void
@@ -112,7 +112,7 @@
 define dso_local void @test__twu(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__twu:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:twu 3, 4
+; CHECK-NEXT:twu r3, r4
 ; CHECK-NEXT:blr
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
   ret void
@@ -121,18 +121,225 @@
 define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
 ; CHECK-LABEL: test__tw_no_match:
 ; CHECK:   # %bb.0:
-; 

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

gentle ping


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[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, hiraditya.
NeHuang requested review of this revision.

This patch adds the backend optimization to match XL behavior for the two 
builtins `__tdw` and `__tw` that when the second input argument is an 
immediate, emitting `tdi`/`twi` instructions instead of `td`/`tw`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112285

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -127,6 +127,110 @@
   ret void
 }
 
+; tw -> twi
+define dso_local void @test__twi_boundary(i32 %a) {
+; CHECK-LABEL: test__twi_boundary:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, 3, 32767
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 32767, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary1(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twi 3, 3, -32768
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 -32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary2(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis 4, 0
+; CHECK-NEXT:ori 4, 4, 32768
+; CHECK-NEXT:tw 3, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary3(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lis 4, -1
+; CHECK-NEXT:ori 4, 4, 32767
+; CHECK-NEXT:tw 3, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 -32769, i32 3)
+  ret void
+}
+
+define dso_local void @test__twlgti(i32 %a) {
+; CHECK-LABEL: test__twlgti:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgti 3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 0, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllti(i32 %a) {
+; CHECK-LABEL: test__twllti:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllti 3, 1
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 1, i32 2)
+  ret void
+}
+
+define dso_local void @test__tweqi(i32 %a) {
+; CHECK-LABEL: test__tweqi:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweqi 3, 2
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 2, i32 4)
+  ret void
+}
+
+define dso_local void @test__twgti(i32 %a) {
+; CHECK-LABEL: test__twgti:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgti 3, 16
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 16, i32 8)
+  ret void
+}
+
+define dso_local void @test__twlti(i32 %a) {
+; CHECK-LABEL: test__twlti:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlti 3, 64
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 64, i32 16)
+  ret void
+}
+
+define dso_local void @test__twnei(i32 %a) {
+; CHECK-LABEL: test__twnei:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twnei 3, 256
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 256, i32 24)
+  ret void
+}
+
+define dso_local void @test__twui(i32 %a) {
+; CHECK-LABEL: test__twui:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twui 3, 512
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 512, i32 31)
+  ret void
+}
+
 ; trap
 declare void @llvm.ppc.trap(i32 %a)
 define dso_local void @test__trap(i32 %a) {
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
@@ -124,6 +124,110 @@
   ret void
 }
 
+; tdw -> tdi
+define dso_local void @test__tdi_boundary(i64 %a) {
+; CHECK-LABEL: test__tdi_boundary:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdi 3, 3, 32767
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tdw(i64 %a, i64 32767, i32 3)
+  ret void
+}
+
+define dso_local void @test__tdi_boundary1(i64 %a) {
+; CHECK-LABEL: test__tdi_boundary1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdi 3, 3, -32768
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tdw(i64 %a, i64 -32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__td_boundary2(i64 %a) {
+; CHECK-LABEL: test__td_boundary2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:ori 4, 4, 32768
+; CHECK-NEXT:td 3, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tdw(i64 %a, i64 32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__td_boundary3(i64 %a) {
+; CHECK-LABEL: test__td_boundary3:
+; CHECK:   # %bb.0:
+; 

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

gentle ping


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[PATCH] D111229: [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter

[Victor Huang via Phabricator via cfe-commits]

NeHuang accepted this revision as: NeHuang.
NeHuang added a comment.
This revision is now accepted and ready to land.

Thanks. LGTM. One minor can be addressed when commit it.




Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c:71
+
+  /*shift = 31, mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 0x1FF);

please remove `shift = 31,` in the comment 


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[PATCH] D111229: [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

Please check and add a test  in 
`clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c` with `shift` as a variable.


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[PATCH] D111229: [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-error.c:46
   unsigned int mask;
-  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
+  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7);
   res = __builtin_ppc_rlwnm(ui, 31, mask);  // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}

Please also remove `__builtin_ppc_rlwnm(ui, shift, 7);` in this test. We only 
keep cases trigger sema check errors.


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[PATCH] D110935: [NFC] Update vec_extract builtin signatures to take signed int.

[Victor Huang via Phabricator via cfe-commits]

NeHuang accepted this revision as: NeHuang.
NeHuang added a comment.
This revision is now accepted and ready to land.

LTGM


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[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 378284.
NeHuang added a comment.

clang-format


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Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir

Index: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
@@ -0,0 +1,448 @@
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s
+
+---
+name:conditional_trap_opt_reg_implicit_def
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = IMPLICIT_DEF
+%1:gprc = IMPLICIT_DEF
+%2:g8rc = IMPLICIT_DEF
+%3:g8rc = IMPLICIT_DEF
+TW 8, %0, %1
+TD 8, %2, %3
+TWI 24, %0, 0
+TDI 24, %2, 0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_reg_implicit_def
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  twgt3, 3
+  # CHECK-NEXT:  tdgt3, 3
+  # CHECK-NEXT:  twnei   3, 0
+  # CHECK-NEXT:  tdnei   3, 0
+  # CHECK-NEXT:  blr
+---
+name:conditional_trap_opt_TW_31
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 0
+TW 31, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_31
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_16
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TW 16, %1, %0
+TW 16, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_16
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_8
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 10
+TW 8, %1, %0
+TW 8, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_8
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_2
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 2
+TW 2, %1, %0
+TW 2, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_2
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_1
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -3
+%1:gprc = LI 4
+TW 1, %1, %0
+TW 1, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_1
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_4
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TW 4, %1, %0
+TW 4, %1, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_4
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_31
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+TWI 31, %0, 0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_31
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_16
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TWI 16, %1, 5
+TWI 16, %0, 1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_16
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_8
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 10
+TWI 8, %1, -1
+TWI 8, %0, 10
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_8
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_2
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 2
+TWI 2, %1, -1
+TWI 2, %0, 2
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_2
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, PowerPC.
NeHuang added projects: LLVM, PowerPC.
Herald added subscribers: shchenz, JDevlieghere, kbarton, hiraditya.
NeHuang requested review of this revision.

This patch adds PPC back end optimization to analyze the arguments of a 
conditional trap instruction to execute one of the following

- Delete it if the condition is never true
- Replace it with an unconditional trap if the condition is always true
- Otherwise keep it


Repository:
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https://reviews.llvm.org/D111434

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir

Index: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
@@ -0,0 +1,448 @@
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s
+
+---
+name:conditional_trap_opt_reg_implicit_def
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = IMPLICIT_DEF
+%1:gprc = IMPLICIT_DEF
+%2:g8rc = IMPLICIT_DEF
+%3:g8rc = IMPLICIT_DEF
+TW 8, %0, %1
+TD 8, %2, %3
+TWI 24, %0, 0
+TDI 24, %2, 0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_reg_implicit_def
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  twgt3, 3
+  # CHECK-NEXT:  tdgt3, 3
+  # CHECK-NEXT:  twnei   3, 0
+  # CHECK-NEXT:  tdnei   3, 0
+  # CHECK-NEXT:  blr
+---
+name:conditional_trap_opt_TW_31
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+%1:gprc = LI 0
+TW 31, %1, %0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_31
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_16
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TW 16, %1, %0
+TW 16, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_16
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_8
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 10
+TW 8, %1, %0
+TW 8, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_8
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_2
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 2
+TW 2, %1, %0
+TW 2, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_2
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_1
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -3
+%1:gprc = LI 4
+TW 1, %1, %0
+TW 1, %0, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_1
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TW_4
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TW 4, %1, %0
+TW 4, %1, %1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TW_4
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_31
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 3
+TWI 31, %0, 0
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_31
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_16
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI 5
+%1:gprc = LI 1
+TWI 16, %1, 5
+TWI 16, %0, 1
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_16
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:conditional_trap_opt_TWI_8
+alignment:   16
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+%0:gprc = LI -1
+%1:gprc = LI 10
+TWI 8, %1, -1
+TWI 8, %0, 10
+BLR8 implicit $lr8, implicit $rm
+...
+  # CHECK-LABEL: conditional_trap_opt_TWI_8
+  # CHECK: # %bb.0: # %entry
+  # CHECK-NEXT:  trap
+  # CHECK-NEXT:  blr
+
+---
+name:

[PATCH] D108823: [PowerPC] Mark splat immediate instructions as rematerializable

[Victor Huang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6e1aaf18af6c: [PowerPC] Mark splat immediate instructions as 
rematerializable (authored by NeHuang).

Changed prior to commit:
  https://reviews.llvm.org/D108823?vs=369101=374892#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108823/new/

https://reviews.llvm.org/D108823

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/constant-pool.ll
  llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
  llvm/test/CodeGen/PowerPC/p10-splatImm.ll

Index: llvm/test/CodeGen/PowerPC/p10-splatImm.ll
===
--- llvm/test/CodeGen/PowerPC/p10-splatImm.ll
+++ llvm/test/CodeGen/PowerPC/p10-splatImm.ll
@@ -249,7 +249,6 @@
 ; CHECK-LABEL: testFloatScalar:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:xxspltidp vs1, 1135290941
-; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:blr
 
 entry:
@@ -270,7 +269,6 @@
 ; CHECK-LABEL: testDoubleRepresentableScalar:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:xxspltidp vs1, 1135290941
-; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
===
--- llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
+++ llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
@@ -35,8 +35,7 @@
 
 define dso_local void @P10_Spill_CR_UN(%2* %arg, %1* %arg1, i32 %arg2) local_unnamed_addr {
 ; CHECK-LABEL: P10_Spill_CR_UN:
-; CHECK: .localentry P10_Spill_CR_UN, 1
-; CHECK-NEXT:  # %bb.0: # %bb
+; CHECK:   # %bb.0: # %bb
 ; CHECK-NEXT:mflr r0
 ; CHECK-NEXT:mfcr r12
 ; CHECK-NEXT:std r0, 16(r1)
@@ -146,19 +145,19 @@
 ; CHECK-NEXT:# implicit-def: $r3
 ; CHECK-NEXT:  .LBB0_15: # %bb50
 ; CHECK-NEXT:li r4, 0
-; CHECK-NEXT:xxspltidp vs3, -1082130432
 ; CHECK-NEXT:extsh r9, r3
 ; CHECK-NEXT:extsw r6, r28
 ; CHECK-NEXT:li r5, 0
+; CHECK-NEXT:xxspltidp vs3, -1082130432
+; CHECK-NEXT:xxspltidp vs4, -1082130432
 ; CHECK-NEXT:std r30, 104(r1)
 ; CHECK-NEXT:std r29, 96(r1)
 ; CHECK-NEXT:li r7, 0
 ; CHECK-NEXT:li r8, 0
 ; CHECK-NEXT:li r10, 0
-; CHECK-NEXT:fmr f4, f3
-; CHECK-NEXT:xxlxor f1, f1, f1
 ; CHECK-NEXT:std r4, 152(r1)
 ; CHECK-NEXT:li r4, -1
+; CHECK-NEXT:xxlxor f1, f1, f1
 ; CHECK-NEXT:std r4, 112(r1)
 ; CHECK-NEXT:li r4, 1024
 ; CHECK-NEXT:bl call_4@notoc
@@ -304,19 +303,19 @@
 ; CHECK-BE-NEXT:# implicit-def: $r3
 ; CHECK-BE-NEXT:  .LBB0_15: # %bb50
 ; CHECK-BE-NEXT:li r4, 0
-; CHECK-BE-NEXT:xxspltidp vs3, -1082130432
 ; CHECK-BE-NEXT:extsh r9, r3
 ; CHECK-BE-NEXT:extsw r6, r28
 ; CHECK-BE-NEXT:li r5, 0
+; CHECK-BE-NEXT:xxspltidp vs3, -1082130432
+; CHECK-BE-NEXT:xxspltidp vs4, -1082130432
 ; CHECK-BE-NEXT:std r30, 120(r1)
 ; CHECK-BE-NEXT:std r29, 112(r1)
 ; CHECK-BE-NEXT:li r7, 0
 ; CHECK-BE-NEXT:li r8, 0
 ; CHECK-BE-NEXT:li r10, 0
-; CHECK-BE-NEXT:fmr f4, f3
-; CHECK-BE-NEXT:xxlxor f1, f1, f1
 ; CHECK-BE-NEXT:std r4, 168(r1)
 ; CHECK-BE-NEXT:li r4, -1
+; CHECK-BE-NEXT:xxlxor f1, f1, f1
 ; CHECK-BE-NEXT:std r4, 128(r1)
 ; CHECK-BE-NEXT:li r4, 1024
 ; CHECK-BE-NEXT:bl call_4
Index: llvm/test/CodeGen/PowerPC/constant-pool.ll
===
--- llvm/test/CodeGen/PowerPC/constant-pool.ll
+++ llvm/test/CodeGen/PowerPC/constant-pool.ll
@@ -364,15 +364,15 @@
 ; CHECK-NEXT:.cfi_def_cfa_offset 48
 ; CHECK-NEXT:.cfi_offset lr, 16
 ; CHECK-NEXT:.cfi_offset v31, -16
+; CHECK-NEXT:xxlxor f4, f4, f4
+; CHECK-NEXT:xxsplti32dx vs3, 0, 1074935889
 ; CHECK-NEXT:stxv vs63, 32(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:xxsplti32dx vs63, 0, 1074935889
-; CHECK-NEXT:xxlxor f4, f4, f4
-; CHECK-NEXT:xxlor vs3, vs63, vs63
 ; CHECK-NEXT:xxsplti32dx vs3, 1, -343597384
 ; CHECK-NEXT:# kill: def $f3 killed $f3 killed $vsl3
 ; CHECK-NEXT:bl __gcc_qadd@notoc
-; CHECK-NEXT:xxlor vs3, vs63, vs63
 ; CHECK-NEXT:xxlxor f4, f4, f4
+; CHECK-NEXT:xxsplti32dx vs3, 0, 1074935889
 ; CHECK-NEXT:xxsplti32dx vs3, 1, -1719329096
 ; CHECK-NEXT:# kill: def $f3 killed $f3 killed $vsl3
 ; CHECK-NEXT:bl __gcc_qadd@notoc
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1854,15 +1854,6 @@
 }
 
 let Predicates = [PrefixInstrs] in {
-  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
- (ins i32imm:$IMM32),
- "xxspltiw $XT, $IMM32", IIC_VecGeneral,
- 

[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/test/Sema/ppc-mma-builtins.c:1
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -target-feature -mma -fsyntax-only %s -verify

can you please add  `// REQUIRES: powerpc-registered-target`  for the ppc 
specific test?


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[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

Do we already have a backend test case for `fdiv` emitting a software estimate 
when `-Ofast` is used?


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[PATCH] D110273: [PowerPC] Fix lharx and lbarx builtin signatures

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:27
 
 char test_lbarx(volatile unsigned char *a) {
   // CHECK-LABEL: @test_lbarx

Do you also need to update the input argument type here as well to match the 
changes in `BuiltinsPPC.def`?


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[PATCH] D108302: [PowerPC] Fixed the crash due to early if conversion with fixed CR fields.

[Victor Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4a226529e2cf: [PowerPC] Fixed the crash due to early if 
conversion with fixed CR fields (authored by NeHuang).

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Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll


Index: llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 
-verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 
-verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr9 
-verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-64
+; RUN: llc < %s -mtriple=powerpc-unknown-aix -mcpu=pwr9 -verify-machineinstrs 
| FileCheck %s --check-prefix=CHECK-AIX-32
+
+define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) 
local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-NEXT:bge 6, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %land.rhs
+; CHECK-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-NEXT:mfocrf 3, 2
+; CHECK-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-64-LABEL: test:
+; CHECK-AIX-64:   # %bb.0: # %entry
+; CHECK-AIX-64-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-AIX-64-NEXT:bge 6, L..BB0_2
+; CHECK-AIX-64-NEXT:  # %bb.1: # %land.rhs
+; CHECK-AIX-64-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-AIX-64-NEXT:mfocrf 3, 2
+; CHECK-AIX-64-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-AIX-64-NEXT:clrldi 3, 3, 32
+; CHECK-AIX-64-NEXT:blr
+; CHECK-AIX-64-NEXT:  L..BB0_2:
+; CHECK-AIX-64-NEXT:li 3, 0
+; CHECK-AIX-64-NEXT:blr
+;
+; CHECK-AIX-32-LABEL: test:
+; CHECK-AIX-32:   # %bb.0: # %entry
+; CHECK-AIX-32-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-AIX-32-NEXT:bge 6, L..BB0_2
+; CHECK-AIX-32-NEXT:  # %bb.1: # %land.rhs
+; CHECK-AIX-32-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-AIX-32-NEXT:mfocrf 3, 2
+; CHECK-AIX-32-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-AIX-32-NEXT:blr
+; CHECK-AIX-32-NEXT:  L..BB0_2:
+; CHECK-AIX-32-NEXT:li 3, 0
+; CHECK-AIX-32-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x 
i32> %b)
+  %tobool.not = icmp eq i32 %0, 0
+  br i1 %tobool.not, label %land.end, label %land.rhs
+
+land.rhs: ; preds = %entry
+  %1 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %c, <4 x 
i32> %b)
+  %tobool1 = icmp ne i32 %1, 0
+  %phi.cast = zext i1 %tobool1 to i32
+  br label %land.end
+
+land.end: ; preds = %land.rhs, %entry
+  %2 = phi i32 [ 0, %entry ], [ %phi.cast, %land.rhs ]
+  ret i32 %2
+}
+
+declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1541,6 +1541,11 @@
   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
 return false;
 
+  // If the conditional branch uses a physical register, then it cannot be
+  // turned into a select.
+  if (Register::isPhysicalRegister(Cond[1].getReg()))
+return false;
+
   // Check register classes.
   const MachineRegisterInfo  = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *RC =


Index: llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr9 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-64
+; RUN: llc < %s -mtriple=powerpc-unknown-aix -mcpu=pwr9 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-32
+
+define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-NEXT:bge 6, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %land.rhs
+; CHECK-NEXT:vcmpgtsw. 2, 4, 

[PATCH] D109178: [PowerPC] Disable vector types when not supported by subtarget features

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-int128.c:4
+// RUN:   -triple powerpc64-unknown-unknown -target-cpu pwr8 \
+// RUN:  -emit-llvm %s -o - -U__XL_COMPAT_ALTIVEC__ | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \

nit: indentation 



Comment at: clang/test/Parser/altivec.c:92
 // These should have errors.
+#ifndef __VSX__
 __vector double vv_d1;   // expected-error {{use of 'double' with 
'__vector' requires VSX support to be enabled (available on POWER7 or later)}}

Will this patch also impact `vector double`?   If not, can we move `#ifndef 
__VSX__` down below `vector double v_d2;`?  



Comment at: clang/test/Parser/cxx-altivec.cpp:91
 
-// These should have errors.
+#ifndef __VSX__
+// These should have errors for non pwr7 vsx builds.

same as above.


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[PATCH] D108302: [PowerPC] Fixed the crash due to early if conversion with fixed CR fields.

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 370428.
NeHuang added a comment.

Address review comments

- typo update
- use proper mcpu in the test case.


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Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll


Index: llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 
-verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 
-verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr9 
-verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-64
+; RUN: llc < %s -mtriple=powerpc-unknown-aix -mcpu=pwr9 -verify-machineinstrs 
| FileCheck %s --check-prefix=CHECK-AIX-32
+
+define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) 
local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-NEXT:bge 6, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %land.rhs
+; CHECK-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-NEXT:mfocrf 3, 2
+; CHECK-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-64-LABEL: test:
+; CHECK-AIX-64:   # %bb.0: # %entry
+; CHECK-AIX-64-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-AIX-64-NEXT:bge 6, L..BB0_2
+; CHECK-AIX-64-NEXT:  # %bb.1: # %land.rhs
+; CHECK-AIX-64-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-AIX-64-NEXT:mfocrf 3, 2
+; CHECK-AIX-64-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-AIX-64-NEXT:clrldi 3, 3, 32
+; CHECK-AIX-64-NEXT:blr
+; CHECK-AIX-64-NEXT:  L..BB0_2:
+; CHECK-AIX-64-NEXT:li 3, 0
+; CHECK-AIX-64-NEXT:blr
+;
+; CHECK-AIX-32-LABEL: test:
+; CHECK-AIX-32:   # %bb.0: # %entry
+; CHECK-AIX-32-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-AIX-32-NEXT:bge 6, L..BB0_2
+; CHECK-AIX-32-NEXT:  # %bb.1: # %land.rhs
+; CHECK-AIX-32-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-AIX-32-NEXT:mfocrf 3, 2
+; CHECK-AIX-32-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-AIX-32-NEXT:blr
+; CHECK-AIX-32-NEXT:  L..BB0_2:
+; CHECK-AIX-32-NEXT:li 3, 0
+; CHECK-AIX-32-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x 
i32> %b)
+  %tobool.not = icmp eq i32 %0, 0
+  br i1 %tobool.not, label %land.end, label %land.rhs
+
+land.rhs: ; preds = %entry
+  %1 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %c, <4 x 
i32> %b)
+  %tobool1 = icmp ne i32 %1, 0
+  %phi.cast = zext i1 %tobool1 to i32
+  br label %land.end
+
+land.end: ; preds = %land.rhs, %entry
+  %2 = phi i32 [ 0, %entry ], [ %phi.cast, %land.rhs ]
+  ret i32 %2
+}
+
+declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1541,6 +1541,11 @@
   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
 return false;
 
+  // If the conditional branch uses a physical register, then it cannot be
+  // turned into a select.
+  if (Register::isPhysicalRegister(Cond[1].getReg()))
+return false;
+
   // Check register classes.
   const MachineRegisterInfo  = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *RC =


Index: llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr9 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-64
+; RUN: llc < %s -mtriple=powerpc-unknown-aix -mcpu=pwr9 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-32
+
+define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-NEXT:bge 6, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %land.rhs
+; CHECK-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-NEXT:mfocrf 3, 2
+; CHECK-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-NEXT:clrldi 3, 3, 32
+; 

[PATCH] D108302: [PowerPC] Fixed the crash due to early if conversion with fixed CR fields.

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 369531.
NeHuang added a comment.

Address review comment.


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Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll


Index: llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 
-verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 
-verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr7 
-verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-64
+; RUN: llc < %s -mtriple=powerpc-unknown-aix -mcpu=pwr7 -verify-machineinstrs 
| FileCheck %s --check-prefix=CHECK-AIX-32
+
+define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) 
local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-NEXT:bge 6, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %land.rhs
+; CHECK-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-NEXT:mfocrf 3, 2
+; CHECK-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-64-LABEL: test:
+; CHECK-AIX-64:   # %bb.0: # %entry
+; CHECK-AIX-64-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-AIX-64-NEXT:bge 6, L..BB0_2
+; CHECK-AIX-64-NEXT:  # %bb.1: # %land.rhs
+; CHECK-AIX-64-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-AIX-64-NEXT:mfocrf 3, 2
+; CHECK-AIX-64-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-AIX-64-NEXT:clrldi 3, 3, 32
+; CHECK-AIX-64-NEXT:blr
+; CHECK-AIX-64-NEXT:  L..BB0_2:
+; CHECK-AIX-64-NEXT:li 3, 0
+; CHECK-AIX-64-NEXT:blr
+;
+; CHECK-AIX-32-LABEL: test:
+; CHECK-AIX-32:   # %bb.0: # %entry
+; CHECK-AIX-32-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-AIX-32-NEXT:bge 6, L..BB0_2
+; CHECK-AIX-32-NEXT:  # %bb.1: # %land.rhs
+; CHECK-AIX-32-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-AIX-32-NEXT:mfocrf 3, 2
+; CHECK-AIX-32-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-AIX-32-NEXT:blr
+; CHECK-AIX-32-NEXT:  L..BB0_2:
+; CHECK-AIX-32-NEXT:li 3, 0
+; CHECK-AIX-32-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x 
i32> %b)
+  %tobool.not = icmp eq i32 %0, 0
+  br i1 %tobool.not, label %land.end, label %land.rhs
+
+land.rhs: ; preds = %entry
+  %1 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %c, <4 x 
i32> %b)
+  %tobool1 = icmp ne i32 %1, 0
+  %phi.cast = zext i1 %tobool1 to i32
+  br label %land.end
+
+land.end: ; preds = %land.rhs, %entry
+  %2 = phi i32 [ 0, %entry ], [ %phi.cast, %land.rhs ]
+  ret i32 %2
+}
+
+declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1541,6 +1541,11 @@
   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
 return false;
 
+  // If the condition branch uses a physical register, then it cannot be turned
+  // into a select.
+  if (Register::isPhysicalRegister(Cond[1].getReg()))
+return false;
+
   // Check register classes.
   const MachineRegisterInfo  = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *RC =


Index: llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr7 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-64
+; RUN: llc < %s -mtriple=powerpc-unknown-aix -mcpu=pwr7 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-32
+
+define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-NEXT:bge 6, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %land.rhs
+; CHECK-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-NEXT:mfocrf 3, 2
+; CHECK-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+; CHECK-NEXT:  .LBB0_2:
+; 

[PATCH] D108702: [PowerPC][NFC] Rename P10 builtins vec_clrl, vec_clrr to vec_clr_first and vec_clr_last

[Victor Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2e5c17d19e37: [PowerPC][NFC] Rename P10 builtins vec_clrl, 
vec_clrr to vec_clr_first and… (authored by NeHuang).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108702/new/

https://reviews.llvm.org/D108702

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c


Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -732,36 +732,36 @@
   return vec_genpcvm(vulla, 0);
 }
 
-vector signed char test_vec_vclrl_sc(void) {
+vector signed char test_vec_clr_first_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrl(vsca, uia);
+  return vec_clr_first(vsca, uia);
 }
 
-vector unsigned char test_vec_clrl_uc(void) {
+vector unsigned char test_vec_clr_first_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrl(vuca, uia);
+  return vec_clr_first(vuca, uia);
 }
 
-vector signed char test_vec_vclrr_sc(void) {
+vector signed char test_vec_clr_last_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrr(vsca, uia);
+  return vec_clr_last(vsca, uia);
 }
 
-vector unsigned char test_vec_clrr_uc(void) {
+vector unsigned char test_vec_clr_last_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrr(vuca, uia);
+  return vec_clr_last(vuca, uia);
 }
 
 vector unsigned long long test_vclzdm(void) {
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -18312,10 +18312,10 @@
: __builtin_vsx_xxgenpcvdm((__a), (int)(__imm)))
 #endif /* __VSX__ */
 
-/* vec_clrl */
+/* vec_clr_first */
 
 static __inline__ vector signed char __ATTRS_o_ai
-vec_clrl(vector signed char __a, unsigned int __n) {
+vec_clr_first(vector signed char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrrb(__a, __n);
 #else
@@ -18324,7 +18324,7 @@
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
-vec_clrl(vector unsigned char __a, unsigned int __n) {
+vec_clr_first(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrrb((vector signed char)__a, __n);
 #else
@@ -18332,10 +18332,10 @@
 #endif
 }
 
-/* vec_clrr */
+/* vec_clr_last */
 
 static __inline__ vector signed char __ATTRS_o_ai
-vec_clrr(vector signed char __a, unsigned int __n) {
+vec_clr_last(vector signed char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrlb(__a, __n);
 #else
@@ -18344,7 +18344,7 @@
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
-vec_clrr(vector unsigned char __a, unsigned int __n) {
+vec_clr_last(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrlb((vector signed char)__a, __n);
 #else


Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -732,36 +732,36 @@
   return vec_genpcvm(vulla, 0);
 }
 
-vector signed char test_vec_vclrl_sc(void) {
+vector signed char test_vec_clr_first_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrl(vsca, uia);
+  return vec_clr_first(vsca, uia);
 }
 
-vector unsigned char test_vec_clrl_uc(void) {
+vector unsigned char test_vec_clr_first_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrl(vuca, uia);
+  return vec_clr_first(vuca, uia);
 }
 
-vector signed char test_vec_vclrr_sc(void) {
+vector signed char test_vec_clr_last_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrr(vsca, uia);
+  return vec_clr_last(vsca, uia);
 }
 
-vector unsigned char test_vec_clrr_uc(void) {

[PATCH] D108823: [PowerPC] Mark splat immediate instructions as rematerializable

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, lei, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, hiraditya, qcolombet.
NeHuang requested review of this revision.

This patch marks splat immediate instructions `XXSPLTIDP` and `XXSPLTI32DX` as 
rematerializable to prevent MachineLICM from moving them out of loops.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108823

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/constant-pool.ll
  llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
  llvm/test/CodeGen/PowerPC/p10-splatImm.ll

Index: llvm/test/CodeGen/PowerPC/p10-splatImm.ll
===
--- llvm/test/CodeGen/PowerPC/p10-splatImm.ll
+++ llvm/test/CodeGen/PowerPC/p10-splatImm.ll
@@ -249,7 +249,6 @@
 ; CHECK-LABEL: testFloatScalar:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:xxspltidp vs1, 1135290941
-; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:blr
 
 entry:
@@ -270,7 +269,6 @@
 ; CHECK-LABEL: testDoubleRepresentableScalar:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:xxspltidp vs1, 1135290941
-; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
===
--- llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
+++ llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
@@ -35,8 +35,7 @@
 
 define dso_local void @P10_Spill_CR_UN(%2* %arg, %1* %arg1, i32 %arg2) local_unnamed_addr {
 ; CHECK-LABEL: P10_Spill_CR_UN:
-; CHECK: .localentry P10_Spill_CR_UN, 1
-; CHECK-NEXT:  # %bb.0: # %bb
+; CHECK:   # %bb.0: # %bb
 ; CHECK-NEXT:mflr r0
 ; CHECK-NEXT:mfcr r12
 ; CHECK-NEXT:std r0, 16(r1)
@@ -146,19 +145,19 @@
 ; CHECK-NEXT:# implicit-def: $r3
 ; CHECK-NEXT:  .LBB0_15: # %bb50
 ; CHECK-NEXT:li r4, 0
-; CHECK-NEXT:xxspltidp vs3, -1082130432
 ; CHECK-NEXT:extsh r9, r3
 ; CHECK-NEXT:extsw r6, r28
 ; CHECK-NEXT:li r5, 0
+; CHECK-NEXT:xxspltidp vs3, -1082130432
+; CHECK-NEXT:xxspltidp vs4, -1082130432
 ; CHECK-NEXT:std r30, 104(r1)
 ; CHECK-NEXT:std r29, 96(r1)
 ; CHECK-NEXT:li r7, 0
 ; CHECK-NEXT:li r8, 0
 ; CHECK-NEXT:li r10, 0
-; CHECK-NEXT:fmr f4, f3
-; CHECK-NEXT:xxlxor f1, f1, f1
 ; CHECK-NEXT:std r4, 152(r1)
 ; CHECK-NEXT:li r4, -1
+; CHECK-NEXT:xxlxor f1, f1, f1
 ; CHECK-NEXT:std r4, 112(r1)
 ; CHECK-NEXT:li r4, 1024
 ; CHECK-NEXT:bl call_4@notoc
@@ -304,19 +303,19 @@
 ; CHECK-BE-NEXT:# implicit-def: $r3
 ; CHECK-BE-NEXT:  .LBB0_15: # %bb50
 ; CHECK-BE-NEXT:li r4, 0
-; CHECK-BE-NEXT:xxspltidp vs3, -1082130432
 ; CHECK-BE-NEXT:extsh r9, r3
 ; CHECK-BE-NEXT:extsw r6, r28
 ; CHECK-BE-NEXT:li r5, 0
+; CHECK-BE-NEXT:xxspltidp vs3, -1082130432
+; CHECK-BE-NEXT:xxspltidp vs4, -1082130432
 ; CHECK-BE-NEXT:std r30, 120(r1)
 ; CHECK-BE-NEXT:std r29, 112(r1)
 ; CHECK-BE-NEXT:li r7, 0
 ; CHECK-BE-NEXT:li r8, 0
 ; CHECK-BE-NEXT:li r10, 0
-; CHECK-BE-NEXT:fmr f4, f3
-; CHECK-BE-NEXT:xxlxor f1, f1, f1
 ; CHECK-BE-NEXT:std r4, 168(r1)
 ; CHECK-BE-NEXT:li r4, -1
+; CHECK-BE-NEXT:xxlxor f1, f1, f1
 ; CHECK-BE-NEXT:std r4, 128(r1)
 ; CHECK-BE-NEXT:li r4, 1024
 ; CHECK-BE-NEXT:bl call_4
Index: llvm/test/CodeGen/PowerPC/constant-pool.ll
===
--- llvm/test/CodeGen/PowerPC/constant-pool.ll
+++ llvm/test/CodeGen/PowerPC/constant-pool.ll
@@ -364,15 +364,15 @@
 ; CHECK-NEXT:.cfi_def_cfa_offset 48
 ; CHECK-NEXT:.cfi_offset lr, 16
 ; CHECK-NEXT:.cfi_offset v31, -16
+; CHECK-NEXT:xxlxor f4, f4, f4
+; CHECK-NEXT:xxsplti32dx vs3, 0, 1074935889
 ; CHECK-NEXT:stxv vs63, 32(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:xxsplti32dx vs63, 0, 1074935889
-; CHECK-NEXT:xxlxor f4, f4, f4
-; CHECK-NEXT:xxlor vs3, vs63, vs63
 ; CHECK-NEXT:xxsplti32dx vs3, 1, -343597384
 ; CHECK-NEXT:# kill: def $f3 killed $f3 killed $vsl3
 ; CHECK-NEXT:bl __gcc_qadd@notoc
-; CHECK-NEXT:xxlor vs3, vs63, vs63
 ; CHECK-NEXT:xxlxor f4, f4, f4
+; CHECK-NEXT:xxsplti32dx vs3, 0, 1074935889
 ; CHECK-NEXT:xxsplti32dx vs3, 1, -1719329096
 ; CHECK-NEXT:# kill: def $f3 killed $f3 killed $vsl3
 ; CHECK-NEXT:bl __gcc_qadd@notoc
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1861,15 +1861,6 @@
 }
 
 let Predicates = [PrefixInstrs] in {
-  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
- (ins i32imm:$IMM32),
- "xxspltiw $XT, $IMM32", IIC_VecGeneral,
- 

[PATCH] D108702: [PowerPC][NFC] Rename P10 builtins vec_clrl, vec_clrr to vec_clr_first and vec_clr_last

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: amyk, lei, stefanp, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, nemanjai.
NeHuang requested review of this revision.
Herald added a project: clang.

This patch renames the vector clear left/right builtins `vec_clrl`, `vec_clrr` 
to `vec_clr_first` and `vec_clr_last` to avoid the ambiguities when dealing 
with endianness.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108702

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c


Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -732,36 +732,36 @@
   return vec_genpcvm(vulla, 0);
 }
 
-vector signed char test_vec_vclrl_sc(void) {
+vector signed char test_vec_clr_first_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrl(vsca, uia);
+  return vec_clr_first(vsca, uia);
 }
 
-vector unsigned char test_vec_clrl_uc(void) {
+vector unsigned char test_vec_clr_first_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrl(vuca, uia);
+  return vec_clr_first(vuca, uia);
 }
 
-vector signed char test_vec_vclrr_sc(void) {
+vector signed char test_vec_clr_last_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrr(vsca, uia);
+  return vec_clr_last(vsca, uia);
 }
 
-vector unsigned char test_vec_clrr_uc(void) {
+vector unsigned char test_vec_clr_last_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrr(vuca, uia);
+  return vec_clr_last(vuca, uia);
 }
 
 vector unsigned long long test_vclzdm(void) {
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -18312,10 +18312,10 @@
: __builtin_vsx_xxgenpcvdm((__a), (int)(__imm)))
 #endif /* __VSX__ */
 
-/* vec_clrl */
+/* vec_clr_first */
 
 static __inline__ vector signed char __ATTRS_o_ai
-vec_clrl(vector signed char __a, unsigned int __n) {
+vec_clr_first(vector signed char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrrb(__a, __n);
 #else
@@ -18324,7 +18324,7 @@
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
-vec_clrl(vector unsigned char __a, unsigned int __n) {
+vec_clr_first(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrrb((vector signed char)__a, __n);
 #else
@@ -18332,10 +18332,10 @@
 #endif
 }
 
-/* vec_clrr */
+/* vec_clr_last */
 
 static __inline__ vector signed char __ATTRS_o_ai
-vec_clrr(vector signed char __a, unsigned int __n) {
+vec_clr_last(vector signed char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrlb(__a, __n);
 #else
@@ -18344,7 +18344,7 @@
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
-vec_clrr(vector unsigned char __a, unsigned int __n) {
+vec_clr_last(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrlb((vector signed char)__a, __n);
 #else


Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -732,36 +732,36 @@
   return vec_genpcvm(vulla, 0);
 }
 
-vector signed char test_vec_vclrl_sc(void) {
+vector signed char test_vec_clr_first_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrl(vsca, uia);
+  return vec_clr_first(vsca, uia);
 }
 
-vector unsigned char test_vec_clrl_uc(void) {
+vector unsigned char test_vec_clr_first_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrl(vuca, uia);
+  return vec_clr_first(vuca, uia);
 }
 
-vector signed char test_vec_vclrr_sc(void) {
+vector signed char test_vec_clr_last_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrr(vsca, uia);
+  

[PATCH] D108302: [PowerPC] Fixed the crash due to early if conversion with fixed CR fields.

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: stefanp, nemanjai, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, hiraditya.
NeHuang requested review of this revision.

This patch adds a fix to do early if conversion to select when conditional 
branch not using physical register to prevent the crash when expanding ISEL 
instruction.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108302

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll


Index: llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 
-verify-machineinstrs | FileCheck %s
+target datalayout = 
"E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+
+define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) 
local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-NEXT:bge 6, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %land.rhs
+; CHECK-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-NEXT:mfocrf 3, 2
+; CHECK-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x 
i32> %b)
+  %tobool.not = icmp eq i32 %0, 0
+  br i1 %tobool.not, label %land.end, label %land.rhs
+
+land.rhs: ; preds = %entry
+  %1 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %c, <4 x 
i32> %b)
+  %tobool1 = icmp ne i32 %1, 0
+  %phi.cast = zext i1 %tobool1 to i32
+  br label %land.end
+
+land.end: ; preds = %land.rhs, %entry
+  %2 = phi i32 [ 0, %entry ], [ %phi.cast, %land.rhs ]
+  ret i32 %2
+}
+
+; Function Attrs: nofree nosync nounwind readnone
+declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1541,6 +1541,12 @@
   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
 return false;
 
+  // If the condition branch uses physical register, then it cannot be turned
+  // into a select.
+  if (Register::isPhysicalRegister(Cond[1].getReg())) {
+return false;
+  }
+
   // Check register classes.
   const MachineRegisterInfo  = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *RC =


Index: llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+
+define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vcmpgtsw. 2, 2, 3
+; CHECK-NEXT:bge 6, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %land.rhs
+; CHECK-NEXT:vcmpgtsw. 2, 4, 3
+; CHECK-NEXT:mfocrf 3, 2
+; CHECK-NEXT:rlwinm 3, 3, 25, 31, 31
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x i32> %b)
+  %tobool.not = icmp eq i32 %0, 0
+  br i1 %tobool.not, label %land.end, label %land.rhs
+
+land.rhs: ; preds = %entry
+  %1 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %c, <4 x i32> %b)
+  %tobool1 = icmp ne i32 %1, 0
+  %phi.cast = zext i1 %tobool1 to i32
+  br label %land.end
+
+land.end: ; preds = %land.rhs, %entry
+  %2 = phi i32 [ 0, %entry ], [ %phi.cast, %land.rhs ]
+  ret i32 %2
+}
+
+; Function Attrs: nofree nosync nounwind readnone
+declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1541,6 +1541,12 @@
   if (Cond[1].getReg() == PPC::CTR || 

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

[Victor Huang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG99e00663d4cd: [PowerPC] Fix return address computation for 
__builtin_return_address (authored by NeHuang).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107646/new/

https://reviews.llvm.org/D107646

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
  llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

Index: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
@@ -0,0 +1,140 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux \
+; RUN:   -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-BE
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @test0() nounwind readnone {
+; CHECK-64B-LE-LABEL: test0:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 48(1)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 64(1)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test0:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 40(1)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0);
+  ret i8* %0
+}
+
+define i8* @test1() nounwind readnone {
+; CHECK-64B-LE-LABEL: test1:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test1:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test1:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(3)
+; CHECK-32B-BE-NEXT:lwz 3, 8(3)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1);
+  ret i8* %0
+}
+
+define i8* @test2() nounwind readnone {
+; CHECK-64B-LE-LABEL: test2:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test2:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test2:
+; 

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 365761.
NeHuang added a comment.

Address review comment from Nemanja.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107646/new/

https://reviews.llvm.org/D107646

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
  llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

Index: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
@@ -0,0 +1,140 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux \
+; RUN:   -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-BE
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @test0() nounwind readnone {
+; CHECK-64B-LE-LABEL: test0:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 48(1)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 64(1)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test0:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 40(1)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0);
+  ret i8* %0
+}
+
+define i8* @test1() nounwind readnone {
+; CHECK-64B-LE-LABEL: test1:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test1:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test1:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(3)
+; CHECK-32B-BE-NEXT:lwz 3, 8(3)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1);
+  ret i8* %0
+}
+
+define i8* @test2() nounwind readnone {
+; CHECK-64B-LE-LABEL: test2:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test2:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test2:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

[Victor Huang via Phabricator via cfe-commits]

NeHuang accepted this revision.
NeHuang added a comment.

LGTM


Repository:
  rG LLVM Github Monorepo

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[PATCH] D107461: [PowerPC] Do not define __PRIVILEGED__

[Victor Huang via Phabricator via cfe-commits]

NeHuang accepted this revision as: NeHuang.
NeHuang added a comment.

LGTM


Repository:
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[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

LGTM.


Repository:
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[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 365470.
NeHuang added a comment.

Address review comments on the test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107646/new/

https://reviews.llvm.org/D107646

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
  llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

Index: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
@@ -0,0 +1,140 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux \
+; RUN:   -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-BE
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @test0() nounwind readnone {
+; CHECK-64B-LE-LABEL: test0:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 48(1)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 64(1)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test0:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 40(1)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0);
+  ret i8* %0
+}
+
+define i8* @test1() nounwind readnone {
+; CHECK-64B-LE-LABEL: test1:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test1:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test1:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(3)
+; CHECK-32B-BE-NEXT:lwz 3, 8(3)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1);
+  ret i8* %0
+}
+
+define i8* @test2() nounwind readnone {
+; CHECK-64B-LE-LABEL: test2:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test2:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test2:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; 

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 364856.
NeHuang added a comment.

- Rebased with ToT
- Clang-format


Repository:
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Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
  llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

Index: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
@@ -0,0 +1,174 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-AIX
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-AIX
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @test0() nounwind readnone {
+; CHECK-64B-LE-LABEL: test0:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 48(1)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 64(1)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-64B-AIX-LABEL: test0:
+; CHECK-64B-AIX:   # %bb.0: # %entry
+; CHECK-64B-AIX-NEXT:mflr 0
+; CHECK-64B-AIX-NEXT:std 0, 16(1)
+; CHECK-64B-AIX-NEXT:stdu 1, -48(1)
+; CHECK-64B-AIX-NEXT:ld 3, 64(1)
+; CHECK-64B-AIX-NEXT:addi 1, 1, 48
+; CHECK-64B-AIX-NEXT:ld 0, 16(1)
+; CHECK-64B-AIX-NEXT:mtlr 0
+; CHECK-64B-AIX-NEXT:blr
+;
+; CHECK-32B-AIX-LABEL: test0:
+; CHECK-32B-AIX:   # %bb.0: # %entry
+; CHECK-32B-AIX-NEXT:mflr 0
+; CHECK-32B-AIX-NEXT:stw 0, 8(1)
+; CHECK-32B-AIX-NEXT:stwu 1, -32(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 40(1)
+; CHECK-32B-AIX-NEXT:addi 1, 1, 32
+; CHECK-32B-AIX-NEXT:lwz 0, 8(1)
+; CHECK-32B-AIX-NEXT:mtlr 0
+; CHECK-32B-AIX-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0);
+  ret i8* %0
+}
+
+define i8* @test1() nounwind readnone {
+; CHECK-64B-LE-LABEL: test1:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test1:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-64B-AIX-LABEL: test1:
+; CHECK-64B-AIX:   # %bb.0: # %entry
+; CHECK-64B-AIX-NEXT:mflr 0
+; CHECK-64B-AIX-NEXT:std 0, 16(1)
+; CHECK-64B-AIX-NEXT:stdu 1, -48(1)
+; CHECK-64B-AIX-NEXT:ld 3, 0(1)
+; CHECK-64B-AIX-NEXT:ld 3, 0(3)
+; CHECK-64B-AIX-NEXT:ld 3, 16(3)
+; CHECK-64B-AIX-NEXT:addi 1, 1, 48
+; CHECK-64B-AIX-NEXT:ld 0, 16(1)
+; CHECK-64B-AIX-NEXT:mtlr 0
+; CHECK-64B-AIX-NEXT:blr
+;
+; CHECK-32B-AIX-LABEL: test1:
+; CHECK-32B-AIX:   # %bb.0: # %entry
+; CHECK-32B-AIX-NEXT:mflr 0
+; CHECK-32B-AIX-NEXT:stw 0, 8(1)
+; CHECK-32B-AIX-NEXT:stwu 1, -32(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 0(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 0(3)
+; CHECK-32B-AIX-NEXT:lwz 3, 8(3)
+; CHECK-32B-AIX-NEXT:addi 1, 1, 32
+; CHECK-32B-AIX-NEXT:lwz 0, 8(1)
+; CHECK-32B-AIX-NEXT:mtlr 0
+; CHECK-32B-AIX-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1);
+  ret i8* %0
+}
+
+define i8* @test2() nounwind readnone {
+; CHECK-64B-LE-LABEL: test2:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c:17
+// CHECK-LABEL: @test_swdiv(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8

nit: alignment with CHECKs below. Same for the other test cases.



Comment at: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:452
+
+  addPass(createPPCLowerCheckedFPArithPass());
 }

+1, 


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[PATCH] D107461: [PowerPC] Do not define __PRIVILEGED__

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/test/Driver/ppc-mprivileged-support-check.c:25
+// HASPRIV: test() #0 {
+// HASPRIV: attributes #0 {
+// HASPRIV-SAME: +privileged

maybe check for `attributes #0 = {`  


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[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, hiraditya.
NeHuang requested review of this revision.

When depth > 0, callee frame address is used to compute the return address of 
callee producing improper return address. This patch adds the fix to use caller 
frame address to compute the return address of callee.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107646

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
  llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

Index: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
@@ -0,0 +1,174 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-AIX
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-AIX
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @test0() nounwind readnone {
+; CHECK-64B-LE-LABEL: test0:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 48(1)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 64(1)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-64B-AIX-LABEL: test0:
+; CHECK-64B-AIX:   # %bb.0: # %entry
+; CHECK-64B-AIX-NEXT:mflr 0
+; CHECK-64B-AIX-NEXT:std 0, 16(1)
+; CHECK-64B-AIX-NEXT:stdu 1, -48(1)
+; CHECK-64B-AIX-NEXT:ld 3, 64(1)
+; CHECK-64B-AIX-NEXT:addi 1, 1, 48
+; CHECK-64B-AIX-NEXT:ld 0, 16(1)
+; CHECK-64B-AIX-NEXT:mtlr 0
+; CHECK-64B-AIX-NEXT:blr
+;
+; CHECK-32B-AIX-LABEL: test0:
+; CHECK-32B-AIX:   # %bb.0: # %entry
+; CHECK-32B-AIX-NEXT:mflr 0
+; CHECK-32B-AIX-NEXT:stw 0, 8(1)
+; CHECK-32B-AIX-NEXT:stwu 1, -32(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 40(1)
+; CHECK-32B-AIX-NEXT:addi 1, 1, 32
+; CHECK-32B-AIX-NEXT:lwz 0, 8(1)
+; CHECK-32B-AIX-NEXT:mtlr 0
+; CHECK-32B-AIX-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0);
+  ret i8* %0
+}
+
+define i8* @test1() nounwind readnone {
+; CHECK-64B-LE-LABEL: test1:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test1:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-64B-AIX-LABEL: test1:
+; CHECK-64B-AIX:   # %bb.0: # %entry
+; CHECK-64B-AIX-NEXT:mflr 0
+; CHECK-64B-AIX-NEXT:std 0, 16(1)
+; CHECK-64B-AIX-NEXT:stdu 1, -48(1)
+; CHECK-64B-AIX-NEXT:ld 3, 0(1)
+; CHECK-64B-AIX-NEXT:ld 3, 0(3)
+; CHECK-64B-AIX-NEXT:ld 3, 16(3)
+; CHECK-64B-AIX-NEXT:addi 1, 1, 48
+; CHECK-64B-AIX-NEXT:ld 0, 16(1)
+; CHECK-64B-AIX-NEXT:mtlr 0
+; CHECK-64B-AIX-NEXT:blr
+;
+; CHECK-32B-AIX-LABEL: test1:
+; CHECK-32B-AIX:   # %bb.0: # %entry
+; CHECK-32B-AIX-NEXT:mflr 0
+; CHECK-32B-AIX-NEXT:stw 0, 8(1)
+; CHECK-32B-AIX-NEXT:stwu 1, -32(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 0(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 0(3)
+; CHECK-32B-AIX-NEXT:lwz 3, 8(3)
+; CHECK-32B-AIX-NEXT:addi 1, 1, 32
+; CHECK-32B-AIX-NEXT:lwz 0, 8(1)
+; CHECK-32B-AIX-NEXT:mtlr 0
+; CHECK-32B-AIX-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1);
+  ret i8* %0
+}
+
+define i8* @test2() nounwind readnone {
+; 

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:45
+  // CHECK-AIX-NEXT: ret { double, double } %.fca.1.insert
+  return __cmplxl(lda, ldb);
+}

nemanjai wrote:
> We really only need this test case and we should be able to just add it to 
> one of the existing XL-compat clang test cases.
As suggest above, can we add the test case `__cmplxl` to one of the existing 
clang test file `builtins-ppc-xlcompat-cmplx.c`? You can auto generate the 
`CHECKS` using `utils/update_cc_test_checks.py` to avoid hardcoding the 
variable names. 


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[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/O3-pipeline.ll:211
   ret void
-}
\ No newline at end of file
+}

unrelated change?



Comment at: llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll:7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \

nit: `pwr7`  for aix run lines



Comment at: llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll:8
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX

can we also add a run line for 64 bit AIX?


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[PATCH] D107138: [PowerPC] Implement cmplxl builtins

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:1
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

`// REQUIRES: powerpc-registered-target`



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:1
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

NeHuang wrote:
> `// REQUIRES: powerpc-registered-target`
Question: why do we need `-O2` for this builtin?




Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex-32bit-only.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \

nemanjai wrote:
> I don't think we need the back end tests. No new IR is produced in this patch.
+1


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[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:3426
+  case PPC::BI__builtin_ppc_addex: {
+if (SemaFeatureCheck(*this, TheCall, "power9-vector",
+ diag::err_ppc_builtin_only_on_arch, "9") ||

I think we start using `isa-v30-instructions` for pwr9 only (or later process)  
in `SemaFeatureCheck`



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c:4
+// RUN:   -verify %s
+
+extern unsigned long long ull;

can we also add the run lines for 64 bit LE Linux, 64 bit AIX and 32 bit AIX?  
Will also need `#ifdef __PPC64__` for the test case. 



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll:44
+
+define dso_local i64 @call_addex_1(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_1:

This test case is identical as `call_addex_0`  The unsigned long long and 
signed long long scenarios produce identical IR and we should only keep one 
test case here.


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[PATCH] D106817: [PowerPC] Changed sema checking range for tdw td builtin

[Victor Huang via Phabricator via cfe-commits]

NeHuang accepted this revision as: NeHuang.
NeHuang added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
NeHuang marked an inline comment as done.
Closed by commit rG26ea4a443243: [PowerPC] Add PowerPC __stbcx 
builtin and intrinsic for XL compatibility (authored by NeHuang).

Changed prior to commit:
  https://reviews.llvm.org/D106484?vs=360803=360844#toc

Repository:
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
@@ -74,6 +74,28 @@
   ret i32 %2
 }
 
+declare i32 @llvm.ppc.stbcx(i8*, i32)
+define signext i32 @test_stbcx(i8* %addr, i8 signext %val) {
+; CHECK-64-LABEL: test_stbcx:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:stbcx. 4, 0, 3
+; CHECK-64-NEXT:mfocrf 3, 128
+; CHECK-64-NEXT:srwi 3, 3, 28
+; CHECK-64-NEXT:extsw 3, 3
+; CHECK-64-NEXT:blr
+;
+; CHECK-32-LABEL: test_stbcx:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:stbcx. 4, 0, 3
+; CHECK-32-NEXT:mfocrf 3, 128
+; CHECK-32-NEXT:srwi 3, 3, 28
+; CHECK-32-NEXT:blr
+entry:
+  %conv = sext i8 %val to i32
+  %0 = tail call i32 @llvm.ppc.stbcx(i8* %addr, i32 %conv)
+  ret i32 %0
+}
+
 define dso_local signext i16 @test_lharx(i16* %a) {
 ; CHECK-64-LABEL: test_lharx:
 ; CHECK-64:   # %bb.0: # %entry
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5463,6 +5463,8 @@
 
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
+def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A),
+  (STBCX gprc:$A, ForceXForm:$dst)>;
 def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
   (TW $IMM, $A, $B)>;
 def : Pat<(int_ppc_trap gprc:$A),
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1566,6 +1566,9 @@
 [IntrWriteMem]>;
   def int_ppc_sthcx
   : Intrinsic<[llvm_i32_ty], [ llvm_ptr_ty, llvm_i32_ty ], [IntrWriteMem]>;
+  def int_ppc_stbcx : GCCBuiltin<"__builtin_ppc_stbcx">,
+  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+[IntrWriteMem]>;
   def int_ppc_dcbtstt : GCCBuiltin<"__builtin_ppc_dcbtstt">,
 Intrinsic<[], [llvm_ptr_ty],
   [IntrArgMemOnly, NoCapture>]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
@@ -15,6 +15,8 @@
 // RUN:   -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
 
 extern void *a;
+extern volatile char *c_addr;
+extern char c;
 
 void test_icbt() {
 // CHECK-LABEL: @test_icbt(
@@ -31,3 +33,14 @@
 // CHECK-PWR8: call void @llvm.ppc.icbt(i8* %0)
 // CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
 }
+
+int test_builtin_ppc_stbcx() {
+// CHECK-PWR8-LABEL: @test_builtin_ppc_stbcx(
+// CHECK-PWR8: [[TMP0:%.*]] = load i8*, i8** @c_addr, align {{[0-9]+}}
+// CHECK-PWR8-NEXT:[[TMP1:%.*]] = load i8, i8* @c, align 1
+// CHECK-PWR8-NEXT:[[TMP2:%.*]] = sext i8 [[TMP1]] to i32
+// CHECK-PWR8-NEXT:[[TMP3:%.*]] = call i32 @llvm.ppc.stbcx(i8* [[TMP0]], i32 [[TMP2]])
+// CHECK-PWR8-NEXT:ret i32 [[TMP3]]
+// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
+  return __builtin_ppc_stbcx(c_addr, c);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3434,9 +3434,8 @@
   case PPC::BI__builtin_ppc_rdlam:
 return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_icbt:
-return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
-diag::err_ppc_builtin_only_on_arch, "8");
   case PPC::BI__builtin_ppc_sthcx:
+  case PPC::BI__builtin_ppc_stbcx:
   case PPC::BI__builtin_ppc_lharx:
   case PPC::BI__builtin_ppc_lbarx:

[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang marked an inline comment as done.
NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c:31
+  return __builtin_ppc_stbcx(c_addr, c);
+}

lei wrote:
> Why not just add this tc to 
> `clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c`?
> The other related store functions are tested there.
`__stbcx` is only valid with `pwr8` (or later cpu)


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[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 360803.
NeHuang added a comment.

- Addressed review comments from Lei
- Rebased the patch


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
@@ -29,6 +29,28 @@
   ret i32 %0
 }
 
+declare i32 @llvm.ppc.stbcx(i8*, i32)
+define signext i32 @test_stbcx(i8* %addr, i8 signext %val) {
+; CHECK-64-LABEL: test_stbcx:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:stbcx. 4, 0, 3
+; CHECK-64-NEXT:mfocrf 3, 128
+; CHECK-64-NEXT:srwi 3, 3, 28
+; CHECK-64-NEXT:extsw 3, 3
+; CHECK-64-NEXT:blr
+;
+; CHECK-32-LABEL: test_stbcx:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:stbcx. 4, 0, 3
+; CHECK-32-NEXT:mfocrf 3, 128
+; CHECK-32-NEXT:srwi 3, 3, 28
+; CHECK-32-NEXT:blr
+entry:
+  %conv = sext i8 %val to i32
+  %0 = tail call i32 @llvm.ppc.stbcx(i8* %addr, i32 %conv)
+  ret i32 %0
+}
+
 declare i32 @llvm.ppc.stwcx(i8*, i32)
 define dso_local signext i32 @test_stwcx(i32* %a, i32 signext %b) {
 ; CHECK-64-LABEL: test_stwcx:
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5463,6 +5463,8 @@
 
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
+def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A),
+  (STBCX gprc:$A, ForceXForm:$dst)>;
 def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
   (TW $IMM, $A, $B)>;
 def : Pat<(int_ppc_trap gprc:$A),
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1558,6 +1558,9 @@
   Intrinsic<[],[],[]>;
   def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
   Intrinsic<[],[],[]>;
+  def int_ppc_stbcx : GCCBuiltin<"__builtin_ppc_stbcx">,
+  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+[IntrWriteMem]>;
   def int_ppc_stdcx : GCCBuiltin<"__builtin_ppc_stdcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i64_ty],
 [IntrWriteMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
@@ -15,6 +15,8 @@
 // RUN:   -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
 
 extern void *a;
+extern volatile char *c_addr;
+extern char c;
 
 void test_icbt() {
 // CHECK-LABEL: @test_icbt(
@@ -31,3 +33,14 @@
 // CHECK-PWR8: call void @llvm.ppc.icbt(i8* %0)
 // CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
 }
+
+int test_builtin_ppc_stbcx() {
+// CHECK-PWR8-LABEL: @test_builtin_ppc_stbcx(
+// CHECK-PWR8: [[TMP0:%.*]] = load i8*, i8** @c_addr, align {{[0-9]+}}
+// CHECK-PWR8-NEXT:[[TMP1:%.*]] = load i8, i8* @c, align 1
+// CHECK-PWR8-NEXT:[[TMP2:%.*]] = sext i8 [[TMP1]] to i32
+// CHECK-PWR8-NEXT:[[TMP3:%.*]] = call i32 @llvm.ppc.stbcx(i8* [[TMP0]], i32 [[TMP2]])
+// CHECK-PWR8-NEXT:ret i32 [[TMP3]]
+// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
+  return __builtin_ppc_stbcx(c_addr, c);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3434,6 +3434,7 @@
   case PPC::BI__builtin_ppc_rdlam:
 return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_icbt:
+  case PPC::BI__builtin_ppc_stbcx:
 return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
 diag::err_ppc_builtin_only_on_arch, "8");
   case PPC::BI__builtin_ppc_sthcx:
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -121,6 +121,7 @@
   Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
   Builder.defineMacro("__lbarx", 

[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, hiraditya.
NeHuang requested review of this revision.
Herald added a project: clang.
Herald added subscribers: llvm-commits, cfe-commits.

This patch is in a series of patches to provide builtins for compatibility with 
the XL compiler. 
This patch adds the builtin and intrinsic for  "__stbcx".


Repository:
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https://reviews.llvm.org/D106484

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
@@ -50,3 +50,25 @@
   %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %b)
   ret i32 %1
 }
+
+declare i32 @llvm.ppc.stbcx(i8*, i32)
+define signext i32 @test_stbcx(i8* %addr, i8 signext %val) {
+; CHECK-64-LABEL: test_stbcx:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:stbcx. 4, 0, 3
+; CHECK-64-NEXT:mfocrf 3, 128
+; CHECK-64-NEXT:srwi 3, 3, 28
+; CHECK-64-NEXT:extsw 3, 3
+; CHECK-64-NEXT:blr
+;
+; CHECK-32-LABEL: test_stbcx:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:stbcx. 4, 0, 3
+; CHECK-32-NEXT:mfocrf 3, 128
+; CHECK-32-NEXT:srwi 3, 3, 28
+; CHECK-32-NEXT:blr
+entry:
+  %conv = sext i8 %val to i32
+  %0 = tail call i32 @llvm.ppc.stbcx(i8* %addr, i32 %conv)
+  ret i32 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5459,6 +5459,8 @@
 
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
+def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A),
+  (STBCX gprc:$A, ForceXForm:$dst)>;
 def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
   (TW $IMM, $A, $B)>;
 def : Pat<(int_ppc_trap gprc:$A),
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1559,6 +1559,9 @@
   Intrinsic<[],[],[]>;
   def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
   Intrinsic<[],[],[]>;
+  def int_ppc_stbcx : GCCBuiltin<"__builtin_ppc_stbcx">,
+  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+[IntrWriteMem]>;
   def int_ppc_stdcx : GCCBuiltin<"__builtin_ppc_stdcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i64_ty],
 [IntrWriteMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
@@ -0,0 +1,31 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s --check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s --check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s --check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s --check-prefix=CHECK-PWR8
+// RUN: not %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+// RUN: not %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+// RUN: not %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
+// RUN:   -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+
+extern volatile char *c_addr;
+extern char c;
+
+// CHECK-PWR8-LABEL: @test_builtin_ppc_stbcx(
+// CHECK-PWR8: [[TMP0:%.*]] = load i8*, i8** @c_addr, align {{[0-9]+}}
+// CHECK-PWR8-NEXT:[[TMP1:%.*]] = load i8, i8* @c, align 1
+// CHECK-PWR8-NEXT:[[TMP2:%.*]] = sext i8 [[TMP1]] to i32
+// CHECK-PWR8-NEXT:[[TMP3:%.*]] = call i32 @llvm.ppc.stbcx(i8* [[TMP0]], i32 [[TMP2]])
+// CHECK-PWR8-NEXT:ret i32 [[TMP3]]
+
+// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
+

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

[Victor Huang via Phabricator via cfe-commits]

NeHuang added subscribers: jroelofs, NeHuang.
NeHuang added a comment.

@jroelofs committed `f6769b663a0d4432b5e00e0c03904a5dfba7b077` to move the 
backend test cases from `CodeGen` -> `CodeGen/PowerPC` so they don't fail when 
the PPC backend isn't built.


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[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

Thanks @jroelofs for moving the test cases! Those cases were added in 
https://reviews.llvm.org/D105946 and I have notified the author.


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[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1a762f93f816: [PowerPC] Add PowerPC cmpb builtin and emit 
target indepedent code for XL… (authored by NeHuang).

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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 < %s | FileCheck %s
+
+define i64 @test_cmpb(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cmpb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cmpb 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %cmpb = tail call i64 @llvm.ppc.cmpb.i64.i64.i64(i64 %a, i64 %b)
+  ret i64 %cmpb
+}
+
+declare i64 @llvm.ppc.cmpb.i64.i64.i64(i64, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+
+define i64 @test_cmpb(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cmpb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cmpb 4, 4, 6
+; CHECK-NEXT:cmpb 3, 3, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = trunc i64 %a to i32
+  %1 = trunc i64 %b to i32
+  %2 = lshr i64 %a, 32
+  %3 = trunc i64 %2 to i32
+  %4 = lshr i64 %b, 32
+  %5 = trunc i64 %4 to i32
+  %cmpb = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %0, i32 %1)
+  %6 = zext i32 %cmpb to i64
+  %cmpb1 = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %3, i32 %5)
+  %7 = zext i32 %cmpb1 to i64
+  %8 = shl nuw i64 %7, 32
+  %9 = or i64 %8, %6
+  ret i64 %9
+}
+
+declare i32 @llvm.ppc.cmpb.i32.i32.i32(i32, i32)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5291,6 +5291,8 @@
   (i32 (MULHW $a, $b))>;
 def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)),
   (i32 (MULHWU $a, $b))>;
+def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)),
+  (i32 (CMPB $a, $b))>;
 
 def : Pat<(int_ppc_load2r ForceXForm:$ptr),
   (LHBRX ForceXForm:$ptr)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1796,6 +1796,9 @@
   (STDBRX g8rc:$a, ForceXForm:$ptr)>;
 }
 
+def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)),
+  (i64 (CMPB8 $a, $b))>;
+
 let Predicates = [IsISA3_0] in {
 // DARN (deliver random number)
 // L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1575,6 +1575,9 @@
   def int_ppc_setb
   : GCCBuiltin<"__builtin_ppc_setb">,
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_cmpb
+  : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty, llvm_anyint_ty],
+  [IntrNoMem]>;
   // multiply
   def int_ppc_mulhd
   : GCCBuiltin<"__builtin_ppc_mulhd">,
Index: clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-64B
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s --check-prefix=CHECK-64B
+// RUN: %clang_cc1 

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 360109.
NeHuang added a comment.

clang-format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105194/new/

https://reviews.llvm.org/D105194

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 < %s | FileCheck %s
+
+define i64 @test_cmpb(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cmpb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cmpb 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %cmpb = tail call i64 @llvm.ppc.cmpb.i64.i64.i64(i64 %a, i64 %b)
+  ret i64 %cmpb
+}
+
+declare i64 @llvm.ppc.cmpb.i64.i64.i64(i64, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+
+define i64 @test_cmpb(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cmpb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cmpb 4, 4, 6
+; CHECK-NEXT:cmpb 3, 3, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = trunc i64 %a to i32
+  %1 = trunc i64 %b to i32
+  %2 = lshr i64 %a, 32
+  %3 = trunc i64 %2 to i32
+  %4 = lshr i64 %b, 32
+  %5 = trunc i64 %4 to i32
+  %cmpb = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %0, i32 %1)
+  %6 = zext i32 %cmpb to i64
+  %cmpb1 = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %3, i32 %5)
+  %7 = zext i32 %cmpb1 to i64
+  %8 = shl nuw i64 %7, 32
+  %9 = or i64 %8, %6
+  ret i64 %9
+}
+
+declare i32 @llvm.ppc.cmpb.i32.i32.i32(i32, i32)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5291,6 +5291,8 @@
   (i32 (MULHW $a, $b))>;
 def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)),
   (i32 (MULHWU $a, $b))>;
+def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)),
+  (i32 (CMPB $a, $b))>;
 
 def : Pat<(int_ppc_load2r ForceXForm:$ptr),
   (LHBRX ForceXForm:$ptr)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1796,6 +1796,9 @@
   (STDBRX g8rc:$a, ForceXForm:$ptr)>;
 }
 
+def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)),
+  (i64 (CMPB8 $a, $b))>;
+
 let Predicates = [IsISA3_0] in {
 // DARN (deliver random number)
 // L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1576,6 +1576,9 @@
   def int_ppc_setb
   : GCCBuiltin<"__builtin_ppc_setb">,
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_cmpb
+  : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty, llvm_anyint_ty],
+  [IntrNoMem]>;
   // multiply
   def int_ppc_mulhd
   : GCCBuiltin<"__builtin_ppc_mulhd">,
Index: clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-64B
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s --check-prefix=CHECK-64B
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-32B
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang marked 4 inline comments as done.
NeHuang added a comment.

Rebased the patch with ToT.


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[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 359843.
NeHuang added a comment.

Address review comments from Nemanja.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105194/new/

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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 < %s | FileCheck %s
+
+define i64 @test_cmpb(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cmpb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cmpb 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %cmpb = tail call i64 @llvm.ppc.cmpb.i64.i64.i64(i64 %a, i64 %b)
+  ret i64 %cmpb
+}
+
+declare i64 @llvm.ppc.cmpb.i64.i64.i64(i64, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+
+define i64 @test_cmpb(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cmpb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cmpb 4, 4, 6
+; CHECK-NEXT:cmpb 3, 3, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = trunc i64 %a to i32
+  %1 = trunc i64 %b to i32
+  %2 = lshr i64 %a, 32
+  %3 = trunc i64 %2 to i32
+  %4 = lshr i64 %b, 32
+  %5 = trunc i64 %4 to i32
+  %cmpb = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %0, i32 %1)
+  %6 = zext i32 %cmpb to i64
+  %cmpb1 = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %3, i32 %5)
+  %7 = zext i32 %cmpb1 to i64
+  %8 = shl nuw i64 %7, 32
+  %9 = or i64 %8, %6
+  ret i64 %9
+}
+
+declare i32 @llvm.ppc.cmpb.i32.i32.i32(i32, i32)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5291,6 +5291,8 @@
   (i32 (MULHW $a, $b))>;
 def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)),
   (i32 (MULHWU $a, $b))>;
+def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)),
+  (i32 (CMPB $a, $b))>;
 
 def : Pat<(int_ppc_load2r ForceXForm:$ptr),
   (LHBRX ForceXForm:$ptr)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1796,6 +1796,9 @@
   (STDBRX g8rc:$a, ForceXForm:$ptr)>;
 }
 
+def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)),
+  (i64 (CMPB8 $a, $b))>;
+
 let Predicates = [IsISA3_0] in {
 // DARN (deliver random number)
 // L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1576,6 +1576,9 @@
   def int_ppc_setb
   : GCCBuiltin<"__builtin_ppc_setb">,
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_cmpb
+  : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty, llvm_anyint_ty],
+  [IntrNoMem]>;
   // multiply
   def int_ppc_mulhd
   : GCCBuiltin<"__builtin_ppc_mulhd">,
Index: clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-64B
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s --check-prefix=CHECK-64B
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-32B
+// RUN: %clang_cc1 -triple 

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Victor Huang via Phabricator via cfe-commits]

NeHuang accepted this revision.
NeHuang added a comment.

LGTM


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[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 359467.
NeHuang added a comment.
Herald added subscribers: llvm-commits, hiraditya.

Address review comment to rework 32 bit handling.


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 < %s | FileCheck %s
+
+define i64 @test_cmpb(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cmpb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cmpb 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %cmpb = tail call i64 @llvm.ppc.cmpb.i64.i64.i64(i64 %a, i64 %b)
+  ret i64 %cmpb
+}
+
+declare i64 @llvm.ppc.cmpb.i64.i64.i64(i64, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+
+define i64 @test_cmpb(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cmpb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cmpb 4, 4, 6
+; CHECK-NEXT:cmpb 3, 3, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = trunc i64 %a to i32
+  %1 = trunc i64 %b to i32
+  %2 = lshr i64 %a, 32
+  %3 = trunc i64 %2 to i32
+  %4 = lshr i64 %b, 32
+  %5 = trunc i64 %4 to i32
+  %cmpb = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %0, i32 %1)
+  %6 = zext i32 %cmpb to i64
+  %cmpb1 = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %3, i32 %5)
+  %7 = zext i32 %cmpb1 to i64
+  %8 = shl nuw i64 %7, 32
+  %9 = or i64 %8, %6
+  ret i64 %9
+}
+
+declare i32 @llvm.ppc.cmpb.i32.i32.i32(i32, i32)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5263,6 +5263,8 @@
 def : Pat<(i32 (int_ppc_cmprb i32:$a, i32:$b, i32:$c)),
   (i32 (SETB (CMPRB imm:$a, $b, $c)))>;
 }
+def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)),
+  (i32 (CMPB $a, $b))>;
 def : Pat<(i32 (int_ppc_mulhw i32:$a, i32:$b)),
   (i32 (MULHW $a, $b))>;
 def : Pat<(i32 (int_ppc_mulhwu i32:$a, i32:$b)),
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1709,6 +1709,9 @@
   (i64 (MULHDU $a, $b))>;
 }
 
+def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)),
+  (i64 (CMPB8 $a, $b))>;
+
 let Predicates = [IsISA3_0] in {
 // DARN (deliver random number)
 // L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1533,6 +1533,8 @@
   def int_ppc_setb
   : GCCBuiltin<"__builtin_ppc_setb">,
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_cmpb
+  : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty, llvm_anyint_ty], [IntrNoMem]>;
   // multiply
   def int_ppc_mulhd
   : GCCBuiltin<"__builtin_ppc_mulhd">,
Index: clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-64B
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s --check-prefix=CHECK-64B
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | 

[PATCH] D106021: [PowerPC] Add PowerPC population count, reversed load and store related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
NeHuang marked an inline comment as done.
Closed by commit rG4eb107ccbad7: [PowerPC] Add PowerPC population count, 
reversed load and store related… (authored by NeHuang).

Changed prior to commit:
  https://reviews.llvm.org/D106021?vs=358700=359150#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106021/new/

https://reviews.llvm.org/D106021

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
  clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-popcnt.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-popcnt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-popcnt.ll
@@ -0,0 +1,51 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
+
+@ui = external global i32, align 4
+@ull = external global i64, align 8
+
+define dso_local signext i32 @test_builtin_ppc_poppar4() {
+; CHECK-32B-LABEL: test_builtin_ppc_poppar4:
+; CHECK-32B: popcntw 3, 3
+; CHECK-32B-NEXT:clrlwi 3, 3, 31
+; CHECK-32B-NEXT:blr
+; CHECK-64B-LABEL: test_builtin_ppc_poppar4:
+; CHECK-64B: popcntw 3, 3
+; CHECK-64B-NEXT:clrlwi 3, 3, 31
+; CHECK-64B-NEXT:blr
+entry:
+  %0 = load i32, i32* @ui, align 4
+  %1 = load i32, i32* @ui, align 4
+  %2 = call i32 @llvm.ctpop.i32(i32 %1)
+  %3 = and i32 %2, 1
+  ret i32 %3
+}
+
+declare i32 @llvm.ctpop.i32(i32)
+
+define dso_local signext i32 @test_builtin_ppc_poppar8() {
+; CHECK-32B-LABEL: test_builtin_ppc_poppar8:
+; CHECK-32B: xor 3, 3, 4
+; CHECK-32B-NEXT:popcntw 3, 3
+; CHECK-32B-NEXT:clrlwi 3, 3, 31
+; CHECK-32B-NEXT:blr
+; CHECK-64B-LABEL: test_builtin_ppc_poppar8:
+; CHECK-64B: popcntd 3, 3
+; CHECK-64B-NEXT:clrldi 3, 3, 63
+; CHECK-64B-NEXT:blr
+entry:
+  %0 = load i64, i64* @ull, align 8
+  %1 = load i64, i64* @ull, align 8
+  %2 = call i64 @llvm.ctpop.i64(i64 %1)
+  %3 = and i64 %2, 1
+  %cast = trunc i64 %3 to i32
+  ret i32 %cast
+}
+
+declare i64 @llvm.ctpop.i64(i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
@@ -0,0 +1,87 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
+
+@us = external global i16, align 2
+@us_addr = external global i16*, align 8
+@ui = external global i32, align 4
+@ui_addr = external global i32*, align 8
+
+define dso_local void @test_builtin_ppc_store2r() {
+; CHECK-64B-LABEL: test_builtin_ppc_store2r:
+; CHECK-64B: sthbrx 3, 0, 4
+; CHECK-64B-NEXT:blr
+
+; CHECK-32B-LABEL: test_builtin_ppc_store2r:
+; CHECK-32B: sthbrx 3, 0, 4
+; CHECK-32B-NEXT:blr
+entry:
+  %0 = load i16, i16* @us, align 2
+  %conv = zext i16 %0 to i32
+  %1 = load i16*, i16** @us_addr, align 8
+  %2 = bitcast i16* %1 to i8*
+  call void @llvm.ppc.store2r(i32 %conv, i8* %2)
+  ret void
+}
+
+declare void @llvm.ppc.store2r(i32, i8*)
+
+define dso_local void @test_builtin_ppc_store4r() {
+; CHECK-64B-LABEL: test_builtin_ppc_store4r:
+; CHECK-64B: stwbrx 3, 0, 4
+; CHECK-64B-NEXT:blr
+
+; CHECK-32B-LABEL: test_builtin_ppc_store4r:
+; CHECK-32B: stwbrx 3, 0, 4
+; CHECK-32B-NEXT:blr
+entry:

[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd40e8091bd1f: [PowerPC] Add PowerPC rotate related builtins 
and emit target independent code… (authored by NeHuang).

Changed prior to commit:
  https://reviews.llvm.org/D104744?vs=358761=358986#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104744/new/

https://reviews.llvm.org/D104744

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,56 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+  // CHECK-LABEL: test_builtin_ppc_rldimi
+  // CHECK:   %res = alloca i64, align 8
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+  // CHECK-NEXT:  store i64 [[RF]], i64* %res, align 8
+  // CHECK-NEXT:  ret void
+
+  /*shift = 63, mask = 0x00FFF000 = 72057593769492480, ~mask = 0xFF000FFF = -72057593769492481*/
+  unsigned long long res = __builtin_ppc_rldimi(ull, ull, 63, 0x00FFF000);
+}
+
+void test_builtin_ppc_rlwimi() {
+  // CHECK-LABEL: test_builtin_ppc_rlwimi
+  // CHECK:   %res = alloca i32, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+  // CHECK-NEXT:  store i32 [[RF]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*shift = 31, mask = 0x00 = 16776960, ~mask = 0xFFFF = -16776961*/
+  unsigned int res = __builtin_ppc_rlwimi(ui, ui, 31, 0x00);
+}
+
+void test_builtin_ppc_rlwnm() {
+  // CHECK-LABEL: test_builtin_ppc_rlwnm
+  // CHECK:   %res = alloca i32, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 511
+  // CHECK-NEXT:  store i32 [[RC]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*shift = 31, mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -10,6 +10,8 @@
 
 extern long long lla, llb;
 extern int ia, ib;
+extern unsigned int ui;
+extern unsigned long long ull;
 
 void test_trap(void) {
 #ifdef __PPC64__
@@ -17,3 +19,27 @@
 #endif
   __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid range [0, 31]}}
 }
+
+void test_builtin_ppc_rldimi() {
+  unsigned int shift;
+  unsigned long long mask;
+  unsigned long long res = __builtin_ppc_rldimi(ull, ull, shift, 7); // expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+  res = __builtin_ppc_rldimi(ull, ull, 63, mask);// expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+  res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00);  // expected-error {{argument 3 value should represent a contiguous bit field}}
+}
+
+void test_builtin_ppc_rlwimi() {
+  unsigned int shift;
+  unsigned int mask;
+  unsigned int res = __builtin_ppc_rlwimi(ui, ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwimi' must be a constant integer}}
+  res = 

[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 358761.
NeHuang marked 4 inline comments as done.
NeHuang added a comment.

Address review comments from Nemanja.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104744/new/

https://reviews.llvm.org/D104744

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,56 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+  // CHECK-LABEL: test_builtin_ppc_rldimi
+  // CHECK:   %res = alloca i64, align 8
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+  // CHECK-NEXT:  store i64 [[RF]], i64* %res, align 8
+  // CHECK-NEXT:  ret void
+
+  /*shift = 63, mask = 0x00FFF000 = 72057593769492480, ~mask = 0xFF000FFF = -72057593769492481*/
+  unsigned long long res = __builtin_ppc_rldimi(ull, ull, 63, 0x00FFF000);
+}
+
+void test_builtin_ppc_rlwimi() {
+  // CHECK-LABEL: test_builtin_ppc_rlwimi
+  // CHECK:   %res = alloca i32, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+  // CHECK-NEXT:  store i32 [[RF]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*shift = 31, mask = 0x00 = 16776960, ~mask = 0xFFFF = -16776961*/
+  unsigned int res = __builtin_ppc_rlwimi(ui, ui, 31, 0x00);
+}
+
+void test_builtin_ppc_rlwnm() {
+  // CHECK-LABEL: test_builtin_ppc_rlwnm
+  // CHECK:   %res = alloca i32, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 511
+  // CHECK-NEXT:  store i32 [[RC]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*shift = 31, mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -0,0 +1,37 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+  unsigned int shift;
+  unsigned long long mask;
+  unsigned long long res = __builtin_ppc_rldimi(ull, ull, shift, 7); // expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+  res = __builtin_ppc_rldimi(ull, ull, 63, mask);// expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+  res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00);  // expected-error {{argument 3 value should represent a contiguous bit field}}
+}
+
+void test_builtin_ppc_rlwimi() {
+  unsigned int shift;
+  unsigned int mask;
+  unsigned int res = __builtin_ppc_rlwimi(ui, ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwimi' must be a constant integer}}
+  res = 

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang marked an inline comment as done.
NeHuang added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15081
   }
+  case PPC::BI__builtin_ppc_cmpb: {
+llvm::Type *Ty = Ops[0]->getType();

NeHuang wrote:
> nemanjai wrote:
> > I find it rather surprising that we are emitting this complex sequence for 
> > this builtin. Perhaps there is a good reason for doing so, but at the very 
> > least, this requires a thorough explanation in a comment.
> > 
> > One additional concern I have with this is that if some transformation 
> > proves that some portion of this is unused (perhaps using `DemandedBits` 
> > analysis), it may optimize out a portion of this, thereby making the 
> > sequence emit a whole bunch of xor's, or's, rotates, etc.
> > 
> > For example:
> > ```
> > ...
> > unsigned long long A = __builtin_ppc_cmpb(B, C);
> > return A & 0xFF00FF00FF00FF;
> > ```
> > It is entirely possible that the optimizer will get rid of some of the 
> > produced instructions and then the back end won't be able to emit a single 
> > `cmpb` but will have to emit a whole bunch of scalar instructions.
> - The backend test case define i64 @test64(i64 %x, i64 %y) is in 
> llvm/test/CodeGen/PowerPC/cmpb.ll
> - Also Tried the test case and results look fine.
> ```
> $ cat test_cmpb.c
> long long test_cmpb(long long a, long long b) {
>   //return __cmpb(a, b);
>   unsigned long long A = __builtin_ppc_cmpb(a, b);
>   return A & 0xFF00FF00FF00FF;
> }
> $ clang -cc1 -O3 -triple powerpc-unknown-aix test_cmpb.c -target-cpu pwr9 -S 
> -o test_cmpb_32bit.s
> ...
> .test_cmpb:
> # %bb.0:# %entry
> cmpb 4, 6, 4
> lis 6, 255
> cmpb 3, 5, 3
> ori 6, 6, 255
> and 4, 4, 6
> and 3, 3, 6
> blr
> $ clang -cc1 -O3 -triple powerpc64-unknown-aix test_cmpb.c -target-cpu pwr9 
> -S -o test_cmpb_64bit.s
> .test_cmpb:
> # %bb.0:# %entry
> cmpb 3, 4, 3
> lis 4, 255
> ori 4, 4, 255
> rldimi 4, 4, 32, 0
> and 3, 3, 4
> blr
> ```
The intension of emitting this complex sequence for this builtin is to produce 
the target independent code matching the backend test case IR (in the 
description) and produce asm results matching xlc. Verified the target IR will 
produce expected asm results for 32 bit and 64 bit.
- For 64 bit 
```
cmpb 3, 3, 4
blr
```
- For 32 bit 
```
cmpb 4, 6, 4
cmpb 3, 5, 3
blr
```



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  rG LLVM Github Monorepo

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[PATCH] D106021: [PowerPC] Add PowerPC population count, reversed load and store related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, hiraditya.
NeHuang requested review of this revision.
Herald added a project: clang.
Herald added subscribers: llvm-commits, cfe-commits.

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtins and instrisics for 
population 
count, reversed load and store related operations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106021

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
  clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-popcnt.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-popcnt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-popcnt.ll
@@ -0,0 +1,51 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
+
+@ui = external global i32, align 4
+@ull = external global i64, align 8
+
+define dso_local signext i32 @test_builtin_ppc_poppar4() {
+; CHECK-32B-LABEL: test_builtin_ppc_poppar4:
+; CHECK-32B: popcntw 3, 3
+; CHECK-32B-NEXT:clrlwi 3, 3, 31
+; CHECK-32B-NEXT:blr
+; CHECK-64B-LABEL: test_builtin_ppc_poppar4:
+; CHECK-64B: popcntw 3, 3
+; CHECK-64B-NEXT:clrlwi 3, 3, 31
+; CHECK-64B-NEXT:blr
+entry:
+  %0 = load i32, i32* @ui, align 4
+  %1 = load i32, i32* @ui, align 4
+  %2 = call i32 @llvm.ctpop.i32(i32 %1)
+  %3 = and i32 %2, 1
+  ret i32 %3
+}
+
+declare i32 @llvm.ctpop.i32(i32)
+
+define dso_local signext i32 @test_builtin_ppc_poppar8() {
+; CHECK-32B-LABEL: test_builtin_ppc_poppar8:
+; CHECK-32B: xor 3, 3, 4
+; CHECK-32B-NEXT:popcntw 3, 3
+; CHECK-32B-NEXT:clrlwi 3, 3, 31
+; CHECK-32B-NEXT:blr
+; CHECK-64B-LABEL: test_builtin_ppc_poppar8:
+; CHECK-64B: popcntd 3, 3
+; CHECK-64B-NEXT:clrldi 3, 3, 63
+; CHECK-64B-NEXT:blr
+entry:
+  %0 = load i64, i64* @ull, align 8
+  %1 = load i64, i64* @ull, align 8
+  %2 = call i64 @llvm.ctpop.i64(i64 %1)
+  %3 = and i64 %2, 1
+  %cast = trunc i64 %3 to i32
+  ret i32 %cast
+}
+
+declare i64 @llvm.ctpop.i64(i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
@@ -0,0 +1,89 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32B
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
+
+@us = external global i16, align 2
+@us_addr = external global i16*, align 8
+@ui = external global i32, align 4
+@ui_addr = external global i32*, align 8
+
+define dso_local void @test_builtin_ppc_store2r() {
+; CHECK-64B-LABEL: test_builtin_ppc_store2r:
+; CHECK-64B: clrlwi 3, 3, 16
+; CHECK-64B-NEXT:sthbrx 3, 0, 4
+; CHECK-64B-NEXT:blr
+
+; CHECK-32B-LABEL: test_builtin_ppc_store2r:
+; CHECK-32B: clrlwi 3, 3, 16
+; CHECK-32B-NEXT:sthbrx 3, 0, 4
+; CHECK-32B-NEXT:blr
+entry:
+  %0 = load i16, i16* @us, align 2
+  %conv = zext i16 %0 to i32
+  %1 = load i16*, i16** @us_addr, align 8
+  %2 = bitcast i16* %1 to i8*
+  call void @llvm.ppc.store2r(i32 %conv, i8* %2)
+  ret void
+}
+
+declare void @llvm.ppc.store2r(i32, i8*)
+
+define dso_local void @test_builtin_ppc_store4r() {
+; CHECK-64B-LABEL: test_builtin_ppc_store4r:
+; CHECK-64B: stwbrx 3, 0, 4
+; 

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15081
   }
+  case PPC::BI__builtin_ppc_cmpb: {
+llvm::Type *Ty = Ops[0]->getType();

nemanjai wrote:
> I find it rather surprising that we are emitting this complex sequence for 
> this builtin. Perhaps there is a good reason for doing so, but at the very 
> least, this requires a thorough explanation in a comment.
> 
> One additional concern I have with this is that if some transformation proves 
> that some portion of this is unused (perhaps using `DemandedBits` analysis), 
> it may optimize out a portion of this, thereby making the sequence emit a 
> whole bunch of xor's, or's, rotates, etc.
> 
> For example:
> ```
> ...
> unsigned long long A = __builtin_ppc_cmpb(B, C);
> return A & 0xFF00FF00FF00FF;
> ```
> It is entirely possible that the optimizer will get rid of some of the 
> produced instructions and then the back end won't be able to emit a single 
> `cmpb` but will have to emit a whole bunch of scalar instructions.
- The backend test case define i64 @test64(i64 %x, i64 %y) is in 
llvm/test/CodeGen/PowerPC/cmpb.ll
- Also Tried the test case and results look fine.
```
$ cat test_cmpb.c
long long test_cmpb(long long a, long long b) {
  //return __cmpb(a, b);
  unsigned long long A = __builtin_ppc_cmpb(a, b);
  return A & 0xFF00FF00FF00FF;
}
$ clang -cc1 -O3 -triple powerpc-unknown-aix test_cmpb.c -target-cpu pwr9 -S -o 
test_cmpb_32bit.s
...
.test_cmpb:
# %bb.0:# %entry
cmpb 4, 6, 4
lis 6, 255
cmpb 3, 5, 3
ori 6, 6, 255
and 4, 4, 6
and 3, 3, 6
blr
$ clang -cc1 -O3 -triple powerpc64-unknown-aix test_cmpb.c -target-cpu pwr9 -S 
-o test_cmpb_64bit.s
.test_cmpb:
# %bb.0:# %entry
cmpb 3, 4, 3
lis 4, 255
ori 4, 4, 255
rldimi 4, 4, 32, 0
and 3, 3, 4
blr
```


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[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG18c19414eb70: [PowerPC] Add PowerPC compare and multiply 
related builtins and instrinsics for… (authored by NeHuang).

Changed prior to commit:
  https://reviews.llvm.org/D102875?vs=358397=358441#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102875/new/

https://reviews.llvm.org/D102875

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+
+define dso_local signext i32 @test_builtin_ppc_mulhw(i32 %a, i32%b) {
+; CHECK-32-LABEL: test_builtin_ppc_mulhw:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhw 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhw:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhw 3, 3, 4
+; CHECK-64-NEXT:extsw 3, 3
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhw(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.mulhw(i32, i32)
+
+define dso_local zeroext i32 @test_builtin_ppc_mulhwu(i32 %a, i32%b) {
+; CHECK-32-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhwu 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhwu 3, 3, 4
+; CHECK-64-NEXT:clrldi 3, 3, 32
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhwu(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.mulhwu(i32, i32)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @test_builtin_ppc_mulhd(i64 %a, i64 %b) {
+; CHECK-LABEL: test_builtin_ppc_mulhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhd 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhd(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.mulhd(i64, i64)
+
+define dso_local i64 @test_builtin_ppc_mulhdu(i64 %a, i64 %b) {
+; CHECK-LABEL: test_builtin_ppc_mulhdu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhdu 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhdu(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.mulhdu(i64, i64)
+
+define dso_local i64 @test_builtin_ppc_maddhd(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: test_builtin_ppc_maddhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:maddhd 3, 3, 4, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.maddhd(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.maddhd(i64, i64, i64)
+
+define dso_local i64 @test_builtin_ppc_maddhdu(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: test_builtin_ppc_maddhdu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:maddhdu 3, 3, 4, 5
+; CHECK-NEXT:blr

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 358397.
NeHuang marked 4 inline comments as done.
NeHuang added a comment.

Addressed review comments from Nemanja.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102875/new/

https://reviews.llvm.org/D102875

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+
+define dso_local signext i32 @test_builtin_ppc_mulhw(i32 %a, i32%b) {
+; CHECK-32-LABEL: test_builtin_ppc_mulhw:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhw 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhw:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhw 3, 3, 4
+; CHECK-64-NEXT:extsw 3, 3
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhw(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.mulhw(i32, i32)
+
+define dso_local zeroext i32 @test_builtin_ppc_mulhwu(i32 %a, i32%b) {
+; CHECK-32-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhwu 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhwu 3, 3, 4
+; CHECK-64-NEXT:clrldi 3, 3, 32
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhwu(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.mulhwu(i32, i32)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @test_builtin_ppc_mulhd(i64 %a, i64 %b) {
+; CHECK-LABEL: test_builtin_ppc_mulhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhd 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhd(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.mulhd(i64, i64)
+
+define dso_local i64 @test_builtin_ppc_mulhdu(i64 %a, i64 %b) {
+; CHECK-LABEL: test_builtin_ppc_mulhdu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhdu 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhdu(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.mulhdu(i64, i64)
+
+define dso_local i64 @test_builtin_ppc_maddhd(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: test_builtin_ppc_maddhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:maddhd 3, 3, 4, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.maddhd(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.maddhd(i64, i64, i64)
+
+define dso_local i64 @test_builtin_ppc_maddhdu(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: test_builtin_ppc_maddhdu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:maddhdu 3, 3, 4, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.maddhdu(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.maddhdu(i64, i64, i64)
+
+define dso_local i64 @test_builtin_ppc_maddld(i64 %a, i64 %b, 

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

[Victor Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG10e0cdfc6526: [PowerPC][NFC] Power ISA features for 
Semachecking (authored by NeHuang).

Changed prior to commit:
  https://reviews.llvm.org/D105501?vs=358049=358285#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Sema/SemaChecking.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h

Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -146,6 +146,7 @@
   bool HasStoreFusion;
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
+  bool IsISA2_07;
   bool IsISA3_0;
   bool IsISA3_1;
   bool UseLongCalls;
@@ -319,6 +320,7 @@
 
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
+  bool isISA2_07() const { return IsISA2_07; }
   bool isISA3_0() const { return IsISA3_0; }
   bool isISA3_1() const { return IsISA3_1; }
   bool useLongCalls() const { return UseLongCalls; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -126,6 +126,7 @@
   HasStoreFusion = false;
   HasAddiLoadFusion = false;
   HasAddisLoadFusion = false;
+  IsISA2_07 = false;
   IsISA3_0 = false;
   IsISA3_1 = false;
   UseLongCalls = false;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1176,6 +1176,7 @@
 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
 def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
 def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
+def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
 def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
 def HasFPU : Predicate<"Subtarget->hasFPU()">;
 def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -210,9 +210,13 @@
 def DeprecatedDST: SubtargetFeature<"", "DeprecatedDST", "true",
   "Treat vector data stream cache control instructions as deprecated">;
 
+def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
+  "true",
+  "Enable instructions in ISA 2.07.">;
 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
  "true",
- "Enable instructions in ISA 3.0.">;
+ "Enable instructions in ISA 3.0.",
+ [FeatureISA2_07]>;
 def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
  "true",
  "Enable instructions in ISA 3.1.",
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3275,10 +3275,18 @@
 }
 
 static bool SemaFeatureCheck(Sema , CallExpr *TheCall,
- StringRef FeatureToCheck, unsigned DiagID) {
-  if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck))
-return S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange();
-  return false;
+ StringRef FeatureToCheck, unsigned DiagID,
+ StringRef DiagArg = "") {
+  if (S.Context.getTargetInfo().hasFeature(FeatureToCheck))
+return false;
+
+  if (DiagArg.empty())
+S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange();
+  else
+S.Diag(TheCall->getBeginLoc(), DiagID)
+<< DiagArg << TheCall->getSourceRange();
+
+  return true;
 }
 
 bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo , unsigned BuiltinID,
@@ -3320,17 +3328,17 @@
   case PPC::BI__builtin_divde:
   case PPC::BI__builtin_divdeu:
 return SemaFeatureCheck(*this, TheCall, "extdiv",
-diag::err_ppc_builtin_only_on_pwr7);
+diag::err_ppc_builtin_only_on_arch, "7");
   case PPC::BI__builtin_bpermd:
 return SemaFeatureCheck(*this, TheCall, "bpermd",
-

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll:9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+

amyk wrote:
> Does it make sense to add pre-P9 for these instructions that existed prior to 
> P9?
Will merge in Power ISA features Sema checking patch 
https://reviews.llvm.org/D105501 for pwr9+ only sema checking once approved.


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[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

Need to merge with https://reviews.llvm.org/D105501 changes once approved for 
pwr9 (or later processor) only sema checking.


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[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 357626.
NeHuang added a comment.

Remove entry check in test case.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-compare.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
@@ -0,0 +1,54 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+// CHECK-LABEL: @test_builtin_ppc_cmpb(
+// CHECK-NEXT:[[LLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK-NEXT:[[LLB_ADDR:%.*]] = alloca i64, align 8
+// CHECK-NEXT:store i64 [[LLA:%.*]], i64* [[LLA_ADDR]], align 8
+// CHECK-NEXT:store i64 [[LLB:%.*]], i64* [[LLB_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load i64, i64* [[LLA_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* [[LLB_ADDR]], align 8
+// CHECK-NEXT:[[TMP2:%.*]] = xor i64 [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP3:%.*]] = and i64 [[TMP2]], 255
+// CHECK-NEXT:[[TMP4:%.*]] = icmp eq i64 [[TMP3]], 0
+// CHECK-NEXT:[[TMP5:%.*]] = select i1 [[TMP4]], i64 255, i64 0
+// CHECK-NEXT:[[TMP6:%.*]] = or i64 0, [[TMP5]]
+// CHECK-NEXT:[[TMP7:%.*]] = and i64 [[TMP2]], 65280
+// CHECK-NEXT:[[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
+// CHECK-NEXT:[[TMP9:%.*]] = select i1 [[TMP8]], i64 65280, i64 0
+// CHECK-NEXT:[[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
+// CHECK-NEXT:[[TMP11:%.*]] = and i64 [[TMP2]], 16711680
+// CHECK-NEXT:[[TMP12:%.*]] = icmp eq i64 [[TMP11]], 0
+// CHECK-NEXT:[[TMP13:%.*]] = select i1 [[TMP12]], i64 16711680, i64 0
+// CHECK-NEXT:[[TMP14:%.*]] = or i64 [[TMP10]], [[TMP13]]
+// CHECK-NEXT:[[TMP15:%.*]] = and i64 [[TMP2]], 4278190080
+// CHECK-NEXT:[[TMP16:%.*]] = icmp eq i64 [[TMP15]], 0
+// CHECK-NEXT:[[TMP17:%.*]] = select i1 [[TMP16]], i64 4278190080, i64 0
+// CHECK-NEXT:[[TMP18:%.*]] = or i64 [[TMP14]], [[TMP17]]
+// CHECK-NEXT:[[TMP19:%.*]] = and i64 [[TMP2]], 1095216660480
+// CHECK-NEXT:[[TMP20:%.*]] = icmp eq i64 [[TMP19]], 0
+// CHECK-NEXT:[[TMP21:%.*]] = select i1 [[TMP20]], i64 1095216660480, i64 0
+// CHECK-NEXT:[[TMP22:%.*]] = or i64 [[TMP18]], [[TMP21]]
+// CHECK-NEXT:[[TMP23:%.*]] = and i64 [[TMP2]], 280375465082880
+// CHECK-NEXT:[[TMP24:%.*]] = icmp eq i64 [[TMP23]], 0
+// CHECK-NEXT:[[TMP25:%.*]] = select i1 [[TMP24]], i64 280375465082880, i64 0
+// CHECK-NEXT:[[TMP26:%.*]] = or i64 [[TMP22]], [[TMP25]]
+// CHECK-NEXT:[[TMP27:%.*]] = and i64 [[TMP2]], 71776119061217280
+// CHECK-NEXT:[[TMP28:%.*]] = icmp eq i64 [[TMP27]], 0
+// CHECK-NEXT:[[TMP29:%.*]] = select i1 [[TMP28]], i64 71776119061217280, i64 0
+// CHECK-NEXT:[[TMP30:%.*]] = or i64 [[TMP26]], [[TMP29]]
+// CHECK-NEXT:[[TMP31:%.*]] = and i64 [[TMP2]], -72057594037927936
+// CHECK-NEXT:[[TMP32:%.*]] = icmp eq i64 [[TMP31]], 0
+// CHECK-NEXT:[[TMP33:%.*]] = select i1 [[TMP32]], i64 -72057594037927936, i64 0
+// CHECK-NEXT:[[TMP34:%.*]] = or i64 [[TMP30]], [[TMP33]]
+// CHECK-NEXT:ret i64 [[TMP34]]
+//
+long long test_builtin_ppc_cmpb(long long lla, long long llb) {
+  return __builtin_ppc_cmpb(lla, llb);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15078,6 +15078,21 @@
 Value *shift = Builder.CreateCall(F, {Ops[0], Ops[0], Ops[1]});
 return Builder.CreateAnd(shift, Ops[2]);
   }
+  case PPC::BI__builtin_ppc_cmpb: {
+llvm::Type *Ty = Ops[0]->getType();
+Value *Zero = Constant::getNullValue(Ty);
+Value *Res = Constant::getNullValue(Ty);
+Value *X = Builder.CreateXor(Ops[0], Ops[1]);
+for (int i = 0; i < 8; i++) {
+  int64_t Mask = (int64_t)0xff << i * 8;
+  Value *Cmp = Builder.CreateICmpEQ(
+  Builder.CreateAnd(X, ConstantInt::getSigned(Ty, Mask)), Zero);
+  Value *Select =
+  Builder.CreateSelect(Cmp, ConstantInt::getSigned(Ty, Mask), Zero);
+  Res = Builder.CreateOr(Res, Select);
+}
+return Res;
+  }
   // Copy sign
   case PPC::BI__builtin_vsx_xvcpsgnsp:
   case PPC::BI__builtin_vsx_xvcpsgndp: {
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- 

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:3356
+  case PPC::BI__builtin_ppc_maddld:
+return SemaFeatureCheck(*this, TheCall, "power9-vector",
+diag::err_ppc_builtin_only_on_pwr9);

amyk wrote:
> This is just a question. 
> Is `power9-vector` the correct feature check in these cases? Does it matter 
> if these are not vector instructions?
yeah, we planned using this feature to do the sema check for `pwr9` only (or 
later cpus) builtins.


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[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 357625.
NeHuang marked 3 inline comments as done.
NeHuang added a comment.

Address review comments on test case and remove change not needed.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+
+define dso_local signext i32 @test_builtin_ppc_mulhw(i32 %a, i32%b) {
+; CHECK-32-LABEL: test_builtin_ppc_mulhw:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhw 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhw:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhw 3, 3, 4
+; CHECK-64-NEXT:extsw 3, 3
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhw(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.mulhw(i32, i32)
+
+define dso_local zeroext i32 @test_builtin_ppc_mulhwu(i32 %a, i32%b) {
+; CHECK-32-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhwu 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhwu 3, 3, 4
+; CHECK-64-NEXT:clrldi 3, 3, 32
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhwu(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.mulhwu(i32, i32)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @test_builtin_ppc_mulhd(i64 %a, i64 %b) {
+; CHECK-LABEL: test_builtin_ppc_mulhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhd 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhd(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.mulhd(i64, i64)
+
+define dso_local i64 @test_builtin_ppc_mulhdu(i64 %a, i64 %b) {
+; CHECK-LABEL: test_builtin_ppc_mulhdu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhdu 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhdu(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.mulhdu(i64, i64)
+
+define dso_local i64 @test_builtin_ppc_maddhd(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: test_builtin_ppc_maddhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:maddhd 3, 3, 4, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.maddhd(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.maddhd(i64, i64, i64)
+
+define dso_local i64 @test_builtin_ppc_maddhdu(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: test_builtin_ppc_maddhdu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:maddhdu 3, 3, 4, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.maddhdu(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+declare i64 

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

gentle ping


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[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

gentle ping.


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[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

gentle ping.


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[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang accepted this revision.
NeHuang added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks for addressing the comments!


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[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang resigned from this revision.
NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c:2
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \

Please use `pwr7` for BE test and `pwr8` for LE test.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c:8
+// RUN: not %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 2>&1 | \
+// RUN:  FileCheck %s -check-prefixes=CHECK32-ERROR

pwr8 -> pwr7



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c:11
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | \
+// RUN:  FileCheck %s --check-prefixes=CHECK64

pwr8 -> pwr7



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-trap.c:8
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | \
+// RUN:  FileCheck %s

same as above



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-trap.c:11
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | \
+// RUN:  FileCheck %s

same as above.



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll:7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \

same target cpu issue for the aix run lines in back end test cases.



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll:28
+}
+
+define dso_local void @test__tdweq(i64 %a, i64 %b) {

can you add another test case for `call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 
3)` to verify the backend change below:
```
// tdne
def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 3),
  (TD 24, $A, $B)>;
```



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll:41
+; CHECK:   # %bb.0:
+; CHECK-NEXT:td 5, 3, 4
+; CHECK-NEXT:blr

seems the InstAlias defined for `td` and `tw` not working as expected 



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[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 356701.
NeHuang marked 4 inline comments as done.
NeHuang added a comment.

Address review comments on the test case. Target cpu sema checking covered in 
front end test cases. will keep current coverage in backend test.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+
+define dso_local signext i32 @test_builtin_ppc_mulhw(i32 %a, i32%b) {
+; CHECK-32-LABEL: test_builtin_ppc_mulhw:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhw 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhw:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhw 3, 3, 4
+; CHECK-64-NEXT:extsw 3, 3
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhw(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.mulhw(i32, i32)
+
+define dso_local zeroext i32 @test_builtin_ppc_mulhwu(i32 %a, i32%b) {
+; CHECK-32-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhwu 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhwu 3, 3, 4
+; CHECK-64-NEXT:clrldi 3, 3, 32
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhwu(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.mulhwu(i32, i32)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @test_builtin_ppc_mulhd(i64 %a, i64 %b) {
+; CHECK-LABEL: test_builtin_ppc_mulhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhd 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhd(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.mulhd(i64, i64)
+
+define dso_local i64 @test_builtin_ppc_mulhdu(i64 %a, i64 %b) {
+; CHECK-LABEL: test_builtin_ppc_mulhdu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhdu 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhdu(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.mulhdu(i64, i64)
+
+define dso_local i64 @test_builtin_ppc_maddhd(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: test_builtin_ppc_maddhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:maddhd 3, 3, 4, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.maddhd(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+declare i64 @llvm.ppc.maddhd(i64, i64, i64)
+
+define dso_local i64 @test_builtin_ppc_maddhdu(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: test_builtin_ppc_maddhdu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:maddhdu 3, 3, 4, 5
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 

[PATCH] D105236: [PowerPC] Implament Load and Reserve and Store Conditional Builtins

[Victor Huang via Phabricator via cfe-commits]

NeHuang accepted this revision as: NeHuang.
NeHuang added a comment.
This revision is now accepted and ready to land.

Overall LGTM.


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[PATCH] D105236: [PowerPC] Implament Load and Reserve and Store Conditional Builtins

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: 
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c:1
+// RUN: not %clang_cc1 -triple=powerpc-unknown-aix -O2 -S -emit-llvm %s -o - 
2>&1 |\
+// RUN: FileCheck %s --check-prefix=CHECK32-ERROR

`-S` seems redundant.
Any reason we need `-O2` for these tests?



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:1
+// RUN: %clang_cc1 -triple=powerpc-unknown-aix -O2 -S -emit-llvm %s -o - | \
+// RUN: FileCheck %s

same as above.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:11
+int test_lwarx(volatile int* a) {
+  // CHECK: entry:
+  // CHECK: %0 = bitcast i32* %a to i8*

stefanp wrote:
> Please check that this "entry:" is printed out when asserts are on and when 
> asserts are off you may want to remove it at this point.
> 
> I would prefer you check the name of the function instead of "entry". You can 
> use `CHECK-LABEL` to do that. 
Agreed. We should first do `CHECK-LABEL` with the function name.


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[PATCH] D105236: [PowerPC] Implament Load and Reserve and Store Conditional Builtins

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

Please add the sema check & error test case for the two 64 bit only builtins 
`ldarx` and `stdcx`




Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64-only.ll:10
+declare i64 @llvm.ppc.ldarx(i8*)
+define dso_local i64 @test_ldarx(i64* readnone %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_ldarx:

remove `local_unnamed_addr #0`



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64-only.ll:22
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+define dso_local i64 @test(i64* %a, i64 %b) local_unnamed_addr #0 {
+; CHECK-LABEL: test:

remove `local_unnamed_addr #0`



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll:12
+declare i32 @llvm.ppc.lwarx(i8*)
+define dso_local signext i32 @test_lwarx(i32* readnone %a) local_unnamed_addr 
#0 {
+; CHECK-64-LABEL: test_lwarx:

remove `local_unnamed_addr #0`



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll:30
+declare i32 @llvm.ppc.stwcx(i8*, i32)
+define dso_local signext i32 @test_stwcx(i32* %a, i32 signext %b) 
local_unnamed_addr #0 {
+; CHECK-64-LABEL: test_stwcx:

remove `local_unnamed_addr #0`


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[PATCH] D105360: [PowerPC] Fix popcntb XL Compat Builtin for 32bit

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-sync.c:240
+void test_icbt() {
+  __icbt(c);
 }

From the document, `__icbt` only valid when -qarch is set to target pwr8 or 
higher processors. It looks like target cpu sema checking and error case are 
missing. If you are working on another patch to fix it, please put fixme 
comments for the __icbt implementation and test case in this patch. 



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-sync.c:467
+//
+void test_builtin_ppc_icbt() {
+  __builtin_ppc_icbt(c);

same as above.



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll:83
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3

same here, pwr8 (or later processors) only


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[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll:18
+
+define dso_local double @test_fsel(double %a, double %b, double %c) 
local_unnamed_addr #0 {
+; CHECK-PWR7-LABEL: test_fsel 

you can remove  `#0`, `#1` and `#2`


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[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

Overall looks good. Some nits as below.




Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-fp.c:9
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+double test_fric(double a) {

- You can define three extern variables for all the bulitins.
```
extern double a;
extern float b；
extern float c；
```
- You can auto update the test case with utils/update_cc_test_checks.py



Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:4990
   case ISD::INTRINSIC_WO_CHAIN: {
+
+if (N->getConstantOperandVal(0) == Intrinsic::ppc_fsels) {

you can delete blank line and better add comments for the operation below.



Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:4992
+if (N->getConstantOperandVal(0) == Intrinsic::ppc_fsels) {
+  SDValue ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3)};
+  CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32, ops);

Please use `Ops` as the variable name.


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[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang requested changes to this revision.
NeHuang added inline comments.
This revision now requires changes to proceed.



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:32
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")

seems like rebase issue that comments got overwritten.



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:50
 BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")

definition here not matching prototype in document 
```
void __tdw ( long a, long b, unsigned int TO);
```



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:51
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")

prototype 
```
void __tw (int a, int b, unsigned int TO);
```
why not using `Ui` for the last arg?  



Comment at: clang/lib/Sema/SemaChecking.cpp:3347
+  case PPC::BI__builtin_ppc_tw:
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  case PPC::BI__builtin_ppc_tdw:

range suppose to be 0 to 31 based on document.



Comment at: clang/lib/Sema/SemaChecking.cpp:3349
+  case PPC::BI__builtin_ppc_tdw:
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \

same as above.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c:2
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \

are these builtins all pwr9 only? 
- If yes, please rename the file. 
- If not, please use pwr8 for LE test and pwr7 for BE cases.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c:9
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+
+double test_fcfid(double a) {

you can define extern variables here for the bulitins.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-error.c:16
+#ifdef __PPC64__
+  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the 
valid range [1, 31]}}
+#endif

range should be 0 to 31 as described in document.
```
TO A value of 0 to 31 inclusive. Each bit position, if set, indicates one or 
more of
the following possible conditions:
```



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-error.c:18
+#endif
+  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid 
range [1, 31]}}
+}

same as above 



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-trap.c:2
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:  FileCheck %s --check-prefixes=CHECK64,CHECK

same as above.



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll:3
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \

32 bit and 64 bit results look identical, you do not need prefixes.


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[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, lei, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton.
NeHuang requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch add the builtin and emit target independent
code for __cmpb.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-compare.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
@@ -0,0 +1,56 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+// CHECK-LABEL: @test_builtin_ppc_cmpb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK-NEXT:[[LLB_ADDR:%.*]] = alloca i64, align 8
+// CHECK-NEXT:store i64 [[LLA:%.*]], i64* [[LLA_ADDR]], align 8
+// CHECK-NEXT:store i64 [[LLB:%.*]], i64* [[LLB_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load i64, i64* [[LLA_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* [[LLB_ADDR]], align 8
+// CHECK-NEXT:[[TMP2:%.*]] = xor i64 [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP3:%.*]] = and i64 [[TMP2]], 255
+// CHECK-NEXT:[[TMP4:%.*]] = icmp eq i64 [[TMP3]], 0
+// CHECK-NEXT:[[TMP5:%.*]] = select i1 [[TMP4]], i64 255, i64 0
+// CHECK-NEXT:[[TMP6:%.*]] = or i64 0, [[TMP5]]
+// CHECK-NEXT:[[TMP7:%.*]] = and i64 [[TMP2]], 65280
+// CHECK-NEXT:[[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
+// CHECK-NEXT:[[TMP9:%.*]] = select i1 [[TMP8]], i64 65280, i64 0
+// CHECK-NEXT:[[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
+// CHECK-NEXT:[[TMP11:%.*]] = and i64 [[TMP2]], 16711680
+// CHECK-NEXT:[[TMP12:%.*]] = icmp eq i64 [[TMP11]], 0
+// CHECK-NEXT:[[TMP13:%.*]] = select i1 [[TMP12]], i64 16711680, i64 0
+// CHECK-NEXT:[[TMP14:%.*]] = or i64 [[TMP10]], [[TMP13]]
+// CHECK-NEXT:[[TMP15:%.*]] = and i64 [[TMP2]], 4278190080
+// CHECK-NEXT:[[TMP16:%.*]] = icmp eq i64 [[TMP15]], 0
+// CHECK-NEXT:[[TMP17:%.*]] = select i1 [[TMP16]], i64 4278190080, i64 0
+// CHECK-NEXT:[[TMP18:%.*]] = or i64 [[TMP14]], [[TMP17]]
+// CHECK-NEXT:[[TMP19:%.*]] = and i64 [[TMP2]], 1095216660480
+// CHECK-NEXT:[[TMP20:%.*]] = icmp eq i64 [[TMP19]], 0
+// CHECK-NEXT:[[TMP21:%.*]] = select i1 [[TMP20]], i64 1095216660480, i64 0
+// CHECK-NEXT:[[TMP22:%.*]] = or i64 [[TMP18]], [[TMP21]]
+// CHECK-NEXT:[[TMP23:%.*]] = and i64 [[TMP2]], 280375465082880
+// CHECK-NEXT:[[TMP24:%.*]] = icmp eq i64 [[TMP23]], 0
+// CHECK-NEXT:[[TMP25:%.*]] = select i1 [[TMP24]], i64 280375465082880, i64 0
+// CHECK-NEXT:[[TMP26:%.*]] = or i64 [[TMP22]], [[TMP25]]
+// CHECK-NEXT:[[TMP27:%.*]] = and i64 [[TMP2]], 71776119061217280
+// CHECK-NEXT:[[TMP28:%.*]] = icmp eq i64 [[TMP27]], 0
+// CHECK-NEXT:[[TMP29:%.*]] = select i1 [[TMP28]], i64 71776119061217280, i64 0
+// CHECK-NEXT:[[TMP30:%.*]] = or i64 [[TMP26]], [[TMP29]]
+// CHECK-NEXT:[[TMP31:%.*]] = and i64 [[TMP2]], -72057594037927936
+// CHECK-NEXT:[[TMP32:%.*]] = icmp eq i64 [[TMP31]], 0
+// CHECK-NEXT:[[TMP33:%.*]] = select i1 [[TMP32]], i64 -72057594037927936, i64 0
+// CHECK-NEXT:[[TMP34:%.*]] = or i64 [[TMP30]], [[TMP33]]
+// CHECK-NEXT:ret i64 [[TMP34]]
+//
+long long test_builtin_ppc_cmpb(long long lla, long long llb) {
+  return __builtin_ppc_cmpb(lla, llb);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15078,6 +15078,21 @@
 Value *shift = Builder.CreateCall(F, {Ops[0], Ops[0], Ops[1]});
 return Builder.CreateAnd(shift, Ops[2]);
   }
+  case PPC::BI__builtin_ppc_cmpb: {
+llvm::Type *Ty = Ops[0]->getType();
+Value *Zero = Constant::getNullValue(Ty);
+Value *Res = Constant::getNullValue(Ty);
+Value *X = Builder.CreateXor(Ops[0], Ops[1]);
+for (int i = 0; i < 8; i++) {
+  int64_t Mask = (int64_t)0xff << i * 8;
+  Value *Cmp = Builder.CreateICmpEQ(
+  Builder.CreateAnd(X, ConstantInt::getSigned(Ty, Mask)), Zero);
+  Value 

[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 354082.
NeHuang added a comment.

- Rebased the patch with ToT and the patch https://reviews.llvm.org/D102875
- Create the patch with all contexts. (Thanks @qiucf)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104744/new/

https://reviews.llvm.org/D104744

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,56 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+  // CHECK-LABEL: test_builtin_ppc_rldimi
+  // CHECK:   %res = alloca i64, align 8
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+  // CHECK-NEXT:  store i64 [[RF]], i64* %res, align 8
+  // CHECK-NEXT:  ret void
+
+  /*shift = 63, mask = 0x00FFF000 = 72057593769492480, ~mask = 0xFF000FFF = -72057593769492481*/
+  unsigned long long res = __builtin_ppc_rldimi(ull, ull, 63, 0x00FFF000);
+}
+
+void test_builtin_ppc_rlwimi() {
+  // CHECK-LABEL: test_builtin_ppc_rlwimi
+  // CHECK:   %res = alloca i32, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+  // CHECK-NEXT:  store i32 [[RF]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*shift = 31, mask = 0x00 = 16776960, ~mask = 0xFFFF = -16776961*/
+  unsigned int res = __builtin_ppc_rlwimi(ui, ui, 31, 0x00);
+}
+
+void test_builtin_ppc_rlwnm() {
+  // CHECK-LABEL: test_builtin_ppc_rlwnm
+  // CHECK:   %res = alloca i32, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 511
+  // CHECK-NEXT:  store i32 [[RC]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*shift = 31, mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -0,0 +1,37 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+  unsigned int shift;
+  unsigned long long mask;
+  unsigned long long res = __builtin_ppc_rldimi(ull, ull, shift, 7); // expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+  res = __builtin_ppc_rldimi(ull, ull, 63, mask);// expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+  res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00);  // expected-error {{argument 3 value should represent a contiguous bit field}}
+}
+
+void test_builtin_ppc_rlwimi() {
+  unsigned int shift;
+  unsigned int mask;
+  unsigned int res = __builtin_ppc_rlwimi(ui, ui, shift, 7); // expected-error {{argument to 

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 354081.
NeHuang added a comment.

- Added Sema check for the pwr9 only builtins and updated the test cases.
- Rebased the patch with ToT.
- Cleaned up the test cases and address review comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102875/new/

https://reviews.llvm.org/D102875

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+
+; Function Attrs: noinline nounwind optnone
+define dso_local signext i32 @test_builtin_ppc_mulhw(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhw:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhw 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhw:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhw 3, 3, 4
+; CHECK-64-NEXT:extsw 3, 3
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhw(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhw(i32, i32) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local zeroext i32 @test_builtin_ppc_mulhwu(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhwu 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhwu 3, 3, 4
+; CHECK-64-NEXT:clrldi 3, 3, 32
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhwu(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhwu(i32, i32) #1
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind readnone }
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
@@ -0,0 +1,82 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhd(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_mulhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhd 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhd(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.mulhd(i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhdu(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_mulhdu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhdu 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhdu(i64 %a, i64 %b)
+  ret 

[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, PowerPC.
NeHuang added projects: LLVM, clang.
Herald added subscribers: shchenz, kbarton.
NeHuang requested review of this revision.
Herald added a subscriber: cfe-commits.

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtins and emit target independent 
code for rotate related operations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D104744

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,56 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+  // CHECK-LABEL: test_builtin_ppc_rldimi
+  // CHECK:   %res = alloca i64, align 8
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+  // CHECK-NEXT:  store i64 [[RF]], i64* %res, align 8
+  // CHECK-NEXT:  ret void
+
+  /*shift = 63, mask = 0x00FFF000 = 72057593769492480, ~mask = 0xFF000FFF = -72057593769492481*/
+  unsigned long long res = __builtin_ppc_rldimi(ull, ull, 63, 0x00FFF000);
+}
+
+void test_builtin_ppc_rlwimi() {
+  // CHECK-LABEL: test_builtin_ppc_rlwimi
+  // CHECK:   %res = alloca i32, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+  // CHECK-NEXT:  store i32 [[RF]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*shift = 31, mask = 0x00 = 16776960, ~mask = 0xFFFF = -16776961*/
+  unsigned int res = __builtin_ppc_rlwimi(ui, ui, 31, 0x00);
+}
+
+void test_builtin_ppc_rlwnm() {
+  // CHECK-LABEL: test_builtin_ppc_rlwnm
+  // CHECK:   %res = alloca i32, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 511
+  // CHECK-NEXT:  store i32 [[RC]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*shift = 31, mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -10,9 +10,32 @@
 // RUN:   -Wall -Werror -verify %s
 
 extern unsigned int ui;
+extern unsigned long long ull;
 
 void test_builtin_ppc_cmprb() {
   int res =  __builtin_ppc_cmprb(3, ui, ui); //expected-error {{argument value 3 is outside the valid range [0, 1]}}
 }
 
+void test_builtin_ppc_rldimi() {
+  unsigned int shift;
+  unsigned long long mask;
+  unsigned long long res = __builtin_ppc_rldimi(ull, ull, shift, 7); // expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+  res = __builtin_ppc_rldimi(ull, ull, 63, mask);// expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+  res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00);  // expected-error {{argument 3 value should represent a contiguous bit field}}
+}
+
+void test_builtin_ppc_rlwimi() {
+  unsigned int shift;
+  unsigned int mask;
+  unsigned int res = __builtin_ppc_rlwimi(ui, ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwimi' must be a constant integer}}
+  res = 

[PATCH] D104664: [PowerPC][NFC] Clean up builtin sema checks

[Victor Huang via Phabricator via cfe-commits]

NeHuang accepted this revision.
NeHuang added a comment.
This revision is now accepted and ready to land.

LGTM. Please give it some time (~24hrs) before commit to wait for the other 
reviewers' comment.


Repository:
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[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 352560.
NeHuang added a comment.

- Add AIX 32&64 bit run line checks (front and back end test cases)
- Create builtin-ppc-xlcompat-error.c for arguments related error check, add 
error test case for `__builtin_ppc_cmprb`
- Remove 32 bit linux run line checks
- Update bulitin test cases to remove redundant definitions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102875/new/

https://reviews.llvm.org/D102875

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-compare-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+
+; Function Attrs: noinline nounwind optnone
+define dso_local signext i32 @test_builtin_ppc_mulhw(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhw:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhw 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhw:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhw 3, 3, 4
+; CHECK-64-NEXT:extsw 3, 3
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhw(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhw(i32, i32) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local zeroext i32 @test_builtin_ppc_mulhwu(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhwu 3, 3, 4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhwu 3, 3, 4
+; CHECK-64-NEXT:clrldi 3, 3, 32
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhwu(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhwu(i32, i32) #1
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind readnone }
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
@@ -0,0 +1,82 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhd(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_mulhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhd 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhd(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.mulhd(i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhdu(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_mulhdu:
+; CHECK:   # %bb.0: # %entry
+; 

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 351989.
NeHuang added a comment.

Rebased the patch with changes in https://reviews.llvm.org/D104125


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102875/new/

https://reviews.llvm.org/D102875

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-compare-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-64
+
+; Function Attrs: noinline nounwind optnone
+define dso_local signext i32 @test_builtin_ppc_mulhw(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhw:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhw r3, r3, r4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhw:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhw r3, r3, r4
+; CHECK-64-NEXT:extsw r3, r3
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhw(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhw(i32, i32) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local zeroext i32 @test_builtin_ppc_mulhwu(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhwu r3, r3, r4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhwu r3, r3, r4
+; CHECK-64-NEXT:clrldi r3, r3, 32
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhwu(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhwu(i32, i32) #1
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind readnone }
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhd(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_mulhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhd r3, r3, r4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhd(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.mulhd(i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhdu(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_mulhdu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhdu r3, r3, r4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 350991.
NeHuang added a comment.

- Renamed the XLCompat builtin as `__builtin_ppc_*` and add them to 
`definedXLCompatMacros` and update the test cases.
- Report error in SemaChecking when 64 bit only builtins run on a 32 bit target 
and update the test cases.
- Move the XLCompat Intrinsics definition under

  let TargetPrefix = "ppc" in {
  ...
  }


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102875/new/

https://reviews.llvm.org/D102875

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-compare-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-64
+
+; Function Attrs: noinline nounwind optnone
+define dso_local signext i32 @test_builtin_ppc_mulhw(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhw:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhw r3, r3, r4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhw:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhw r3, r3, r4
+; CHECK-64-NEXT:extsw r3, r3
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhw(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhw(i32, i32) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local zeroext i32 @test_builtin_ppc_mulhwu(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhwu r3, r3, r4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhwu r3, r3, r4
+; CHECK-64-NEXT:clrldi r3, r3, 32
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhwu(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhwu(i32, i32) #1
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind readnone }
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhd(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_mulhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhd r3, r3, r4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhd(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.mulhd(i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
NeHuang requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This is patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtins and instrisics for compare
and multiply related operations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102875

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-compare-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-64
+
+; Function Attrs: noinline nounwind optnone
+define dso_local signext i32 @test_builtin_ppc_mulhw(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhw:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhw r3, r3, r4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhw:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhw r3, r3, r4
+; CHECK-64-NEXT:extsw r3, r3
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhw(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhw(i32, i32) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local zeroext i32 @test_builtin_ppc_mulhwu(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:mulhwu r3, r3, r4
+; CHECK-32-NEXT:blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:mulhwu r3, r3, r4
+; CHECK-64-NEXT:clrldi r3, r3, 32
+; CHECK-64-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhwu(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhwu(i32, i32) #1
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind readnone }
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhd(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_mulhd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mulhd r3, r3, r4
+; CHECK-NEXT:blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhd(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.mulhd(i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhdu(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: 

[PATCH] D102070: [AIX][TLS] Diagnose use of unimplemented TLS models

[Victor Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG46475a79f85b: [AIX][TLS] Diagnose use of unimplemented TLS 
models (authored by NeHuang).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102070/new/

https://reviews.llvm.org/D102070

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aix-tls-model.cpp
  clang/test/Sema/aix-attr-tls_model.c

Index: clang/test/Sema/aix-attr-tls_model.c
===
--- /dev/null
+++ clang/test/Sema/aix-attr-tls_model.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr8 -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr8 -verify -fsyntax-only %s
+
+#if !__has_attribute(tls_model)
+#error "Should support tls_model attribute"
+#endif
+
+static __thread int y __attribute((tls_model("global-dynamic"))); // no-warning
+static __thread int y __attribute((tls_model("local-dynamic"))); // expected-error {{TLS model 'local-dynamic' is not yet supported on AIX}}
+static __thread int y __attribute((tls_model("initial-exec"))); // expected-error {{TLS model 'initial-exec' is not yet supported on AIX}}
+static __thread int y __attribute((tls_model("local-exec"))); // expected-error {{TLS model 'local-exec' is not yet supported on AIX}}
Index: clang/test/CodeGen/aix-tls-model.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-tls-model.cpp
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LD-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s -check-prefix=CHECK-IE-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LD-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s -check-prefix=CHECK-IE-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LE-ERROR
+
+int z1 = 0;
+int z2;
+int __thread x;
+int f() {
+  static int __thread y;
+  return y++;
+}
+
+// CHECK-GD: @z1 ={{.*}} global i32 0
+// CHECK-GD: @z2 ={{.*}} global i32 0
+// CHECK-GD: @x ={{.*}} thread_local global i32 0
+// CHECK-GD: @_ZZ1fvE1y = internal thread_local global i32 0
+// CHECK-LD-ERROR:  error: TLS model 'local-dynamic' is not yet supported on AIX
+// CHECK-IE-ERROR:  error: TLS model 'initial-exec' is not yet supported on AIX
+// CHECK-LE-ERROR:  error: TLS model 'local-exec' is not yet supported on AIX
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -1935,6 +1935,12 @@
 return;
   }
 
+  if (S.Context.getTargetInfo().getTriple().isOSAIX() &&
+  Model != "global-dynamic") {
+S.Diag(LiteralLoc, diag::err_aix_attr_unsupported_tls_model) << Model;
+return;
+  }
+
   D->addAttr(::new (S.Context) TLSModelAttr(S.Context, AL, Model));
 }
 
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -1808,6 +1808,14 @@
 Opts.ExplicitEmulatedTLS = true;
   }
 
+  if (Arg *A = Args.getLastArg(OPT_ftlsmodel_EQ)) {
+if (T.isOSAIX()) {
+  StringRef Name = A->getValue();
+  if (Name != "global-dynamic")
+Diags.Report(diag::err_aix_unsupported_tls_model) << Name;
+}
+  }
+
   if (Arg *A = Args.getLastArg(OPT_fdenormal_fp_math_EQ)) {
 StringRef Val = A->getValue();
 Opts.FPDenormalMode = llvm::parseDenormalFPAttribute(Val);
Index: 

[PATCH] D102070: [AIX][TLS] Diagnose use of unimplemented TLS models

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 344258.
NeHuang added a comment.

Address review comment for the diagnostic message.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102070/new/

https://reviews.llvm.org/D102070

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aix-tls-model.cpp
  clang/test/Sema/aix-attr-tls_model.c

Index: clang/test/Sema/aix-attr-tls_model.c
===
--- /dev/null
+++ clang/test/Sema/aix-attr-tls_model.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr8 -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr8 -verify -fsyntax-only %s
+
+#if !__has_attribute(tls_model)
+#error "Should support tls_model attribute"
+#endif
+
+static __thread int y __attribute((tls_model("global-dynamic"))); // no-warning
+static __thread int y __attribute((tls_model("local-dynamic"))); // expected-error {{TLS model 'local-dynamic' is not yet supported on AIX}}
+static __thread int y __attribute((tls_model("initial-exec"))); // expected-error {{TLS model 'initial-exec' is not yet supported on AIX}}
+static __thread int y __attribute((tls_model("local-exec"))); // expected-error {{TLS model 'local-exec' is not yet supported on AIX}}
Index: clang/test/CodeGen/aix-tls-model.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-tls-model.cpp
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LD-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s -check-prefix=CHECK-IE-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LD-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s -check-prefix=CHECK-IE-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LE-ERROR
+
+int z1 = 0;
+int z2;
+int __thread x;
+int f() {
+  static int __thread y;
+  return y++;
+}
+
+// CHECK-GD: @z1 ={{.*}} global i32 0
+// CHECK-GD: @z2 ={{.*}} global i32 0
+// CHECK-GD: @x ={{.*}} thread_local global i32 0
+// CHECK-GD: @_ZZ1fvE1y = internal thread_local global i32 0
+// CHECK-LD-ERROR:  error: TLS model 'local-dynamic' is not yet supported on AIX
+// CHECK-IE-ERROR:  error: TLS model 'initial-exec' is not yet supported on AIX
+// CHECK-LE-ERROR:  error: TLS model 'local-exec' is not yet supported on AIX
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -1935,6 +1935,12 @@
 return;
   }
 
+  if (S.Context.getTargetInfo().getTriple().isOSAIX() &&
+  Model != "global-dynamic") {
+S.Diag(LiteralLoc, diag::err_aix_attr_unsupported_tls_model) << Model;
+return;
+  }
+
   D->addAttr(::new (S.Context) TLSModelAttr(S.Context, AL, Model));
 }
 
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -1808,6 +1808,14 @@
 Opts.ExplicitEmulatedTLS = true;
   }
 
+  if (Arg *A = Args.getLastArg(OPT_ftlsmodel_EQ)) {
+if (T.isOSAIX()) {
+  StringRef Name = A->getValue();
+  if (Name != "global-dynamic")
+Diags.Report(diag::err_aix_unsupported_tls_model) << Name;
+}
+  }
+
   if (Arg *A = Args.getLastArg(OPT_fdenormal_fp_math_EQ)) {
 StringRef Val = A->getValue();
 Opts.FPDenormalMode = llvm::parseDenormalFPAttribute(Val);
Index: clang/include/clang/Basic/DiagnosticSemaKinds.td
===
--- 

[PATCH] D102070: [AIX][TLS] Diagnose use of unimplemented TLS models

[Victor Huang via Phabricator via cfe-commits]

NeHuang updated this revision to Diff 343743.
NeHuang added a comment.

Addressed review comment for the diagnostic message and update the test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102070/new/

https://reviews.llvm.org/D102070

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aix-tls-model.cpp
  clang/test/Sema/aix-attr-tls_model.c

Index: clang/test/Sema/aix-attr-tls_model.c
===
--- /dev/null
+++ clang/test/Sema/aix-attr-tls_model.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr8 -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr8 -verify -fsyntax-only %s
+
+#if !__has_attribute(tls_model)
+#error "Should support tls_model attribute"
+#endif
+
+static __thread int y __attribute((tls_model("global-dynamic"))); // no-warning
+static __thread int y __attribute((tls_model("local-dynamic"))); // expected-error {{TLS model local-dynamic is not yet supported on AIX}}
+static __thread int y __attribute((tls_model("initial-exec"))); // expected-error {{TLS model initial-exec is not yet supported on AIX}}
+static __thread int y __attribute((tls_model("local-exec"))); // expected-error {{TLS model local-exec is not yet supported on AIX}}
Index: clang/test/CodeGen/aix-tls-model.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-tls-model.cpp
@@ -0,0 +1,27 @@
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LD-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s -check-prefix=CHECK-IE-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LD-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s -check-prefix=CHECK-IE-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LE-ERROR
+
+int z1 = 0;
+int z2;
+int __thread x;
+int f() {
+  static int __thread y;
+  return y++;
+}
+
+// CHECK-GD: @z1 ={{.*}} global i32 0
+// CHECK-GD: @z2 ={{.*}} global i32 0
+// CHECK-GD: @x ={{.*}} thread_local global i32 0
+// CHECK-GD: @_ZZ1fvE1y = internal thread_local global i32 0
+// CHECK-GD-ERROR:  error in backend: thread local storage not yet implemented on AIX
+// CHECK-LD-ERROR:  error: TLS model local-dynamic is not yet supported on AIX
+// CHECK-IE-ERROR:  error: TLS model initial-exec is not yet supported on AIX
+// CHECK-LE-ERROR:  error: TLS model local-exec is not yet supported on AIX
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -1935,6 +1935,12 @@
 return;
   }
 
+  if (S.Context.getTargetInfo().getTriple().isOSAIX() &&
+  Model != "global-dynamic") {
+S.Diag(LiteralLoc, diag::err_aix_attr_unsupported_tls_model) << Model;
+return;
+  }
+
   D->addAttr(::new (S.Context) TLSModelAttr(S.Context, AL, Model));
 }
 
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -1808,6 +1808,14 @@
 Opts.ExplicitEmulatedTLS = true;
   }
 
+  if (Arg *A = Args.getLastArg(OPT_ftlsmodel_EQ)) {
+if (T.isOSAIX()) {
+  StringRef Name = A->getValue();
+  if (Name != "global-dynamic")
+Diags.Report(diag::err_aix_unsupported_tls_model) << Name;
+}
+  }
+
   if (Arg *A = Args.getLastArg(OPT_fdenormal_fp_math_EQ)) {
 StringRef Val = A->getValue();
 Opts.FPDenormalMode = llvm::parseDenormalFPAttribute(Val);
Index: