[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

[Zakk Chen via Phabricator via cfe-commits]

khchen abandoned this revision.
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we don't need this patch because we already handle the empty target-abi module 
flag now.


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[PATCH] D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV

[Zakk Chen via Phabricator via cfe-commits]

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I'm not working on RISC-V now and please reference 
https://reviews.llvm.org/D132843#3770454 to see the follow-up work.


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[PATCH] D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata

[Zakk Chen via Phabricator via cfe-commits]

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I'm not working on RISC-V now and please reference 
https://reviews.llvm.org/D132843#3770454 to see the follow-up work.


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[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

LGTM. Thanks for clean up code!




Comment at: clang/include/clang/Basic/riscv_vector.td:820
+(Address0, ..., Address{NF - 1}, mask, Ptr, VL)
+(Address0, ..., Address{NF - 1}, mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, VL)

nit: there is no unmasked builtin comment here.



Comment at: clang/include/clang/Basic/riscv_vector.td:1035
+  Value *StrideOperand = Ops[PtrOperandIdx + 1];
+  Value *VLOperand = Ops[PtrOperandIdx + 2];
+  Operands.push_back(PtrOperand);

In fact, VLOperand is always coming from `Ops.back()`


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[PATCH] D140687: [Clang][RISCV] Use poison instead of undef

[Zakk Chen via Phabricator via cfe-commits]

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!!


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[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:847
+
+  // Intrinsic is in the form of below,
+  // Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)

After remove the builtins comment I don't have idea what's going on this piece 
of code. but I'm okay if there is no concern from the other reviewers.



Comment at: clang/include/clang/Basic/riscv_vector.td:869
 Operands.push_back(ConstantInt::get(Ops.back()->getType(), 
DefaultPolicy));
-assert(Operands.size() == NF + 4);
-  } else {
-// TA builtin: (val0 address, val1 address, ..., ptr, vl)
-// TU builtin: (val0 address, ..., passthru0, ..., ptr, vl)
-// intrinsic: (passthru0, passthru1, ..., ptr, vl)
-if (DefaultPolicy == TAIL_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 1]);
-} else {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(Ops[NF + I]);
-  Operands.push_back(Ops[2 * NF]);
-  Operands.push_back(Ops[2 * NF + 1]);
-}
-  }
+
   llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);

nit: nit: there is no assert now, is it still NFC? I'm not sure.


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[PATCH] D140389: [NFC][Clang][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

[Zakk Chen via Phabricator via cfe-commits]

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


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[PATCH] D138429: [clang][RISCV][NFC] Prevent data race in RVVType::computeType

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:284
+
+class RVVTypeCache {
+private:

nit: maybe we could add some comments to said the motivation for 
`RVVTypeCache`. 



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:289
+
+  static uint64_t computeRVVTypeHashValue(BasicType BT, int Log2LMUL,
+  PrototypeDescriptor Proto);

`static` could be eliminated now.


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[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

> Possible solution/results:
>
> 1. All functions in `a.o` and `b.o` using same target features during the 
> first build stage, `-march=rv64gc` for a.o, `-march=rv64g` for `b.o`, and 
> `-march` option given in LTO CodeGen stage is ignored, it only used for ELF 
> attribute use (this revision).
> 2. All functions in `a.o` and `b.o` using same target features during the 
> first build stage, `-march=rv64gc` for a.o, `-march=rv64g` for `b.o`, and 
> deduced arch info from those `.o` for ELF attribute use (D106347 
> ), `-march`
> 3. All functions in `a.o` and `b.o` re-compile with `-march=rv64gc_zba` and 
> ELF attribute use `rv64gc_zba`.
>
> Option 1: Require user use right `-march` option during LTO stage, and might 
> fill wrong/unexpected ELF attribute if give wrong `-march` or not even not 
> given in LTO stage.
> Option 2: Should be more ideal, but D106347 
>  seems no progress for a while.
> Option 3: This option will break IFUNC usage.

This patch (Option 1) is look good to me, but maybe we need to report a warning 
in linking stage if possible.
I think users may not easy to specific the right -march string when they're 
using external libraries.
We had discussed that before in here  
and here , it's why I proposed Option 
2  which encodes a module scope arch features 
in IR. IIRC, it's similar to what gcc did.


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[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D71387#3755056 , @lewis-revill 
wrote:

> I believe this patch is still relevant/necessary when using LTO for RISCV, so 
> can I ask if @khchen is able to update it to rebase/address the feedback? If 
> not, are there are any objections to me commandeering this revision to get it 
> landed?

Yes, you could command this revision to enable LTO, thank you!!


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[PATCH] D126750: [RISCV][Clang] Support policy function for all vector segment load.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG010f329803c8: [RISCV][Clang] Support policy function for all 
vector segment load. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126750?vs=433270=450064#toc

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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
@@ -6923,3 +6923,28 @@
   return vluxseg8ei64_v_f32mf2(v0, v1, v2, v3, v4, v5, v6, v7, base, bindex, vl);
 }
 
+// CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64( [[MERGE0:%.*]],  [[MERGE1:%.*]], i32* [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { ,  } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], * [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], * [[V1:%.*]], align 4
+// CHECK-RV64-NEXT:ret void
+//
+void test_vluxseg2ei32_v_i32mf2_tu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t merge0, vint32mf2_t merge1, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+  return vluxseg2ei32_v_i32mf2_tu(v0, v1, merge0, merge1, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32mf2_ta(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64( undef,  undef, i32* [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { ,  } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], * [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], * [[V1:%.*]], align 4
+// CHECK-RV64-NEXT:ret void
+//
+void test_vluxseg2ei32_v_i32mf2_ta(vint32mf2_t *v0, vint32mf2_t *v1, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+  return vluxseg2ei32_v_i32mf2_ta(v0, v1, base, bindex, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
@@ -9051,3 +9051,54 @@
   return vluxseg2ei8_v_i8mf8_m(v0, v1, mask, maskedoff0, maskedoff1, base, bindex, vl);
 }
 
+// CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32mf2_tuma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i32.i64( [[MERGE0:%.*]],  [[MERGE1:%.*]], i32* [[BASE:%.*]],  [[BINDEX:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { ,  } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], * [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], * [[V1:%.*]], align 4
+// CHECK-RV64-NEXT:ret void
+//
+void test_vluxseg2ei32_v_i32mf2_tuma(vint32mf2_t *v0, vint32mf2_t *v1, vbool64_t mask, vint32mf2_t merge0, vint32mf2_t merge1, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+  return vluxseg2ei32_v_i32mf2_tuma(v0, v1, mask, merge0, merge1, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32mf2_tumu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i32.i64( [[MERGE0:%.*]],  [[MERGE1:%.*]], i32* [[BASE:%.*]],  [[BINDEX:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { ,  } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], * [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], * 

[PATCH] D126749: [RISCV][Clang] Support policy functions for Vector Mask Instructions.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbb99d4b11d84: [RISCV][Clang] Support policy functions for 
Vector Mask Instructions. (authored by khchen).

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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsof_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsof_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsof.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsof_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsof_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsof_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsof.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsof_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsof_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsif_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsif_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsif.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsif_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsif_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsif_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsif.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsif_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsif_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsbf_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsbf_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsbf.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsbf_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsbf_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsbf_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsbf.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsbf_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsbf_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
@@ -204,7 +204,7 @@
 
 // CHECK-RV64-LABEL: @test_viota_m_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.viota.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.viota.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf8_t 

[PATCH] D126748: [RISCV][Clang] Support policy functions for Vector Reduction Instructions.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdffdca85ec2d: [RISCV][Clang] Support policy functions for 
Vector Reduction (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126748?vs=433267=449338#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126748/new/

https://reviews.llvm.org/D126748

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -194,6 +194,10 @@
   if (RVVI->hasMaskedOffOperand() &&
   RVVI->getDefaultPolicy() == Policy::TAMA)
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
+  // Masked reduction cases.
+  if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
+  RVVI->getDefaultPolicy() == Policy::TAMA)
+OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
 }
@@ -201,7 +205,8 @@
 if (RVVI->hasPolicyOperand())
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
 "DefaultPolicy));\n";
-else if (RVVI->hasPassthruOperand() && RVVI->getDefaultPolicy() == Policy::TA)
+else if (RVVI->hasPassthruOperand() &&
+ RVVI->getDefaultPolicy() == Policy::TA)
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
@@ -759,3 +759,75 @@
 vuint64m1_t scalar, size_t vl) {
   return vwredsumu_vs_u32m8_u64m1_m(mask, dst, vector, scalar, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64( [[MERGE:%.*]],  [[VECTOR:%.*]],  [[SCALAR:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tu(vint64m1_t merge, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
+  return vwredsum_vs_i32mf2_i64m1_tu(merge, vector, scalar, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsumu.nxv1i64.nxv1i32.i64( [[MERGE:%.*]],  [[VECTOR:%.*]],  [[SCALAR:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_tu(vuint64m1_t merge, vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
+  return vwredsumu_vs_u32mf2_u64m1_tu(merge, vector, scalar, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_ta(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64( undef,  [[VECTOR:%.*]],  [[SCALAR:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint64m1_t test_vwredsum_vs_i32mf2_i64m1_ta(vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
+  return vwredsum_vs_i32mf2_i64m1_ta(vector, scalar, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_ta(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  

[PATCH] D126746: [RISCV][Clang] Support policy functions for Vector Comparison Instructions.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9caf2cc05c02: [RISCV][Clang] Support policy functions for 
Vector Comparison (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126746/new/

https://reviews.llvm.org/D126746

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
@@ -1699,3 +1699,75 @@
   vuint64m8_t op1, uint64_t op2, size_t vl) {
   return vmsne_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_i32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmsne_vv_i32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vx_i32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.i32.i64( undef,  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
+  return vmsne_vx_i32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_u32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
+  return vmsne_vv_u32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vx_u32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.i32.i64( undef,  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
+  return vmsne_vx_u32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_i32mf2_b64_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmsne_vv_i32mf2_b64_mu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vx_i32mf2_b64_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.i32.i64( [[MERGE:%.*]],  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
+  return vmsne_vx_i32mf2_b64_mu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_u32mf2_b64_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7eddeb9e99f3: [RISCV][Clang] Support policy functions for 
vmerge, vfmerge and (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126745?vs=433263=449336#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126745/new/

https://reviews.llvm.org/D126745

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
@@ -981,7 +981,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1f16.nxv1f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf4_t test_vmerge_vvm_f16mf4 (vbool64_t mask, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
+vfloat16mf4_t test_vmerge_vvm_f16mf4(vbool64_t mask, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
   return vmerge_vvm_f16mf4(mask, op1, op2, vl);
 }
 
@@ -990,7 +990,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv2f16.nxv2f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf2_t test_vmerge_vvm_f16mf2 (vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
+vfloat16mf2_t test_vmerge_vvm_f16mf2(vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
   return vmerge_vvm_f16mf2(mask, op1, op2, vl);
 }
 
@@ -999,7 +999,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv4f16.nxv4f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m1_t test_vmerge_vvm_f16m1 (vbool16_t mask, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+vfloat16m1_t test_vmerge_vvm_f16m1(vbool16_t mask, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
   return vmerge_vvm_f16m1(mask, op1, op2, vl);
 }
 
@@ -1008,7 +1008,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv8f16.nxv8f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m2_t test_vmerge_vvm_f16m2 (vbool8_t mask, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
+vfloat16m2_t test_vmerge_vvm_f16m2(vbool8_t mask, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
   return vmerge_vvm_f16m2(mask, op1, op2, vl);
 }
 
@@ -1017,7 +1017,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv16f16.nxv16f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m4_t test_vmerge_vvm_f16m4 (vbool4_t mask, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
+vfloat16m4_t test_vmerge_vvm_f16m4(vbool4_t mask, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
   return vmerge_vvm_f16m4(mask, op1, op2, vl);
 }
 
@@ -1026,6 +1026,96 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv32f16.nxv32f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m8_t test_vmerge_vvm_f16m8 (vbool2_t mask, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
+vfloat16m8_t test_vmerge_vvm_f16m8(vbool2_t mask, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
   return vmerge_vvm_f16m8(mask, op1, op2, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmerge_vvm_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1i32.nxv1i32.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint32mf2_t test_vmerge_vvm_i32mf2_tu(vbool64_t mask, vint32mf2_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmerge_vvm_i32mf2_tu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmerge_vxm_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1i32.i32.i64( [[MERGE:%.*]],  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint32mf2_t test_vmerge_vxm_i32mf2_tu(vbool64_t mask, vint32mf2_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
+  return vmerge_vxm_i32mf2_tu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: 

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

@nlopes we will update all undef to poison in follow up patches.


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

oops.. all tests need to updated and include all intrinsic IR tests...
Is there any benefit to switch UndefValue to PoisonValue?
maybe those changed should be in other follow-up patches?


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D126745#3691544 , @craig.topper 
wrote:

> In D126745#3691528 , @khchen wrote:
>
>> In D126745#3678776 , @nlopes wrote:
>>
>>> While at it, could you switch those UndefValue with PoisonValue if 
>>> possible?  Thank you!
>>
>> I'm not sure UndefValue will work because the backend would only check 
>> isUndef() to generate correct code...
>
> PoisonValue and UndefValue are both turned into undef in SelectionDAG today.

thanks @craig.topper, I will switch UndefValue with PoisonValue.


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D126745#3678776 , @nlopes wrote:

> While at it, could you switch those UndefValue with PoisonValue if possible?  
> Thank you!

I'm not sure UndefValue will work because the backend would only check 
isUndef() to generate correct code...


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[PATCH] D126743: [RISCV][Clang] Add tests for all supported policy functions. (NFC)

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8e51917b39cd: [RISCV][Clang] Add tests for all supported 
policy functions. (NFC) (authored by khchen).

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Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c
  

[PATCH] D126741: [RISCV][Clang] Refactor RISCVVEmitter. (NFC)

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG93f8657c743b: [RISCV][Clang] Refactor RISCVVEmitter. (NFC) 
(authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126741?vs=433257=447634#toc

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -50,9 +50,6 @@
   // Prototype for this intrinsic.
   SmallVector Prototype;
 
-  // Prototype for masked intrinsic.
-  SmallVector MaskedPrototype;
-
   // Suffix of intrinsic name.
   SmallVector Suffix;
 
@@ -61,6 +58,10 @@
 
   // Number of field, large than 1 if it's segment load/store.
   unsigned NF;
+
+  bool HasMasked :1;
+  bool HasVL :1;
+  bool HasMaskedOffOperand :1;
 };
 
 // Compressed function signature table.
@@ -241,7 +242,6 @@
 
   llvm::for_each(SemaRecords, [&](const SemaRecord ) {
 InsertToSignatureSet(SR.Prototype);
-InsertToSignatureSet(SR.MaskedPrototype);
 InsertToSignatureSet(SR.Suffix);
 InsertToSignatureSet(SR.OverloadedSuffix);
   });
@@ -583,12 +583,10 @@
 }
 
 SR.NF = NF;
-
-SR.Prototype = std::move(Prototype);
-
-if (HasMasked)
-  SR.MaskedPrototype = std::move(MaskedPrototype);
-
+SR.HasMasked = HasMasked;
+SR.HasVL = HasVL;
+SR.HasMaskedOffOperand = HasMaskedOffOperand;
+SR.Prototype = std::move(BasicPrototype);
 SR.Suffix = parsePrototypes(SuffixProto);
 SR.OverloadedSuffix = parsePrototypes(OverloadedSuffixProto);
 
@@ -616,22 +614,21 @@
 R.Name = SR.Name.c_str();
 R.OverloadedName = SR.OverloadedName.c_str();
 R.PrototypeIndex = SST.getIndex(SR.Prototype);
-R.MaskedPrototypeIndex = SST.getIndex(SR.MaskedPrototype);
 R.SuffixIndex = SST.getIndex(SR.Suffix);
 R.OverloadedSuffixIndex = SST.getIndex(SR.OverloadedSuffix);
 R.PrototypeLength = SR.Prototype.size();
-R.MaskedPrototypeLength = SR.MaskedPrototype.size();
 R.SuffixLength = SR.Suffix.size();
 R.OverloadedSuffixSize = SR.OverloadedSuffix.size();
 R.RequiredExtensions = SR.RequiredExtensions;
 R.TypeRangeMask = SR.TypeRangeMask;
 R.Log2LMULMask = SR.Log2LMULMask;
 R.NF = SR.NF;
+R.HasMasked = SR.HasMasked;
+R.HasVL = SR.HasVL;
+R.HasMaskedOffOperand = SR.HasMaskedOffOperand;
 
 assert(R.PrototypeIndex !=
static_cast(SemaSignatureTable::INVALID_INDEX));
-assert(R.MaskedPrototypeIndex !=
-   static_cast(SemaSignatureTable::INVALID_INDEX));
 assert(R.SuffixIndex !=
static_cast(SemaSignatureTable::INVALID_INDEX));
 assert(R.OverloadedSuffixIndex !=
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -981,17 +981,18 @@
   else
 OS << "\"" << Record.OverloadedName << "\",";
   OS << Record.PrototypeIndex << ",";
-  OS << Record.MaskedPrototypeIndex << ",";
   OS << Record.SuffixIndex << ",";
   OS << Record.OverloadedSuffixIndex << ",";
   OS << (int)Record.PrototypeLength << ",";
-  OS << (int)Record.MaskedPrototypeLength << ",";
   OS << (int)Record.SuffixLength << ",";
   OS << (int)Record.OverloadedSuffixSize << ",";
   OS << (int)Record.RequiredExtensions << ",";
   OS << (int)Record.TypeRangeMask << ",";
   OS << (int)Record.Log2LMULMask << ",";
   OS << (int)Record.NF << ",";
+  OS << (int)Record.HasMasked << ",";
+  OS << (int)Record.HasVL << ",";
+  OS << (int)Record.HasMaskedOffOperand << ",";
   OS << "},\n";
   return OS;
 }
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -178,14 +178,23 @@
   for (auto  : RVVIntrinsicRecords) {
 // Create Intrinsics for each type and LMUL.
 BasicType BaseType = BasicType::Unknown;
-ArrayRef ProtoSeq =
+ArrayRef BasicProtoSeq =
 ProtoSeq2ArrayRef(Record.PrototypeIndex, Record.PrototypeLength);
-ArrayRef ProtoMaskSeq = ProtoSeq2ArrayRef(
-Record.MaskedPrototypeIndex, Record.MaskedPrototypeLength);
 ArrayRef SuffixProto =
 ProtoSeq2ArrayRef(Record.SuffixIndex, Record.SuffixLength);
 ArrayRef OverloadedSuffixProto = ProtoSeq2ArrayRef(
 Record.OverloadedSuffixIndex, Record.OverloadedSuffixSize);
+
+llvm::SmallVector ProtoSeq =
+RVVIntrinsic::computeBuiltinTypes(BasicProtoSeq, 

[PATCH] D126740: [RISCV][Clang] Refactor and rename rvv intrinsic related stuff. (NFC)

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbc4eef509b21: [RISCV][Clang] Refactor and rename rvv 
intrinsic related stuff. (NFC) (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126740?vs=433256=447630#toc

Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -479,12 +479,12 @@
 bool HasMasked = R->getValueAsBit("HasMasked");
 bool HasMaskedOffOperand = R->getValueAsBit("HasMaskedOffOperand");
 bool HasVL = R->getValueAsBit("HasVL");
-Record *MaskedPolicyRecord = R->getValueAsDef("MaskedPolicy");
-PolicyScheme MaskedPolicy =
-static_cast(MaskedPolicyRecord->getValueAsInt("Value"));
-Record *UnMaskedPolicyRecord = R->getValueAsDef("UnMaskedPolicy");
-PolicyScheme UnMaskedPolicy =
-static_cast(UnMaskedPolicyRecord->getValueAsInt("Value"));
+Record *MPSRecord = R->getValueAsDef("MaskedPolicyScheme");
+auto MaskedPolicyScheme =
+static_cast(MPSRecord->getValueAsInt("Value"));
+Record *UMPSRecord = R->getValueAsDef("UnMaskedPolicyScheme");
+auto UnMaskedPolicyScheme =
+static_cast(UMPSRecord->getValueAsInt("Value"));
 bool HasUnMaskedOverloaded = R->getValueAsBit("HasUnMaskedOverloaded");
 std::vector Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
@@ -500,50 +500,19 @@
 
 // Parse prototype and create a list of primitive type with transformers
 // (operand) in Prototype. Prototype[0] is output operand.
-SmallVector Prototype = parsePrototypes(Prototypes);
+SmallVector BasicPrototype =
+parsePrototypes(Prototypes);
 
 SmallVector SuffixDesc = parsePrototypes(SuffixProto);
 SmallVector OverloadedSuffixDesc =
 parsePrototypes(OverloadedSuffixProto);
 
 // Compute Builtin types
-SmallVector MaskedPrototype = Prototype;
-if (HasMasked) {
-  // If HasMaskedOffOperand, insert result type as first input operand.
-  if (HasMaskedOffOperand) {
-if (NF == 1) {
-  MaskedPrototype.insert(MaskedPrototype.begin() + 1, Prototype[0]);
-} else {
-  // Convert
-  // (void, op0 address, op1 address, ...)
-  // to
-  // (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
-  PrototypeDescriptor MaskoffType = Prototype[1];
-  MaskoffType.TM &= ~static_cast(TypeModifier::Pointer);
-  for (unsigned I = 0; I < NF; ++I)
-MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
-   MaskoffType);
-}
-  }
-  if (HasMaskedOffOperand && NF > 1) {
-// Convert
-// (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
-// to
-// (void, op0 address, op1 address, ..., mask, maskedoff0, maskedoff1,
-// ...)
-MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
-   PrototypeDescriptor::Mask);
-  } else {
-// If HasMasked, insert PrototypeDescriptor:Mask as first input operand.
-MaskedPrototype.insert(MaskedPrototype.begin() + 1,
-   PrototypeDescriptor::Mask);
-  }
-}
-// If HasVL, append PrototypeDescriptor:VL to last operand
-if (HasVL) {
-  Prototype.push_back(PrototypeDescriptor::VL);
-  MaskedPrototype.push_back(PrototypeDescriptor::VL);
-}
+auto Prototype = RVVIntrinsic::computeBuiltinTypes(
+BasicPrototype, /*IsMasked=*/false, /*HasMaskedOffOperand=*/false,
+HasVL, NF);
+auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
+BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF);
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -562,7 +531,7 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, IRName,
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
-UnMaskedPolicy, HasUnMaskedOverloaded, HasBuiltinAlias,
+UnMaskedPolicyScheme, HasUnMaskedOverloaded, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF));
 if (HasMasked) {
   // Create a masked intrinsic
@@ -571,7 +540,7 @@
   Out.push_back(std::make_unique(
   Name, SuffixStr, OverloadedName, 

[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:111
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");

I feel this logic is not clear for reader, maybe you should add comment to say 
why the return type -1 are load intrinsics?


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

@craig.topper @rogfer01 - do you have other comments?


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM. Other than that last comments.




Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:77
+  // Create compressed hsignature table from SemaRecords.
+  void init(const std::vector );
+

please use ArrayRef



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:110
+  void createRVVIntrinsics(std::vector> ,
+   std::vector *SemaRecords);
+  /// Create all intrinsics record and SemaSignatureTable from SemaRecords.

maybe SemaRecords could have default argument as nullptr.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:114
+SemaSignatureTable ,
+const std::vector );
+

please use ArrayRef



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:254
+  if (Signature.empty())
+return 0;
+

Does it mean empty Signature always at 0?
If yes,  maybe we could check the table from Index = 1 in below loop?


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[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

Could you please purpose this implement in rvv-intrinsc-doc first?
I think this feature need to have discussion because store to nullptr is UB but 
we are making it as defined behavior only for these intrinsics.
Personally I like they have consistent behavior and in document side we just 
make a note for users that vl should not be a null pointer.


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[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

IMO, if I'm an user, I would not expected intrinsic function will generate the 
condition code to impact the performance, maybe we need to raise a issue in 
rvv-intrinsic-doc.

maybe another way is adding a note in intrinsic document to address that the vl 
could not be a null pointer.

How about the segment load? Does it make sense to add null pointer checking for 
all argument v0~vN?


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[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

> Store to null will be changed to unreachable, so all instructions after vleff 
> intrinsic call will be deleted and it causes runtime errors. If destination 
> to store is null, we won't extract and store the new vl.



> Yes, but only for vleff instructions, since it has two outputs actually. And 
> this behavior is compatible with GCC. If necessary, I will propose it to 
> rvv-intrinsic-doc.

Compiling with -O0, I didn't see this behavior, so are you trying to make the 
optimized code behavior is compatible with GCC?

In addition, it seems this behavior also exist in scalar code, do we also need 
to make the scalar result is compatible with GCC?
ex.

  int foo (int j){
  int *k = nullptr;
  *k = 10;
  return 100;
  }

compiling with `-O3`, llvm generates empty function but gcc generates

  foo(int):
  sw  zero,0(zero)
  ebreak

https://godbolt.org/z/46vGrzs49

Please correct me if I misunderstand something, thanks.


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[PATCH] D125624: [gold] Remove an external dependency to GNU binutils' header file

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

IMO, maybe we could keep the DLLVM_BINUTILS_INCDIR option support but default 
is using the Plugin.h?


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[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D125323#3549794 , @pcwang-thead 
wrote:

> Is there an easy way to update tests? Or we need to add passthru operands 
> manually? I will appreciate it if you can tell me. :-)

use sed to do replacement.
ex.

  #!/bin/bash
  set -x
  
  for var in "$@"
  do
sed -i 's/declare {\([^,]\+\),[^,]\+} \(.*\)(\([0-9a-z*]\+\)/declare 
{\1,\1} \2(\1,\1, \3/g' $var
sed -i 's/declare {\([^,]\+\),[^,]\+,[^,]\+} \(.*\)(\([0-9a-z*]\+\)/declare 
{\1,\1,\1} \2(\1,\1,\1, \3/g' $var
sed -i 's/declare {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+} 
\(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1,\1} \2(\1,\1,\1,\1, \3/g' $var
sed -i 's/declare {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
\(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1,\1,\1} \2(\1,\1,\1,\1,\1, \3/g' $var
sed -i 's/declare {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
\(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1,\1,\1,\1} \2(\1,\1,\1,\1,\1,\1, \3/g' 
$var
sed -i 's/declare {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
\(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1,\1,\1,\1,\1} \2(\1,\1,\1,\1,\1,\1,\1, 
\3/g' $var
sed -i 's/declare 
{\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
\(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1,\1,\1,\1,\1,\1} 
\2(\1,\1,\1,\1,\1,\1,\1,\1, \3/g' $var
sed -i 's/call {\([^,]\+\),[^,]\+} \(.*\)(\([0-9a-z*]\+\)/call {\1,\1} 
\2(\1 undef, \1 undef, \3/g' $var
sed -i 's/call {\([^,]\+\),[^,]\+,[^,]\+} \(.*\)(\([0-9a-z*]\+\)/call 
{\1,\1,\1} \2(\1 undef, \1 undef, \1 undef, \3/g' $var
sed -i 's/call {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+} 
\(.*\)(\([0-9a-z*]\+\)/call {\1,\1,\1,\1} \2(\1 undef, \1 undef, \1 undef, \1 
undef, \3/g' $var
sed -i 's/call {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
\(.*\)(\([0-9a-z*]\+\)/call {\1,\1,\1,\1,\1} \2(\1 undef, \1 undef, \1 undef, 
\1 undef, \1 undef, \3/g' $var
sed -i 's/call {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
\(.*\)(\([0-9a-z*]\+\)/call {\1,\1,\1,\1,\1,\1} \2(\1 undef, \1 undef, \1 
undef, \1 undef, \1 undef, \1 undef, \3/g' $var
sed -i 's/call {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
\(.*\)(\([0-9a-z*]\+\)/call {\1,\1,\1,\1,\1,\1,\1} \2(\1 undef, \1 undef, \1 
undef, \1 undef, \1 undef, \1 undef, \1 undef, \3/g' $var
sed -i 's/call 
{\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
\(.*\)(\([0-9a-z*]\+\)/call {\1,\1,\1,\1,\1,\1,\1,\1} \2(\1 undef, \1 undef ,\1 
undef ,\1 undef, \1 undef ,\1 undef, \1 undef, \1 undef, \
  3/g' $var
  done


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125323/new/

https://reviews.llvm.org/D125323

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[PATCH] D126749: [RISCV][Clang] Support policy functions for Vector Mask Instructions.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126749

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsof_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsof_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsof.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsof_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsof_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsof_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsof.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsof_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsof_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsif_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsif_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsif.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsif_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsif_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsif_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsif.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsif_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsif_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsbf_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsbf_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsbf.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsbf_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsbf_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsbf_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsbf.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsbf_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsbf_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
@@ -204,7 +204,7 @@
 
 // CHECK-RV64-LABEL: @test_viota_m_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.viota.mask.nxv1i8.i64( 

[PATCH] D126748: [RISCV][Clang] Support policy functions for Vector Reduction Instructions.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126748

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -169,6 +169,9 @@
   if (RVVI->hasMaskedOffOperand() &&
   RVVI->getDefaultPolicy() == Policy::TAMA)
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
+  if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
+  RVVI->getDefaultPolicy() == Policy::TAMA)
+OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
 }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
@@ -759,3 +759,75 @@
 vuint64m1_t scalar, size_t vl) {
   return vwredsumu_vs_u32m8_u64m1_m(mask, dst, vector, scalar, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64( [[MERGE:%.*]],  [[VECTOR:%.*]],  [[SCALAR:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tu(vint64m1_t merge, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
+  return vwredsum_vs_i32mf2_i64m1_tu(merge, vector, scalar, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsumu.nxv1i64.nxv1i32.i64( [[MERGE:%.*]],  [[VECTOR:%.*]],  [[SCALAR:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_tu(vuint64m1_t merge, vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
+  return vwredsumu_vs_u32mf2_u64m1_tu(merge, vector, scalar, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_ta(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64( undef,  [[VECTOR:%.*]],  [[SCALAR:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint64m1_t test_vwredsum_vs_i32mf2_i64m1_ta(vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
+  return vwredsum_vs_i32mf2_i64m1_ta(vector, scalar, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_ta(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsumu.nxv1i64.nxv1i32.i64( undef,  [[VECTOR:%.*]],  [[SCALAR:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_ta(vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
+  return vwredsumu_vs_u32mf2_u64m1_ta(vector, scalar, 

[PATCH] D126746: [RISCV][Clang] Support policy functions for Vector Comparison Instructions.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126746

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
@@ -1699,3 +1699,75 @@
   vuint64m8_t op1, uint64_t op2, size_t vl) {
   return vmsne_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_i32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmsne_vv_i32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vx_i32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.i32.i64( undef,  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
+  return vmsne_vx_i32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_u32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
+  return vmsne_vv_u32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vx_u32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.i32.i64( undef,  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
+  return vmsne_vx_u32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_i32mf2_b64_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmsne_vv_i32mf2_b64_mu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vx_i32mf2_b64_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.i32.i64( [[MERGE:%.*]],  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t 

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126745

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
@@ -981,7 +981,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1f16.nxv1f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf4_t test_vmerge_vvm_f16mf4 (vbool64_t mask, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
+vfloat16mf4_t test_vmerge_vvm_f16mf4(vbool64_t mask, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
   return vmerge_vvm_f16mf4(mask, op1, op2, vl);
 }
 
@@ -990,7 +990,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv2f16.nxv2f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf2_t test_vmerge_vvm_f16mf2 (vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
+vfloat16mf2_t test_vmerge_vvm_f16mf2(vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
   return vmerge_vvm_f16mf2(mask, op1, op2, vl);
 }
 
@@ -999,7 +999,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv4f16.nxv4f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m1_t test_vmerge_vvm_f16m1 (vbool16_t mask, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+vfloat16m1_t test_vmerge_vvm_f16m1(vbool16_t mask, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
   return vmerge_vvm_f16m1(mask, op1, op2, vl);
 }
 
@@ -1008,7 +1008,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv8f16.nxv8f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m2_t test_vmerge_vvm_f16m2 (vbool8_t mask, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
+vfloat16m2_t test_vmerge_vvm_f16m2(vbool8_t mask, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
   return vmerge_vvm_f16m2(mask, op1, op2, vl);
 }
 
@@ -1017,7 +1017,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv16f16.nxv16f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m4_t test_vmerge_vvm_f16m4 (vbool4_t mask, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
+vfloat16m4_t test_vmerge_vvm_f16m4(vbool4_t mask, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
   return vmerge_vvm_f16m4(mask, op1, op2, vl);
 }
 
@@ -1026,6 +1026,96 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv32f16.nxv32f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m8_t test_vmerge_vvm_f16m8 (vbool2_t mask, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
+vfloat16m8_t test_vmerge_vvm_f16m8(vbool2_t mask, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
   return vmerge_vvm_f16m8(mask, op1, op2, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmerge_vvm_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1i32.nxv1i32.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint32mf2_t test_vmerge_vvm_i32mf2_tu(vbool64_t mask, vint32mf2_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmerge_vvm_i32mf2_tu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmerge_vxm_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1i32.i32.i64( [[MERGE:%.*]],  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint32mf2_t 

[PATCH] D126743: [RISCV][Clang] Add tests for all supported policy functions. (NFC)

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

In order to make the review easier, I split some tests from
https://reviews.llvm.org/D126742


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126743

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c
  

[PATCH] D126741: [RISCV][Clang] Refactor RISCVVEmitter. (NFC)

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Remove MaskedPrototype and add several fields in RVVIntrinsicRecord,
compute Prototype in runtime.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126741

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRVVLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -50,9 +50,6 @@
   // Prototype for this intrinsic.
   SmallVector Prototype;
 
-  // Prototype for masked intrinsic.
-  SmallVector MaskedPrototype;
-
   // Suffix of intrinsic name.
   SmallVector Suffix;
 
@@ -61,6 +58,10 @@
 
   // Number of field, large than 1 if it's segment load/store.
   unsigned NF;
+
+  bool HasMasked :1;
+  bool HasVL :1;
+  bool HasMaskedOffOperand :1;
 };
 
 class RVVEmitter {
@@ -478,11 +479,11 @@
 }
 
 SR.NF = NF;
+SR.HasMasked = HasMasked;
+SR.HasVL = HasVL;
+SR.HasMaskedOffOperand = HasMaskedOffOperand;
 
-SR.Prototype = std::move(Prototype);
-
-if (HasMasked)
-  SR.MaskedPrototype = std::move(MaskedPrototype);
+SR.Prototype = std::move(BasicPrototype);
 
 auto InitSuffixtype = [&](SmallVectorImpl ,
   StringRef Prototypes) {
@@ -566,7 +567,6 @@
 
   for (const auto  : SemaRecords) {
 InsertToSignatureSet(SemaRecord.Prototype);
-InsertToSignatureSet(SemaRecord.MaskedPrototype);
 InsertToSignatureSet(SemaRecord.Suffix);
 InsertToSignatureSet(SemaRecord.OverloadedSuffix);
   }
@@ -585,17 +585,18 @@
 Record.Name = SR.Name.c_str();
 Record.OverloadedName = SR.OverloadedName.c_str();
 Record.PrototypeIndex = GetSemaSignatureIndex(SR.Prototype);
-Record.MaskedPrototypeIndex = GetSemaSignatureIndex(SR.MaskedPrototype);
 Record.SuffixIndex = GetSemaSignatureIndex(SR.Suffix);
 Record.OverloadedSuffixIndex = GetSemaSignatureIndex(SR.OverloadedSuffix);
 Record.PrototypeLength = SR.Prototype.size();
-Record.MaskedPrototypeLength = SR.MaskedPrototype.size();
 Record.SuffixLength = SR.Suffix.size();
 Record.OverloadedSuffixSize = SR.OverloadedSuffix.size();
 Record.RequiredExtension = SR.RequiredExtension;
 Record.TypeRangeMask = SR.TypeRangeMask;
 Record.Log2LMULMask = SR.Log2LMULMask;
 Record.NF = SR.NF;
+Record.HasMasked = SR.HasMasked;
+Record.HasVL = SR.HasVL;
+Record.HasMaskedOffOperand = SR.HasMaskedOffOperand;
 Out.push_back(Record);
   }
 }
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -983,17 +983,18 @@
   else
 OS << "\"" << Record.OverloadedName << "\",";
   OS << Record.PrototypeIndex << ",";
-  OS << Record.MaskedPrototypeIndex << ",";
   OS << Record.SuffixIndex << ",";
   OS << Record.OverloadedSuffixIndex << ",";
   OS << (int)Record.PrototypeLength << ",";
-  OS << (int)Record.MaskedPrototypeLength << ",";
   OS << (int)Record.SuffixLength << ",";
   OS << (int)Record.OverloadedSuffixSize << ",";
   OS << (int)Record.RequiredExtension << ",";
   OS << (int)Record.TypeRangeMask << ",";
   OS << (int)Record.Log2LMULMask << ",";
   OS << (int)Record.NF << ",";
+  OS << (int)Record.HasMasked << ",";
+  OS << (int)Record.HasVL << ",";
+  OS << (int)Record.HasMaskedOffOperand << ",";
   OS << "},\n";
   return OS;
 }
Index: clang/lib/Sema/SemaRVVLookup.cpp
===
--- clang/lib/Sema/SemaRVVLookup.cpp
+++ clang/lib/Sema/SemaRVVLookup.cpp
@@ -174,10 +174,17 @@
   for (auto  : RVVIntrinsicRecords) {
 // Create Intrinsics for each type and LMUL.
 BasicType BaseType = BasicType::Unknown;
-auto ProtoSeq =
+auto BasicProtoSeq =
 ProtoSeq2ArrayRef(Record.PrototypeIndex, Record.PrototypeLength);
-auto ProtoMaskSeq = ProtoSeq2ArrayRef(Record.MaskedPrototypeIndex,
-  Record.MaskedPrototypeLength);
+
+auto ProtoSeq = RVVIntrinsic::computeBuiltinTypes(
+BasicProtoSeq, /*IsMasked=*/false,
+/*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF);
+
+auto ProtoMaskSeq = 

[PATCH] D126740: [RISCV][Clang] Refactor and rename rvv intrinsic related stuff. (NFC)

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

This changed is based on https://reviews.llvm.org/D111617


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126740

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -375,12 +375,12 @@
 bool HasMasked = R->getValueAsBit("HasMasked");
 bool HasMaskedOffOperand = R->getValueAsBit("HasMaskedOffOperand");
 bool HasVL = R->getValueAsBit("HasVL");
-Record *MaskedPolicyRecord = R->getValueAsDef("MaskedPolicy");
-PolicyScheme MaskedPolicy =
-static_cast(MaskedPolicyRecord->getValueAsInt("Value"));
-Record *UnMaskedPolicyRecord = R->getValueAsDef("UnMaskedPolicy");
-PolicyScheme UnMaskedPolicy =
-static_cast(UnMaskedPolicyRecord->getValueAsInt("Value"));
+Record *MPSRecord = R->getValueAsDef("MaskedPolicyScheme");
+auto MaskedPolicyScheme =
+static_cast(MPSRecord->getValueAsInt("Value"));
+Record *UMPSRecord = R->getValueAsDef("UnMaskedPolicyScheme");
+auto UnMaskedPolicyScheme =
+static_cast(UMPSRecord->getValueAsInt("Value"));
 bool HasUnMaskedOverloaded = R->getValueAsBit("HasUnMaskedOverloaded");
 std::vector Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
@@ -396,50 +396,19 @@
 
 // Parse prototype and create a list of primitive type with transformers
 // (operand) in Prototype. Prototype[0] is output operand.
-SmallVector Prototype = parsePrototypes(Prototypes);
+SmallVector BasicPrototype =
+parsePrototypes(Prototypes);
 
 SmallVector SuffixDesc = parsePrototypes(SuffixProto);
 SmallVector OverloadedSuffixDesc =
 parsePrototypes(OverloadedSuffixProto);
 
 // Compute Builtin types
-SmallVector MaskedPrototype = Prototype;
-if (HasMasked) {
-  // If HasMaskedOffOperand, insert result type as first input operand.
-  if (HasMaskedOffOperand) {
-if (NF == 1) {
-  MaskedPrototype.insert(MaskedPrototype.begin() + 1, Prototype[0]);
-} else {
-  // Convert
-  // (void, op0 address, op1 address, ...)
-  // to
-  // (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
-  PrototypeDescriptor MaskoffType = Prototype[1];
-  MaskoffType.TM &= ~static_cast(TypeModifier::Pointer);
-  for (unsigned I = 0; I < NF; ++I)
-MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
-   MaskoffType);
-}
-  }
-  if (HasMaskedOffOperand && NF > 1) {
-// Convert
-// (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
-// to
-// (void, op0 address, op1 address, ..., mask, maskedoff0, maskedoff1,
-// ...)
-MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
-   PrototypeDescriptor::Mask);
-  } else {
-// If HasMasked, insert PrototypeDescriptor:Mask as first input operand.
-MaskedPrototype.insert(MaskedPrototype.begin() + 1,
-   PrototypeDescriptor::Mask);
-  }
-}
-// If HasVL, append PrototypeDescriptor:VL to last operand
-if (HasVL) {
-  Prototype.push_back(PrototypeDescriptor::VL);
-  MaskedPrototype.push_back(PrototypeDescriptor::VL);
-}
+auto Prototype = RVVIntrinsic::computeBuiltinTypes(
+BasicPrototype, /*IsMasked=*/false, /*HasMaskedOffOperand=*/false,
+HasVL, NF);
+auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
+BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF);
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -458,7 +427,7 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, IRName,
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
-UnMaskedPolicy, HasUnMaskedOverloaded, HasBuiltinAlias,
+UnMaskedPolicyScheme, HasUnMaskedOverloaded, HasBuiltinAlias,
 

[PATCH] D126634: [RISCV][NFC] Rename variables in rvv intrinsics related files.

[Zakk Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG79e3d57f5228: [RISCV][NFC] Rename variables in rvv 
intrinsics related files. (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126634/new/

https://reviews.llvm.org/D126634

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -155,10 +155,10 @@
   OS << ");\n";
 }
 
-void emitMangledFuncDef(const RVVIntrinsic , raw_ostream ) {
+void emitOverloadedFuncDef(const RVVIntrinsic , raw_ostream ) {
   OS << "__attribute__((__clang_builtin_alias__(";
   OS << "__builtin_rvv_" << RVVI.getBuiltinName() << ")))\n";
-  OS << RVVI.getOutputType()->getTypeStr() << " " << RVVI.getMangledName()
+  OS << RVVI.getOutputType()->getTypeStr() << " " << RVVI.getOverloadedName()
  << "(";
   // Emit function arguments
   const RVVTypes  = RVVI.getInputTypes();
@@ -289,7 +289,7 @@
 if (!Inst.isMasked() && !Inst.hasUnMaskedOverloaded())
   return;
 OS << "__rvv_aio ";
-emitMangledFuncDef(Inst, OS);
+emitOverloadedFuncDef(Inst, OS);
   });
 
   OS << "#undef __rvv_aio\n";
@@ -387,8 +387,8 @@
   for (auto *R : RV) {
 StringRef Name = R->getValueAsString("Name");
 StringRef SuffixProto = R->getValueAsString("Suffix");
-StringRef OverloadedName = R->getValueAsString("MangledName");
-StringRef OverloadedSuffixProto = R->getValueAsString("MangledSuffix");
+StringRef OverloadedName = R->getValueAsString("OverloadedName");
+StringRef OverloadedSuffixProto = R->getValueAsString("OverloadedSuffix");
 StringRef Prototypes = R->getValueAsString("Prototype");
 StringRef TypeRange = R->getValueAsString("TypeRange");
 bool HasMasked = R->getValueAsBit("HasMasked");
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -791,13 +791,13 @@
 
 Optional
 RVVType::computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
-  ArrayRef PrototypeSeq) {
+  ArrayRef Prototype) {
   // LMUL x NF must be less than or equal to 8.
   if ((Log2LMUL >= 1) && (1 << Log2LMUL) * NF > 8)
 return llvm::None;
 
   RVVTypes Types;
-  for (const PrototypeDescriptor  : PrototypeSeq) {
+  for (const PrototypeDescriptor  : Prototype) {
 auto T = computeType(BT, Log2LMUL, Proto);
 if (!T.hasValue())
   return llvm::None;
@@ -847,8 +847,8 @@
 // RVVIntrinsic implementation
 //===--===//
 RVVIntrinsic::RVVIntrinsic(
-StringRef NewName, StringRef Suffix, StringRef NewMangledName,
-StringRef MangledSuffix, StringRef IRName, bool IsMasked,
+StringRef NewName, StringRef Suffix, StringRef NewOverloadedName,
+StringRef OverloadedSuffix, StringRef IRName, bool IsMasked,
 bool HasMaskedOffOperand, bool HasVL, PolicyScheme Scheme,
 bool HasUnMaskedOverloaded, bool HasBuiltinAlias, StringRef ManualCodegen,
 const RVVTypes , const std::vector ,
@@ -858,17 +858,17 @@
   HasBuiltinAlias(HasBuiltinAlias), ManualCodegen(ManualCodegen.str()),
   NF(NF) {
 
-  // Init BuiltinName, Name and MangledName
+  // Init BuiltinName, Name and OverloadedName
   BuiltinName = NewName.str();
   Name = BuiltinName;
-  if (NewMangledName.empty())
-MangledName = NewName.split("_").first.str();
+  if (NewOverloadedName.empty())
+OverloadedName = NewName.split("_").first.str();
   else
-MangledName = NewMangledName.str();
+OverloadedName = NewOverloadedName.str();
   if (!Suffix.empty())
 Name += "_" + Suffix.str();
-  if (!MangledSuffix.empty())
-MangledName += "_" + MangledSuffix.str();
+  if (!OverloadedSuffix.empty())
+OverloadedName += "_" + OverloadedSuffix.str();
   if (IsMasked) {
 BuiltinName += "_m";
 Name += "_m";
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -256,7 +256,7 @@
   /// have illegal RVVType.
   static llvm::Optional
   computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
-   llvm::ArrayRef PrototypeSeq);
+   llvm::ArrayRef Prototype);
   static llvm::Optional computeType(BasicType BT, int Log2LMUL,
 PrototypeDescriptor Proto);
 };
@@ -287,7 +287,7 @@
 private:
   std::string BuiltinName; // Builtin name
   std::string Name;  

[PATCH] D126634: [RISCV][NFC] Rename variables in rvv intrinsics related files.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added a reviewer: kito-cheng.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

This patch does the same thing as D125886  
did.

- Use `Overloaded` rather than `Mangled`.
- Use `Prototype` or `Desc` rather than `Seq`, it's not just a string

sequence.


Repository:
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https://reviews.llvm.org/D126634

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -155,10 +155,10 @@
   OS << ");\n";
 }
 
-void emitMangledFuncDef(const RVVIntrinsic , raw_ostream ) {
+void emitOverloadedFuncDef(const RVVIntrinsic , raw_ostream ) {
   OS << "__attribute__((__clang_builtin_alias__(";
   OS << "__builtin_rvv_" << RVVI.getBuiltinName() << ")))\n";
-  OS << RVVI.getOutputType()->getTypeStr() << " " << RVVI.getMangledName()
+  OS << RVVI.getOutputType()->getTypeStr() << " " << RVVI.getOverloadedName()
  << "(";
   // Emit function arguments
   const RVVTypes  = RVVI.getInputTypes();
@@ -289,7 +289,7 @@
 if (!Inst.isMasked() && !Inst.hasUnMaskedOverloaded())
   return;
 OS << "__rvv_aio ";
-emitMangledFuncDef(Inst, OS);
+emitOverloadedFuncDef(Inst, OS);
   });
 
   OS << "#undef __rvv_aio\n";
@@ -387,8 +387,8 @@
   for (auto *R : RV) {
 StringRef Name = R->getValueAsString("Name");
 StringRef SuffixProto = R->getValueAsString("Suffix");
-StringRef OverloadedName = R->getValueAsString("MangledName");
-StringRef OverloadedSuffixProto = R->getValueAsString("MangledSuffix");
+StringRef OverloadedName = R->getValueAsString("OverloadedName");
+StringRef OverloadedSuffixProto = R->getValueAsString("OverloadedSuffix");
 StringRef Prototypes = R->getValueAsString("Prototype");
 StringRef TypeRange = R->getValueAsString("TypeRange");
 bool HasMasked = R->getValueAsBit("HasMasked");
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -791,13 +791,13 @@
 
 Optional
 RVVType::computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
-  ArrayRef PrototypeSeq) {
+  ArrayRef Prototype) {
   // LMUL x NF must be less than or equal to 8.
   if ((Log2LMUL >= 1) && (1 << Log2LMUL) * NF > 8)
 return llvm::None;
 
   RVVTypes Types;
-  for (const PrototypeDescriptor  : PrototypeSeq) {
+  for (const PrototypeDescriptor  : Prototype) {
 auto T = computeType(BT, Log2LMUL, Proto);
 if (!T.hasValue())
   return llvm::None;
@@ -847,8 +847,8 @@
 // RVVIntrinsic implementation
 //===--===//
 RVVIntrinsic::RVVIntrinsic(
-StringRef NewName, StringRef Suffix, StringRef NewMangledName,
-StringRef MangledSuffix, StringRef IRName, bool IsMasked,
+StringRef NewName, StringRef Suffix, StringRef NewOverloadedName,
+StringRef OverloadedSuffix, StringRef IRName, bool IsMasked,
 bool HasMaskedOffOperand, bool HasVL, PolicyScheme Scheme,
 bool HasUnMaskedOverloaded, bool HasBuiltinAlias, StringRef ManualCodegen,
 const RVVTypes , const std::vector ,
@@ -858,17 +858,17 @@
   HasBuiltinAlias(HasBuiltinAlias), ManualCodegen(ManualCodegen.str()),
   NF(NF) {
 
-  // Init BuiltinName, Name and MangledName
+  // Init BuiltinName, Name and OverloadedName
   BuiltinName = NewName.str();
   Name = BuiltinName;
-  if (NewMangledName.empty())
-MangledName = NewName.split("_").first.str();
+  if (NewOverloadedName.empty())
+OverloadedName = NewName.split("_").first.str();
   else
-MangledName = NewMangledName.str();
+OverloadedName = NewOverloadedName.str();
   if (!Suffix.empty())
 Name += "_" + Suffix.str();
-  if (!MangledSuffix.empty())
-MangledName += "_" + MangledSuffix.str();
+  if (!OverloadedSuffix.empty())
+OverloadedName += "_" + OverloadedSuffix.str();
   if (IsMasked) {
 BuiltinName += "_m";
 Name += "_m";
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ 

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: clang/lib/Sema/SemaRVVLookup.cpp:175
+  for (auto  : RVVIntrinsicRecords) {
+// Create Intrinsics for each type and LMUL.
+BasicType BaseType = BasicType::Unknown;

Those code logic need to sync with createRVVIntrinsics, maybe we could add more 
comment address that.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:91
 private:
   /// Create all intrinsics and add them to \p Out
   void createRVVIntrinsics(std::vector> );

and also init SemaRecords?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:93
   void createRVVIntrinsics(std::vector> );
+  /// Create all intrinsics record from RVVIntrinsics.
+  void createRVVIntrinsicRecord(std::vector );

I think it should be "Create all intrinsics record and SemaSignatureTable from 
SemaRecords"?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:99
 
-  /// Emit Acrh predecessor definitions and body, assume the element of Defs 
are
-  /// sorted by extension.
-  void emitArchMacroAndBody(
-  std::vector> , raw_ostream ,
-  std::function);
-
-  // Emit the architecture preprocessor definitions. Return true when emits
-  // non-empty string.
-  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
-   raw_ostream );
+  /// Construct a compressed signature table used for createSema.
+  void ConstructSemaSignatureTable();

/// Construct a compressed signature table from SemaRecords which is used for 
createSema.
maybe better.




Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:103
+  unsigned
+  GetSemaSignatureIndex(const SmallVector );
 };

This is ambiguous of naming and comment because it also insert signature into 
SemaSignatureTable if not found in the table.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:597
+  };
+
+  for (const auto  : SemaRecords) {

maybe we need an assert to check SemaRecords is not empty.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:637
+  std::vector RVVIntrinsicRecords;
+  createRVVIntrinsics(Defs);
+

we only need SemaRecords initialization part of createRVVIntrinsics, right?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:639
+
+  createRVVIntrinsicRecord(RVVIntrinsicRecords);
+

`createRVVIntrinsicRecord also init SemaSignatureTable implicitly.`


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[PATCH] D126042: [RISCV][NFC] Remove `*=` operator for LMULType

[Zakk Chen via Phabricator via cfe-commits]

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM, thanks.


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[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D125765#3526835 , @pcwang-thead 
wrote:

> In D125765#3524456 , @khchen wrote:
>
>> I think we have no consensus in 
>> https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/18#issuecomment-817890161,
>>  and most people disagree the current naming,
>> maybe we need to have more followup discussion before landing this patch.
>
> Thanks for your reminding of previous discussion!
> Should we put this in next sync-up discussion agenda and settle it down? 
> There are already some large code bases based GCC implementation, we should 
> make it stable before it becomes too hard to change.

I think so. But I think maybe we need to raise an issue somewhere (maybe 
riscv-c-api-doc) to gather opinions from community first. (see below)

>> For example, maybe `_Float16` should be supported when enable zvh, not zvfh?
>
> You mean `zfh`? `float16_t` is only used in RVV intrinsics, so I think it is 
> OK to me. And it is the same as generated type aliases in riscv_vector.h(at 
> about line 130):

Yes, sorry for my typo.

I think maybe we need to have more comprehensive consideration about define 
floating type aliases in RISC-V world.
For example, before RISC-V support half floating type, we had posted 
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/172 to update the 
spec for half floating-point type.

or like https://github.com/riscv-non-isa/riscv-c-api-doc/pull/25, it's trying 
to define a unified naming rules for all intrinsics.
so I think maybe we also need to have RFC in riscv-c-api-doc to define the 
convention for floating type aliases.

>   #if defined(__riscv_zvfh)
>   typedef __rvv_float16mf4_t vfloat16mf4_t;
>   typedef __rvv_float16mf2_t vfloat16mf2_t;
>   typedef __rvv_float16m1_t vfloat16m1_t;
>   typedef __rvv_float16m2_t vfloat16m2_t;
>   typedef __rvv_float16m4_t vfloat16m4_t;
>   typedef __rvv_float16m8_t vfloat16m8_t;
>   #endif




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[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

please move those tests to `test/CodeGen/RISCV/rvv-intrinsics` and rename them 
without `rvv-` prefix.




Comment at: clang/include/clang/Basic/riscv_vector.td:1511
+__extension__ extern __inline
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+unsigned long vread_csr(enum RVV_CSR csr) {

pcwang-thead wrote:
> craig.topper wrote:
> > Do we need __gnu_inline__ and __artificial__? The only intrinsics headers 
> > that have them in clang are in ppc_wrappers. X86 uses 
> > `__attribute__((__always_inline__, __nodebug__`
> I just made it the same as GCC.
Why do you think making it same as GCC is better than same as other targets in 
clang?




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[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

I think we have no consensus in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/18#issuecomment-817890161,
 and most people disagree the current naming,
maybe we need to have more followup discussion before landing this patch.

For example, maybe `_Float16` should be supported when enable zvh, not zvfh?


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[PATCH] D125886: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp

[Zakk Chen via Phabricator via cfe-commits]

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

Do we need to have some tests in `clang/test/PCH/` for new #pragma?




Comment at: clang/lib/Sema/SemaLookup.cpp:932
+  if (DeclareRVVBuiltins) {
+if (GetRVVBuiltinInfo(*this, R, II, PP)) {
+  return true;

Don’t Use Braces on Simple Single-Statement Bodies.



Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:884
 RVVIntrinsic::getSuffixStr(BasicType Type, int Log2LMUL,
-   const llvm::SmallVector ) 
{
+   const llvm::ArrayRef ) {
   SmallVector SuffixStrs;

maybe this changed should be in another NFC patch.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:372
 StringRef Name = R->getValueAsString("Name");
-StringRef SuffixProto = R->getValueAsString("Suffix");
+StringRef Suffix = R->getValueAsString("Suffix");
 StringRef MangledName = R->getValueAsString("MangledName");

maybe all renaming stuffs should be in another NFC patch.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:480
+// They are handled by riscv_vector.h
+if (Name == "vsetvli" || Name == "vsetvlimax")
+  continue;

I feel little tricky to checking the name here. what do you mean they are 
handled by riscv_vector.h?
do you mean they have `vsetvl_macro:RVVHeader`?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:611
+  for (const auto  : SemaRecords) {
+// Output *MUST* sync with RVVIntrinsicRecord in SemaRVVLookup.cpp.
+OS << "{"

I'm thinking is it possible to have an unittest or test to make sure we won't 
screw up in the future implementation?
Is it possible to have unittest to test implement really have `sync` correctly?
Is it easy to debug the mismatch problem during implementation without any new 
test added?
We will add a new implementation (really cool speed up and meaningful 
improvement), but unfortunately we don't have any tests, that make me a little 
hesitating...

What do you think?


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[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

[Zakk Chen via Phabricator via cfe-commits]

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

Thanks Kito. This all LGTM except some warnings need to fix.




Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:384
+return PD;
   // Handle primitive type transformer
+  auto PType = PrototypeDescriptorStr.back();

so we also need to update this comment as base type transformer?



Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:718
+  default:
+llvm_unreachable("Illegal vector type modifier!");
+  }

Don’t use default labels in fully covered switches over enumerations
please remove default in `RISCVVIntrinsicUtils.cpp:624`, 
`RISCVVIntrinsicUtils.cpp:717` and `RISCVVIntrinsicUtils.cpp:793`.



Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:962
+  }
+  return std::move(PrototypeDescriptors);
+}

```
clang/lib/Support/RISCVVIntrinsicUtils.cpp:962:10: warning: moving a local 
object in a return statement prevents copy elision [-Wpessimizing-move]
  return std::move(PrototypeDescriptors);
 ^
clang/lib/Support/RISCVVIntrinsicUtils.cpp:962:10: note: remove std::move call 
here
  return std::move(PrototypeDescriptors);
```


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[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7dfc56c10746: [RISCV] Add the passthru operand for RVV 
unmasked segment load IR intrinsics. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D125323?vs=428674=429171#toc

Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv32-readvl.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv64-readvl.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

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[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 428674.
khchen added a comment.

address Craig's comments, thanks!!


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

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[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.
Herald added a subscriber: shiva0217.

Thanks for refactoring!




Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:55
+// basic vector type, used to compute type info of arguments.
+enum class PrimitiveType : uint8_t {
+  Invalid,

I think vector is not a primitive type in common sense, is it?
why Widening2XVector, Widening4XVector, Widening8XVector and MaskVector is not 
part of VectorTypeModifier?

Sorry, I'm confused and maybe forget something.



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:85
+// TypeProfile is used to compute type info of arguments or return value.
+struct TypeProfile {
+  constexpr TypeProfile() = default;

I think we need to update the comment in riscv_vector.td to sync the word 
"TypeProfile", I feel the new word `TypeProfile` is similar to `modifier` or 
`prototype`, is it?

```
The C/C++ prototype of the builtin is defined by the Prototype attribute.
Prototype is a non-empty sequence of type transformers, the first of which
is the return type of the builtin and the rest are the parameters of the
builtin, in order. For instance if Prototype is "wvv" and TypeRange is "si"
a first builtin will have type
```

we call it  `modifier` or `prototype` is because those words are coming from 
clang intrinsic definition and other target.

https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/Builtins.def#L52
https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/arm_sve.td#L58

personally I think consistent naming maybe better than creating a new word, 
what do you think?


BTW, I think having this new class is really good idea for refactoring!



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:90
+  : PT(static_cast(PT)), TM(static_cast(TM)) {}
+  constexpr TypeProfile(uint8_t PT, uint8_t VTM, uint8_t TM)
+  : PT(PT), VTM(VTM), TM(TM) {}

If we allow parameter could `uint8_t`, why other constructors not follow the 
same rule?



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:97
+
+  std::string IndexStr() const {
+return std::to_string(PT) + "_" + std::to_string(VTM) + "_" +

What's purpose of this function, translate TypeProfile to the Proto string?



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:249
+  /// and LMUL with type transformers). It also record result of type in legal
+  /// or illegal set to avoid compute the  same config again. The result maybe
+  /// have illegal RVVType.

additional space



Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:767
+
+void RVVType::applyFixedLog2LMUL(int Log2LMUL, bool LargerThan) {
+  if (LargerThan) {

In riscv_vector.td is said smaller or larger, I feel little confusing here when 
it call LagerThan. maybe have more comment like `The result of modified type 
should be smaller than giving type` ?


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[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, 
arichardson, qcolombet, MatzeB.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125323

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

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[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

[Zakk Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6c10014f1de6: [RISCV][Clang] add more tests for clang 
driver. (NFC) (authored by khchen).

Repository:
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Files:
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -412,6 +412,26 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG 
%s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS 
%s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version 
number
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p1 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS 
%s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izbt0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental 
extension
+// RV32-EXPERIMENTAL-BADVERS: 'zbt'(this compiler supports 0.93)
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p93 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zbt"
+
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb -### %s \
@@ -494,3 +514,48 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izk1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZK %s
 // RV32-ZK: "-target-feature" "+zk"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfh1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFH %s
+// CHECK-RV32-ZFH: "-target-feature" "+zfh"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfhmin1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFHMIN %s
+// CHECK-RV32-ZFHMIN: "-target-feature" "+zfhmin"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x0p1 -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32X-BADVERS %s
+// RV32-ZVE32X-BADVERS: error: invalid arch name 'rv32izve32x0p1'
+// RV32-ZVE32X-BADVERS: unsupported version number 0.1 for extension 'zve32x'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32X-GOODVERS %s
+// RV32-ZVE32X-GOODVERS: "-target-feature" "+zve32x"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-REQUIRE-F %s
+// RV32-ZVE32F-REQUIRE-F: error: invalid arch name 'rv32izve32f', zve32f 
requires f or zfinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve32f -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-GOOD %s
+// RV32-ZVE32F-GOOD: "-target-feature" "+zve32f"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64x -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64X %s
+// RV32-ZVE64X: "-target-feature" "+zve64x"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64f -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64F-REQUIRE-F %s
+// RV32-ZVE64F-REQUIRE-F: error: invalid arch name 'rv32izve64f', zve32f 
requires f or zfinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64f -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64F-GOOD %s
+// RV32-ZVE64F-GOOD: "-target-feature" "+zve64f"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64d -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64D-REQUIRE-D %s
+// RV32-ZVE64D-REQUIRE-D: error: invalid arch name 'rv32ifzve64d', zve64d 
requires d or zdinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifdzve64d -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64D-GOOD %s
+// RV32-ZVE64D-GOOD: "-target-feature" "+zve64d"


Index: clang/test/Driver/riscv-arch.c
===
--- 

[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 426587.
khchen added a comment.

Add zve64* tests.


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Files:
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -412,6 +412,26 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG 
%s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS 
%s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version 
number
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p1 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS 
%s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izbt0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental 
extension
+// RV32-EXPERIMENTAL-BADVERS: 'zbt'(this compiler supports 0.93)
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p93 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zbt"
+
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb -### %s \
@@ -494,3 +514,48 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izk1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZK %s
 // RV32-ZK: "-target-feature" "+zk"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfh1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFH %s
+// CHECK-RV32-ZFH: "-target-feature" "+zfh"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfhmin1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFHMIN %s
+// CHECK-RV32-ZFHMIN: "-target-feature" "+zfhmin"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x0p1 -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32X-BADVERS %s
+// RV32-ZVE32X-BADVERS: error: invalid arch name 'rv32izve32x0p1'
+// RV32-ZVE32X-BADVERS: unsupported version number 0.1 for extension 'zve32x'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32X-GOODVERS %s
+// RV32-ZVE32X-GOODVERS: "-target-feature" "+zve32x"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-REQUIRE-F %s
+// RV32-ZVE32F-REQUIRE-F: error: invalid arch name 'rv32izve32f', zve32f 
requires f or zfinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve32f -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-GOOD %s
+// RV32-ZVE32F-GOOD: "-target-feature" "+zve32f"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64x -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64X %s
+// RV32-ZVE64X: "-target-feature" "+zve64x"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64f -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64F-REQUIRE-F %s
+// RV32-ZVE64F-REQUIRE-F: error: invalid arch name 'rv32izve64f', zve32f 
requires f or zfinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64f -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64F-GOOD %s
+// RV32-ZVE64F-GOOD: "-target-feature" "+zve64f"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64d -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64D-REQUIRE-D %s
+// RV32-ZVE64D-REQUIRE-D: error: invalid arch name 'rv32ifzve64d', zve64d 
requires d or zdinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifdzve64d -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64D-GOOD %s
+// RV32-ZVE64D-GOOD: "-target-feature" "+zve64d"


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -412,6 +412,26 @@
 // 

[PATCH] D124510: [RISCV] Precommit test for D124509

[Zakk Chen via Phabricator via cfe-commits]

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks!


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[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, asb, luismarques.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD.
Herald added a project: clang.

Test experimental arch, Zfh, Zfmin and Zve arch.


Repository:
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https://reviews.llvm.org/D124611

Files:
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -412,6 +412,26 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG 
%s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS 
%s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version 
number
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p1 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS 
%s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izbt0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental 
extension
+// RV32-EXPERIMENTAL-BADVERS: 'zbt'(this compiler supports 0.93)
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p93 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zbt"
+
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb -### %s \
@@ -494,3 +514,28 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izk1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZK %s
 // RV32-ZK: "-target-feature" "+zk"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfh1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFH %s
+// CHECK-RV32-ZFH: "-target-feature" "+zfh"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfhmin1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFHMIN %s
+// CHECK-RV32-ZFHMIN: "-target-feature" "+zfhmin"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x0p1 -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE-BADVERS %s
+// RV32-ZVE-BADVERS: error: invalid arch name 'rv32izve32x0p1'
+// RV32-ZVE-BADVERS: unsupported version number 0.1 for extension 'zve32x'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE-GOODVERS %s
+// RV32-ZVE-GOODVERS: "-target-feature" "+zve32x"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-REQUIRE-F %s
+// RV32-ZVE32F-REQUIRE-F: error: invalid arch name 'rv32izve32f', zve32f 
requires f or zfinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve32f -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-GOOD %s
+// RV32-ZVE32F-GOOD: "-target-feature" "+zve32f"


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -412,6 +412,26 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izbt'
+// 

[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

It's seem like all targets need to return `false` in 
`useFP16ConversionIntrinsics` for correctness of `int16` -> `__fp16` conversion?


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[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGffe03ff75c26: [RISCV] Fix incorrect policy implement for 
unmasked vslidedown and vslideup. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D124186?vs=424517=424934#toc

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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll

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[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 424517.
khchen edited the summary of this revision.
khchen added a comment.

update clang tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll

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[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D124186#3465136 , @craig.topper 
wrote:

> The intrinsic interface doesn't care about 0 give user control of vstart. Nearly every instruction is undisturbed for 
> 0
> But having said that it probably makes sense to keep the vslideup/down 
> interface the same.



In D124186#3465136 , @craig.topper 
wrote:

> The intrinsic interface doesn't care about 0 give user control of vstart. Nearly every instruction is undisturbed for 
> 0
> But having said that it probably makes sense to keep the vslideup/down 
> interface the same.

Yes I know, but I didn't clarify that in comment, thanks for your advice.


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[PATCH] D124062: [RISCV][Clang][NFC] Update vid intrinsic tests.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D124062#3461069 , @frasercrmck 
wrote:

> Were they perhaps passing because `i64 [[VL:%.*]]` was matching the `, i64 0` 
> too? Seems like a flaw in the checks generated by the script, but I can see 
> how the majority of the time the brevity is nice.

Yes, agree.

Thanks for reviewing.


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[PATCH] D124062: [RISCV][Clang][NFC] Update vid intrinsic tests.

[Zakk Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGbd0d126302a8: [RISCV][Clang][NFC] Update vid intrinsic 
tests. (authored by khchen).

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Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
@@ -160,7 +160,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf8_t test_vid_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
@@ -170,7 +170,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf4_t test_vid_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
@@ -180,7 +180,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf2_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv4i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv4i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf2_t test_vid_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
@@ -190,7 +190,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m1_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv8i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv8i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m1_t test_vid_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, size_t vl) {
@@ -199,7 +199,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m2_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv16i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv16i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m2_t test_vid_v_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, size_t vl) {
@@ -208,7 +208,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv32i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv32i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m4_t test_vid_v_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, size_t vl) {
@@ -217,7 +217,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv64i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv64i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m8_t test_vid_v_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, size_t vl) {
@@ -226,7 +226,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u16mf4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint16mf4_t test_vid_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
@@ -236,7 +236,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u16mf2_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint16mf2_t test_vid_v_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff,
@@ -246,7 +246,7 @@
 
 // CHECK-RV64-LABEL: 

[PATCH] D124062: [RISCV][Clang][NFC] Update vid intrinsic tests.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Re-run the update_cc_test_checks.py to update expected result.
I'm not sure why those tests are passed before.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124062

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
@@ -160,7 +160,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf8_t test_vid_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
@@ -170,7 +170,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf4_t test_vid_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
@@ -180,7 +180,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf2_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv4i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv4i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf2_t test_vid_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
@@ -190,7 +190,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m1_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv8i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv8i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m1_t test_vid_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, size_t vl) {
@@ -199,7 +199,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m2_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv16i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv16i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m2_t test_vid_v_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, size_t vl) {
@@ -208,7 +208,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv32i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv32i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m4_t test_vid_v_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, size_t vl) {
@@ -217,7 +217,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv64i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv64i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m8_t test_vid_v_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, size_t vl) {
@@ -226,7 +226,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u16mf4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint16mf4_t test_vid_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
@@ -236,7 +236,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u16mf2_m(
 // 

[PATCH] D122455: Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"

[Zakk Chen via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG10b2760da0fd: Revert [RISCV] Add policy operand for 
masked compare and vmsbf/vmsif/vmsof IR (authored by khchen).
Herald added a subscriber: sunshaoce.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122455/new/

https://reviews.llvm.org/D122455

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof.ll

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[PATCH] D122455: Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: s, VincentWu, luke957, StephenFan, vkmr, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

This reverts commit 10fd2822b77e12215b4ea82fc6d0a052961eb9d9 
.

I have a better implementation for those operations without the
additional policy operand.
masked compare and vmsbf/vmsif/vmsof are always tail agnostic so we could
assume undef maskedoff is mask agnostic.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122455

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof.ll

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[PATCH] D120870: [RISCV][NFC] Refine and refactor RISCVVEmitter and riscv_vector.td.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG23d60ce164db: [RISCV][NFC] Refine and refactor RISCVVEmitter 
and riscv_vector.td. (authored by khchen).
Herald added subscribers: s, StephenFan, arichardson.

Changed prior to commit:
  https://reviews.llvm.org/D120870?vs=412606=417330#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120870/new/

https://reviews.llvm.org/D120870

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsRISCV.td

Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -220,7 +220,7 @@
   }
   // For unit stride load with mask
   // Input: (maskedoff, pointer, mask, vl, policy)
-  class RISCVUSLoadMask
+  class RISCVUSLoadMasked
 : Intrinsic<[llvm_anyvector_ty ],
 [LLVMMatchType<0>,
  LLVMPointerType>,
@@ -235,7 +235,7 @@
   // Output: (data, vl)
   // NOTE: We model this with default memory properties since we model writing
   // VL as a side effect. IntrReadMem, IntrHasSideEffects does not work.
-  class RISCVUSLoadFFMask
+  class RISCVUSLoadFFMasked
 : Intrinsic<[llvm_anyvector_ty, llvm_anyint_ty],
 [LLVMMatchType<0>,
  LLVMPointerType>,
@@ -256,7 +256,7 @@
   }
   // For strided load with mask
   // Input: (maskedoff, pointer, stride, mask, vl, policy)
-  class RISCVSLoadMask
+  class RISCVSLoadMasked
 : Intrinsic<[llvm_anyvector_ty ],
 [LLVMMatchType<0>,
  LLVMPointerType>, llvm_anyint_ty,
@@ -278,7 +278,7 @@
   }
   // For indexed load with mask
   // Input: (maskedoff, pointer, index, mask, vl, policy)
-  class RISCVILoadMask
+  class RISCVILoadMasked
 : Intrinsic<[llvm_anyvector_ty ],
 [LLVMMatchType<0>,
  LLVMPointerType>, llvm_anyvector_ty,
@@ -300,7 +300,7 @@
   }
   // For unit stride store with mask
   // Input: (vector_in, pointer, mask, vl)
-  class RISCVUSStoreMask
+  class RISCVUSStoreMasked
 : Intrinsic<[],
 [llvm_anyvector_ty,
  LLVMPointerType>,
@@ -321,7 +321,7 @@
   }
   // For stride store with mask
   // Input: (vector_in, pointer, stirde, mask, vl)
-  class RISCVSStoreMask
+  class RISCVSStoreMasked
 : Intrinsic<[],
 [llvm_anyvector_ty,
  LLVMPointerType>, llvm_anyint_ty,
@@ -341,7 +341,7 @@
   }
   // For indexed store with mask
   // Input: (vector_in, pointer, index, mask, vl)
-  class RISCVIStoreMask
+  class RISCVIStoreMasked
 : Intrinsic<[],
 [llvm_anyvector_ty,
  LLVMPointerType>, llvm_anyvector_ty,
@@ -351,7 +351,7 @@
   }
   // For destination vector type is the same as source vector.
   // Input: (passthru, vector_in, vl)
-  class RISCVUnaryAANoMask
+  class RISCVUnaryAAUnMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
 [IntrNoMem]>, RISCVVIntrinsic {
@@ -359,7 +359,7 @@
   }
   // For destination vector type is the same as first source vector (with mask).
   // Input: (vector_in, vector_in, mask, vl, policy)
-  class RISCVUnaryAAMask
+  class RISCVUnaryAAMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>,
  LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
@@ -377,7 +377,7 @@
   }
   // For destination vector type is the same as first and second source vector.
   // Input: (vector_in, vector_in, vl)
-  class RISCVBinaryAAANoMask
+  class RISCVBinaryAAAUnMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
 [IntrNoMem]>, RISCVVIntrinsic {
@@ -385,7 +385,7 @@
   }
   // For destination vector type is the same as first and second source vector.
   // Input: (passthru, vector_in, int_vector_in, vl)
-  class RISCVRGatherVVNoMask
+  class RISCVRGatherVVUnMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>,
  LLVMVectorOfBitcastsToInt<0>, llvm_anyint_ty],
@@ -394,7 +394,7 @@
   }
   // For destination vector type is the same as first and second source vector.
   // Input: (vector_in, vector_in, int_vector_in, vl, policy)
-  class RISCVRGatherVVMask
+  class RISCVRGatherVVMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMVectorOfBitcastsToInt<0>,
  LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
@@ -403,7 +403,7 @@
 let 

[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG10fd2822b77e: [RISCV] Add policy operand for masked compare 
and vmsbf/vmsif/vmsof IR (authored by khchen).
Herald added a subscriber: StephenFan.

Changed prior to commit:
  https://reviews.llvm.org/D120228?vs=416057=417297#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120228/new/

https://reviews.llvm.org/D120228

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof.ll

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[PATCH] D120227: [RISCV] Add policy operand for masked vid and viota IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9ab18cc53537: [RISCV] Add policy operand for masked vid and 
viota IR intrinsics. (authored by khchen).
Herald added subscribers: s, StephenFan, arichardson.
Herald added a project: All.

Changed prior to commit:
  https://reviews.llvm.org/D120227?vs=410209=417223#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120227/new/

https://reviews.llvm.org/D120227

Files:
  clang/include/clang/Basic/riscv_vector.td
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vid.ll
  llvm/test/CodeGen/RISCV/rvv/viota.ll

Index: llvm/test/CodeGen/RISCV/rvv/viota.ll
===
--- llvm/test/CodeGen/RISCV/rvv/viota.ll
+++ llvm/test/CodeGen/RISCV/rvv/viota.ll
@@ -27,7 +27,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv1i8_nxv1i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
@@ -40,7 +40,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -69,7 +69,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv2i8_nxv2i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1:
@@ -82,7 +82,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -111,7 +111,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv4i8_nxv4i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1:
@@ -124,7 +124,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -153,7 +153,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv8i8_nxv8i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1:
@@ -166,7 +166,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -195,7 +195,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv16i8_nxv16i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1:
@@ -208,7 +208,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -237,7 +237,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv32i8_nxv32i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1:
@@ -250,7 +250,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -279,7 +279,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv64i8_nxv64i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1:
@@ -292,7 +292,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -321,7 +321,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv1i16_nxv1i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1:
@@ -334,7 +334,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -363,7 +363,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv2i16_nxv2i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1:
@@ -376,7 +376,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -405,7 +405,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv4i16_nxv4i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1:
@@ -418,7 +418,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -447,7 +447,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv8i16_nxv8i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1:
@@ -460,7 +460,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -489,7 +489,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv16i16_nxv16i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1:
@@ -502,7 +502,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -531,7 +531,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv32i16_nxv32i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: 

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

[Zakk Chen via Phabricator via cfe-commits]

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121984/new/

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[PATCH] D121578: [RISCV][NFC] Add tests to address invalid arch dependencies.

[Zakk Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf5fea45d09e5: [RISCV][NFC] Add tests to address invalid arch 
dependencies. (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121578/new/

https://reviews.llvm.org/D121578

Files:
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -224,6 +224,31 @@
 // RV32-ORDER: error: invalid arch name 'rv32imcq',
 // RV32-ORDER: standard user-level extension not given in canonical order 'q'
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv64e -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-EER %s
+// RV64-EER: error: invalid arch name 'rv64e',
+// RV64-EER: standard user-level extension 'e' requires 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-DER %s
+// RV32-DER: error: invalid arch name 'rv32id',
+// RV32-DER: d requires f extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32f -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
+// RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
+// RV32-ZVE32F-ER: zve32f requires f or zfinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzve64d -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
+// RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',
+// RV32-ZVE64D-ER: zve64d requires d or zdinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl64b -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
+// RV32-ZVL64B-ER: error: invalid arch name 'rv32izvl64b',
+// RV32-ZVL64B-ER: zvl*b requires v or zve* extension to also be specified
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32imw -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-STD-INVAL %s
 // RV32-STD-INVAL: error: invalid arch name 'rv32imw',
@@ -376,6 +401,18 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfh01p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFH %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfh -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFH %s
+// RV32-ZFH: "-target-feature" "+zfh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfhmin01p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfhmin -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
+// RV32-ZFHMIN: "-target-feature" "+zfhmin"
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -224,6 +224,31 @@
 // RV32-ORDER: error: invalid arch name 'rv32imcq',
 // RV32-ORDER: standard user-level extension not given in canonical order 'q'
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv64e -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-EER %s
+// RV64-EER: error: invalid arch name 'rv64e',
+// RV64-EER: standard user-level extension 'e' requires 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-DER %s
+// RV32-DER: error: invalid arch name 'rv32id',
+// RV32-DER: d requires f extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32f -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
+// RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
+// RV32-ZVE32F-ER: zve32f requires f or zfinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzve64d -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
+// RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',
+// RV32-ZVE64D-ER: zve64d requires d or zdinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl64b -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
+// RV32-ZVL64B-ER: error: invalid arch name 'rv32izvl64b',
+// RV32-ZVL64B-ER: zvl*b requires v or zve* extension to also be specified
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32imw 

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.
Herald added a subscriber: s.

In D70401#3384758 , @pcwang-thead 
wrote:

> In D70401#3250049 , @khchen wrote:
>
>> 1. please add a check here 
>> 
>>  and a clang cc1 test for it.
>> 2. Have you try to run llvm-test-suite with rv32e config on qemu?
>
>
>
> 1. Thanks, I may do it later. And here is a question: the comment 
> 
>  says `It is illegal to specify 'e' extensions with 'f' and 'd'`.
>
> While ilp32e 
> 
>  says:
>
>> The ILP32E calling convention is not compatible with ISAs that have 
>> registers that require load and store alignments of more than 32 bits. In 
>> particular, this calling convention must not be used with the D ISA 
>> extension.
>
> And, the RV32E 
>  chapter 
> in RISCV ISA manual says:
>
>> RV32E can be combined with all current standard extensions.
>
> If I understand correctly, E can't be combined with D in current 
> specification since E must use ILP32E calling convention.

IMO, at least clang need to follows the gcc's implementation.
I guess gcc implementation follow riscv-elf-psabi-doc, @kito-cheng could you 
please confirm that?

> 2. I have run llvm-test-suite with rv32e on qemu, and found no major fault 
> for current implementation. Some tests are disabled because they can't run on 
> bare mental (sees Disabled llvm-test-suite cases 
> ).
>
> There are some failed tests due to floating-point precision, but I saw the 
> same result when run with  rv32imc on bare mental. I haven't taken the time 
> to find out the reason, but I guess it may be soft-float issues.

Thanks for testing!! I also tested your patch locally, 
Could you please make sure all gcc and clang results are the same in your 
failed tests?

I found 
https://github.com/llvm/llvm-test-suite/blob/main/SingleSource/UnitTests/2003-05-26-Shorts.c
 result is mismatched with gcc's (-march=rv32e -mabi=ilp32e).
Did you have same issue?

my build option:

  $/path/to/rv32e-gcc/bin/riscv32-unknown-elf-gcc -march=rv32e -mabi=ilp32e 
2003-05-26-Shorts.c
  $./bin/clang --target=riscv32 -march=rv32e -mabi=ilp32e 
--gcc-toolchain=/path/to/rv32e-gcc/ 2003-05-26-Shorts.c 

clang output:

 ui = 3318069411 (0xc5c5b8a3) UL-ui = 0 (0xafafafaf)

  ui*ui = 2382936009 (0x8e08b7c9)   UL/ui = -2060025877491592863 
(0xe3695161)   


  i = -976897885 (0xc5c5b8a3) L-i = 0 (0xafafafb0)  

   i* i = -1912031287 (0x8e08b7c9)L/ i = 6996953267980741613 
(0x611a2bed0001)   


  us= 47267 (0xb8a3)  UL-us = -4195947477825748992 
(0xc5c5afafafaf) 
  us*us = 2234169289 (0x852ab7c9)   UL/us = 1452874783539635691 
(0x1429a5ebf397)


   s= -18269 (0xb8a3) L-s = -4195666002849038335 
(0xc5c6afafafaf)   
   s* s = 333756361 (0x13e4b7c9)  L/ s = -7718140893307295808 
(0x94e3a7c1201b)  


  ub= 163 (0xa3)  UL-ub = -4195745167686238208 
(0xc5c5b800afafafaf) 
  ub*ub = 26569 (0x67c9)  UL/ub = 2350833624863004346 
(0x209fd6ba0113eca9)  


   b= -93 (0xffa3)L-b = -4195744068174610431 
(0xc5c5b900afafafaf)   
   b* b = 8649 (0x21c9)   L/b = -1938405340110362979 
(0xe519669d00dd1421)   

gcc output:

 ui = 3318069411 (0xc5c5b8a3) UL-ui = -5787213829993660416 
(0xafafafaf)
  ui*ui = 2382936009 (0x8e08b7c9)   UL/ui = 3815330145 (0xe3695161)
  
  i = -976897885 (0xc5c5b8a3) L-i = -5787213825698693120 
(0xafafafb0)
   i* i = -1912031287 (0x8e08b7c9)L/ i = 5924072429 (0x1611a2bed)
  
  us= 47267 (0xb8a3)  UL-us = -5787213826675638272 
(0xafafafafc5c5)
  us*us = 2234169289 (0x852ab7c9)   UL/us = 267830203885035 (0xf3971429a5eb)
  
   s= -18269 (0xb8a3) L-s = -5787213826675572736 
(0xafafafafc5c6)
   s* s = 333756361 (0x13e4b7c9)  L/ s = 316777810864064 (0x1201b94e3a7c0)
  
  ub= 163 (0xa3)  UL-ub = -5787213826675591168 

[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 416057.
khchen added a comment.
Herald added subscribers: s, arichardson.

rebase on main.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof.ll

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[PATCH] D121345: [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

LGTM. wait @kito-cheng  to approve it.


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[PATCH] D121578: [RISCV][NFC] Add tests to address invalid arch dependencies.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, kito-cheng.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD.
Herald added a project: clang.

Improve test converage.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121578

Files:
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -224,6 +224,31 @@
 // RV32-ORDER: error: invalid arch name 'rv32imcq',
 // RV32-ORDER: standard user-level extension not given in canonical order 'q'
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv64e -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-EER %s
+// RV64-EER: error: invalid arch name 'rv64e',
+// RV64-EER: standard user-level extension 'e' requires 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-DER %s
+// RV32-DER: error: invalid arch name 'rv32id',
+// RV32-DER: d requires f extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32f -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
+// RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
+// RV32-ZVE32F-ER: zve32f requires f or zfinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzve64d -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
+// RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',
+// RV32-ZVE64D-ER: zve64d requires d or zdinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl64b -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
+// RV32-ZVL64B-ER: error: invalid arch name 'rv32izvl64b',
+// RV32-ZVL64B-ER: zvl*b requires v or zve* extension to also be specified
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32imw -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-STD-INVAL %s
 // RV32-STD-INVAL: error: invalid arch name 'rv32imw',
@@ -376,6 +401,18 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfh01p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFH %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfh -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFH %s
+// RV32-ZFH: "-target-feature" "+zfh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfhmin01p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfhmin -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
+// RV32-ZFHMIN: "-target-feature" "+zfhmin"
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -224,6 +224,31 @@
 // RV32-ORDER: error: invalid arch name 'rv32imcq',
 // RV32-ORDER: standard user-level extension not given in canonical order 'q'
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv64e -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-EER %s
+// RV64-EER: error: invalid arch name 'rv64e',
+// RV64-EER: standard user-level extension 'e' requires 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-DER %s
+// RV32-DER: error: invalid arch name 'rv32id',
+// RV32-DER: d requires f extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32f -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
+// RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
+// RV32-ZVE32F-ER: zve32f requires f or zfinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzve64d -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
+// RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',
+// RV32-ZVE64D-ER: zve64d requires d or zdinx extension to also be specified
+
+// RUN: %clang 

[PATCH] D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

Makes sense to me, but I'd appreciate someone else for a final LGTM.




Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4683
+Ops.push_back(VL);
+Ops.push_back(DAG.getUNDEF(XLenVT)); // Policy
+  }

arcbbb wrote:
> kito-cheng wrote:
> > Is this operand for tail policy? if so why this is `UNDEF`? I guess this 
> > should be `TAIL_AGNOSTIC` rather than `UNDEF`?
> Because unmasked pseudos doesn't have a policy operand,
> TA/TU is distinguished by checking if passthru is undef. I think it is proper 
> to leave undef here.
nit: maybe we could add a comment for that, because it must be `UNDEF` to match 
unmaksed pattern successfully.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4678
+MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
+SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
+Ops.push_back(Mask);

I think `TrueMask` maybe better.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:619
+  VReg result_reg_class,
+  VReg op2_reg_class
+  > {

--> `VReg op2_reg_class> {`



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:649
+defvar ivti = GetIntVTypeInfo.Vti;
+
+defm : VPatConvertStrictSDNode_VLhttps://reviews.llvm.org/D120449/new/

https://reviews.llvm.org/D120449

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[PATCH] D120870: [RISCV][NFC] Refine and refactor RISCVVEmitter and riscv_vector.td.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, kito-cheng, arcbbb, monkchiang, 
eopXD.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

1. Rename nomask as unmasked to match the word in rvv spec.
2. Merge UnMaskpolicy and Maskedpolicy arguments into one in RVVBuiltin class.
3. Rename HasAutoDef as HasBuiltinAlias.
4. Move header definition code into one individual class.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120870

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsRISCV.td

Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -220,7 +220,7 @@
   }
   // For unit stride load with mask
   // Input: (maskedoff, pointer, mask, vl, policy)
-  class RISCVUSLoadMask
+  class RISCVUSLoadMasked
 : Intrinsic<[llvm_anyvector_ty ],
 [LLVMMatchType<0>,
  LLVMPointerType>,
@@ -235,7 +235,7 @@
   // Output: (data, vl)
   // NOTE: We model this with default memory properties since we model writing
   // VL as a side effect. IntrReadMem, IntrHasSideEffects does not work.
-  class RISCVUSLoadFFMask
+  class RISCVUSLoadFFMasked
 : Intrinsic<[llvm_anyvector_ty, llvm_anyint_ty],
 [LLVMMatchType<0>,
  LLVMPointerType>,
@@ -256,7 +256,7 @@
   }
   // For strided load with mask
   // Input: (maskedoff, pointer, stride, mask, vl, policy)
-  class RISCVSLoadMask
+  class RISCVSLoadMasked
 : Intrinsic<[llvm_anyvector_ty ],
 [LLVMMatchType<0>,
  LLVMPointerType>, llvm_anyint_ty,
@@ -278,7 +278,7 @@
   }
   // For indexed load with mask
   // Input: (maskedoff, pointer, index, mask, vl, policy)
-  class RISCVILoadMask
+  class RISCVILoadMasked
 : Intrinsic<[llvm_anyvector_ty ],
 [LLVMMatchType<0>,
  LLVMPointerType>, llvm_anyvector_ty,
@@ -300,7 +300,7 @@
   }
   // For unit stride store with mask
   // Input: (vector_in, pointer, mask, vl)
-  class RISCVUSStoreMask
+  class RISCVUSStoreMasked
 : Intrinsic<[],
 [llvm_anyvector_ty,
  LLVMPointerType>,
@@ -321,7 +321,7 @@
   }
   // For stride store with mask
   // Input: (vector_in, pointer, stirde, mask, vl)
-  class RISCVSStoreMask
+  class RISCVSStoreMasked
 : Intrinsic<[],
 [llvm_anyvector_ty,
  LLVMPointerType>, llvm_anyint_ty,
@@ -341,7 +341,7 @@
   }
   // For indexed store with mask
   // Input: (vector_in, pointer, index, mask, vl)
-  class RISCVIStoreMask
+  class RISCVIStoreMasked
 : Intrinsic<[],
 [llvm_anyvector_ty,
  LLVMPointerType>, llvm_anyvector_ty,
@@ -351,7 +351,7 @@
   }
   // For destination vector type is the same as source vector.
   // Input: (passthru, vector_in, vl)
-  class RISCVUnaryAANoMask
+  class RISCVUnaryAAUnMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
 [IntrNoMem]>, RISCVVIntrinsic {
@@ -359,7 +359,7 @@
   }
   // For destination vector type is the same as first source vector (with mask).
   // Input: (vector_in, vector_in, mask, vl, policy)
-  class RISCVUnaryAAMask
+  class RISCVUnaryAAMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>,
  LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
@@ -377,7 +377,7 @@
   }
   // For destination vector type is the same as first and second source vector.
   // Input: (vector_in, vector_in, vl)
-  class RISCVBinaryAAANoMask
+  class RISCVBinaryAAAUnMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
 [IntrNoMem]>, RISCVVIntrinsic {
@@ -385,7 +385,7 @@
   }
   // For destination vector type is the same as first and second source vector.
   // Input: (passthru, vector_in, int_vector_in, vl)
-  class RISCVRGatherVVNoMask
+  class RISCVRGatherVVUnMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>,
  LLVMVectorOfBitcastsToInt<0>, llvm_anyint_ty],
@@ -394,7 +394,7 @@
   }
   // For destination vector type is the same as first 

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4e115b7d8811: [RISCV] Update computeTargetABI from llc as 
well as clang (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D118333?vs=406842=411315#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118333/new/

https://reviews.llvm.org/D118333

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-calling-conv.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
  llvm/test/CodeGen/RISCV/fastcc-float.ll
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
  llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll
  llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
  llvm/test/CodeGen/RISCV/select-const.ll
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
  llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
  llvm/test/MC/RISCV/mattr-invalid-combination.s

Index: llvm/test/MC/RISCV/mattr-invalid-combination.s
===
--- llvm/test/MC/RISCV/mattr-invalid-combination.s
+++ llvm/test/MC/RISCV/mattr-invalid-combination.s
@@ -1,4 +1,4 @@
 # RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \
 # RUN:   | FileCheck %s -check-prefix=RV64E
 
-# RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target
+# RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32'
Index: llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
===
--- llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
+++ llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 \
 ; RUN:   -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
Index: llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
===
--- llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32IBT
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64IBT
 
 ; Selects of wide values are split into two selects, which can easily cause
Index: llvm/test/CodeGen/RISCV/select-const.ll
===
--- llvm/test/CodeGen/RISCV/select-const.ll
+++ llvm/test/CodeGen/RISCV/select-const.ll
@@ -1,19 +1,19 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IF %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IFBT %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck 

[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, 
jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

Those operations are updated under a tail agnostic policy, but they
could have mask agnostic or undisturbed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120228

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof.ll

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[PATCH] D120227: [RISCV] Add policy operand for masked vid and viota IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, 
jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

Those masked operations are missed the policy operand.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120227

Files:
  clang/include/clang/Basic/riscv_vector.td
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vid.ll
  llvm/test/CodeGen/RISCV/rvv/viota.ll

Index: llvm/test/CodeGen/RISCV/rvv/viota.ll
===
--- llvm/test/CodeGen/RISCV/rvv/viota.ll
+++ llvm/test/CodeGen/RISCV/rvv/viota.ll
@@ -27,7 +27,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv1i8_nxv1i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
@@ -40,7 +40,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -69,7 +69,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv2i8_nxv2i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1:
@@ -82,7 +82,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -111,7 +111,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv4i8_nxv4i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1:
@@ -124,7 +124,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -153,7 +153,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv8i8_nxv8i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1:
@@ -166,7 +166,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -195,7 +195,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv16i8_nxv16i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1:
@@ -208,7 +208,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -237,7 +237,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv32i8_nxv32i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1:
@@ -250,7 +250,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -279,7 +279,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv64i8_nxv64i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1:
@@ -292,7 +292,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -321,7 +321,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv1i16_nxv1i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1:
@@ -334,7 +334,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -363,7 +363,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv2i16_nxv2i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1:
@@ -376,7 +376,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -405,7 +405,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv4i16_nxv4i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1:
@@ -418,7 +418,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -447,7 +447,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv8i16_nxv8i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1:
@@ -460,7 +460,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -489,7 +489,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv16i16_nxv16i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1:
@@ -502,7 +502,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -531,7 +531,7 @@
   ,
   ,
 

[PATCH] D119727: [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGca783124073f: [RISCV] Add the policy operand for nomask 
vector Multiply-Add IR intrinsics. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D119727?vs=408840=409687#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119727/new/

https://reviews.llvm.org/D119727

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

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[PATCH] D119686: [RISCV] Add the passthru operand for nomask vadc/vsbc/vmerge/vfmerge IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG093ecccdab47: [RISCV] Add the passthru operand for 
vadc/vsbc/vmerge/vfmerge IR intrinsics. (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119686/new/

https://reviews.llvm.org/D119686

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll

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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D70401#3325419 , @zixuan-wu wrote:

> It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there 
> are no workable environment such as runtime and kernel for ilp32e in GNU 
> series tools.
> And we can not run llvm-test-suite in baremental environment(NOT linux but 
> elf triple). So I have a question about how to test llvm in elf triple and 
> environment? Is there any test case llvm community normally uses and accepts?

I believe you can try QEMU, I tried it before.
https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/JE0aG-Mr0u4/m/tfFoITv7AgAJ
For llvm-test-suite, you could disable some non-baremental tests manually.
I found some issues in my local rv32e implementation by running llvm-test-suite 
before, it's why I think it's good to have a test.

Maybe the other reviewers have different opinions about this.
@luismarques @jrtc27 @asb @kito-cheng What do you think?


Repository:
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[PATCH] D119686: [RISCV] Add the passthru operand for nomask vadc/vsbc/vmerge/vfmerge IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 409156.
khchen added a comment.

rebase and add more one test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119686/new/

https://reviews.llvm.org/D119686

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll

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[PATCH] D118253: [RISCV] Add the passthru operand for some RVV nomask unary and nullary intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe8973dd389e7: [RISCV] Add the passthru operand for some RVV 
nomask unary and nullary… (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D118253?vs=403269=409155#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118253/new/

https://reviews.llvm.org/D118253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vfclass.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
  llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
  llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vid.ll
  llvm/test/CodeGen/RISCV/rvv/viota.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
  llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll

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[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb7847199044e: [RISCV] Add the passthru operand for RVV 
nomask binary intrinsics. (authored by khchen).
Herald added a subscriber: qcolombet.

Changed prior to commit:
  https://reviews.llvm.org/D117989?vs=408696=409119#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117989/new/

https://reviews.llvm.org/D117989

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul-eew64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul-eew64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c
  

[PATCH] D119727: [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 408840.
khchen added a comment.

Rebase and refine code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119727/new/

https://reviews.llvm.org/D119727

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

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[PATCH] D119727: [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, 
jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.

The nomask vector Multiply-Add need a policy operand because merge value could 
not be undef.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119727

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

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[PATCH] D119686: [RISCV] Add the passthru operand for vadc/vsbc/vmerge/vfmerge IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, 
jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119686

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll

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[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd224be3b999a: [RISCV] Add the policy operand for some masked 
RVV ternary IR intrinsics. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D117681?vs=403117=407849#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117681/new/

https://reviews.llvm.org/D117681

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

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[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

Gentle ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117681/new/

https://reviews.llvm.org/D117681

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[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

Gentle ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117989/new/

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[PATCH] D119250: [RISCV][NFC] Refactor RISCVISAInfo.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcfe7f690367b: [RISCV][NFC] Refactor RISCVISAInfo. (authored 
by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119250/new/

https://reviews.llvm.org/D119250

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -45,11 +45,8 @@
   else
 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
-  unsigned XLen = STI.hasFeature(RISCV::Feature64Bit) ? 64 : 32;
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, STI.getFeatureBits());
-
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
+  auto ParseResult = RISCVFeatures::parseFeatureBits(
+  STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
   if (!ParseResult) {
 /* Assume any error about features should handled earlier.  */
 consumeError(ParseResult.takeError());
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -18,6 +18,7 @@
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/SubtargetFeature.h"
+#include "llvm/Support/RISCVISAInfo.h"
 
 namespace llvm {
 
@@ -344,9 +345,8 @@
 // triple. Exits with report_fatal_error if not.
 void validate(const Triple , const FeatureBitset );
 
-// Convert FeatureBitset to FeatureVector.
-void toFeatureVector(std::vector ,
- const FeatureBitset );
+llvm::Expected>
+parseFeatureBits(bool IsRV64, const FeatureBitset );
 
 } // namespace RISCVFeatures
 
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -16,6 +16,7 @@
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/Support/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
@@ -106,13 +107,17 @@
 report_fatal_error("RV32E can't be enabled for an RV64 target");
 }
 
-void toFeatureVector(std::vector ,
- const FeatureBitset ) {
+llvm::Expected>
+parseFeatureBits(bool IsRV64, const FeatureBitset ) {
+  unsigned XLen = IsRV64 ? 64 : 32;
+  std::vector FeatureVector;
+  // Convert FeatureBitset to FeatureVector.
   for (auto Feature : RISCVFeatureKV) {
 if (FeatureBits[Feature.Value] &&
 llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
   FeatureVector.push_back(std::string("+") + Feature.Key);
   }
+  return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
 }
 
 } // namespace RISCVFeatures
Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -329,21 +329,6 @@
   return true;
 }
 
-StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo ) {
-  if (ISAInfo.getXLen() == 32) {
-if (ISAInfo.hasExtension("d"))
-  return "ilp32d";
-if (ISAInfo.hasExtension("e"))
-  return "ilp32e";
-return "ilp32";
-  } else if (ISAInfo.getXLen() == 64) {
-if (ISAInfo.hasExtension("d"))
-  return "lp64d";
-return "lp64";
-  }
-  llvm_unreachable("Invalid XLEN");
-}
-
 } // namespace RISCV
 } // namespace llvm
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -914,3 +914,18 @@
 return std::move(Result);
   return std::move(ISAInfo);
 }
+
+StringRef RISCVISAInfo::computeDefaultABI() const {
+  if (XLen == 32) {
+if (hasExtension("d"))
+  return "ilp32d";
+if (hasExtension("e"))
+  return "ilp32e";
+return "ilp32";
+  } else if (XLen == 64) {
+if (hasExtension("d"))
+  return "lp64d";
+return "lp64";
+  }
+  llvm_unreachable("Invalid XLEN");
+}
Index: llvm/include/llvm/Support/TargetParser.h
===
--- 

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 406842.
khchen added a comment.

rebase on D119250  to make changes clear.

Thanks for kito's suggestion!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118333/new/

https://reviews.llvm.org/D118333

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-calling-conv.ll
  llvm/test/CodeGen/RISCV/double-imm.ll
  llvm/test/CodeGen/RISCV/double-mem.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
  llvm/test/CodeGen/RISCV/fastcc-float.ll
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/frm-dependency.ll
  llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll
  llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
  llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
  llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
  llvm/test/CodeGen/RISCV/select-const.ll
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
  llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
  llvm/test/MC/RISCV/mattr-invalid-combination.s

Index: llvm/test/MC/RISCV/mattr-invalid-combination.s
===
--- llvm/test/MC/RISCV/mattr-invalid-combination.s
+++ llvm/test/MC/RISCV/mattr-invalid-combination.s
@@ -1,4 +1,4 @@
 # RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \
 # RUN:   | FileCheck %s -check-prefix=RV64E
 
-# RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target
+# RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32'
Index: llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
===
--- llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
+++ llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 \
 ; RUN:   -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
Index: llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
===
--- llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32IBT
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64IBT
 
 ; Selects of wide values are split into two selects, which can easily cause
Index: llvm/test/CodeGen/RISCV/select-const.ll
===
--- llvm/test/CodeGen/RISCV/select-const.ll
+++ llvm/test/CodeGen/RISCV/select-const.ll
@@ -1,19 +1,19 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 

[PATCH] D119250: [RISCV][NFC] Refactor RISCVISAInfo.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: asb, kito-cheng, craig.topper, jrtc27.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, dexonsmith, evandro, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, niosHD, sabuasal, simoncook, johnrusso, rbar, 
hiraditya.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

1. Remove computeDefaultABIFromArch and add computeDefaultABI in

RISCVISAInfo.

2. Add parseFeatureBits which may used in D118333 
.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119250

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -45,11 +45,8 @@
   else
 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
-  unsigned XLen = STI.hasFeature(RISCV::Feature64Bit) ? 64 : 32;
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, STI.getFeatureBits());
-
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
+  auto ParseResult = RISCVFeatures::parseFeatureBits(
+  STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
   if (!ParseResult) {
 /* Assume any error about features should handled earlier.  */
 consumeError(ParseResult.takeError());
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -18,6 +18,7 @@
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/SubtargetFeature.h"
+#include "llvm/Support/RISCVISAInfo.h"
 
 namespace llvm {
 
@@ -344,9 +345,8 @@
 // triple. Exits with report_fatal_error if not.
 void validate(const Triple , const FeatureBitset );
 
-// Convert FeatureBitset to FeatureVector.
-void toFeatureVector(std::vector ,
- const FeatureBitset );
+llvm::Expected>
+parseFeatureBits(bool IsRV64, const FeatureBitset );
 
 } // namespace RISCVFeatures
 
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -16,6 +16,7 @@
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/Support/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
@@ -106,13 +107,17 @@
 report_fatal_error("RV32E can't be enabled for an RV64 target");
 }
 
-void toFeatureVector(std::vector ,
- const FeatureBitset ) {
+llvm::Expected>
+parseFeatureBits(bool IsRV64, const FeatureBitset ) {
+  unsigned XLen = IsRV64 ? 64 : 32;
+  std::vector FeatureVector;
+  // Convert FeatureBitset to FeatureVector.
   for (auto Feature : RISCVFeatureKV) {
 if (FeatureBits[Feature.Value] &&
 llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
   FeatureVector.push_back(std::string("+") + Feature.Key);
   }
+  return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
 }
 
 } // namespace RISCVFeatures
Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -329,21 +329,6 @@
   return true;
 }
 
-StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo ) {
-  if (ISAInfo.getXLen() == 32) {
-if (ISAInfo.hasExtension("d"))
-  return "ilp32d";
-if (ISAInfo.hasExtension("e"))
-  return "ilp32e";
-return "ilp32";
-  } else if (ISAInfo.getXLen() == 64) {
-if (ISAInfo.hasExtension("d"))
-  return "lp64d";
-return "lp64";
-  }
-  llvm_unreachable("Invalid XLEN");
-}
-
 } // namespace RISCV
 } // namespace llvm
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -914,3 +914,18 @@
 return std::move(Result);
   return std::move(ISAInfo);
 }
+
+StringRef 

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

clang will calculate the default target-abi if -mabi is empty and encode the it 
in LLVM IR module flag.
then if llc has no target-abi option (`Options.MCOptions.ABIName` is empty), in 
getSubtargetImpl it uses different way to compute the default target-abi, then 
the default result is not same.
Currently it works well because getSubtargetImpl only check the ABI when 
`Options.MCOptions.ABIName` is not empty.


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[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll:162
+
+attributes #0 = { vscale_range(2,1024) }
+attributes #1 = { vscale_range(4,1024) }

frasercrmck wrote:
> khchen wrote:
> > frasercrmck wrote:
> > > khchen wrote:
> > > > frasercrmck wrote:
> > > > > khchen wrote:
> > > > > > I'm thinking do we need to test zvl and vscale_range in the same 
> > > > > > attribute?
> > > > > > ex. `attributes #0 = { vscale_range(2,1024) 
> > > > > > "target-features"="+zvl512b" }`
> > > > > Perhaps yeah. Just to check - what exactly for? Because we need `zvl` 
> > > > > in the attributes for correctness, or in order to test the 
> > > > > combination of `zvl` architecture and `vscale_range` to test what 
> > > > > happens when they disagree?
> > > > Just test for they disagree.
> > > > Do you know what's expected value for different `vscale_range` value in 
> > > > two function after function inlining? If they are always have the same 
> > > > minimum value for VLEN, I think we don't need a check.
> > > Good idea.
> > > 
> > > As for inlining, I can't see anything that would //prevent// inlining of 
> > > functions with different `vscale_range` attributes, per se. However, I 
> > > was looking at `TTI::areInlineCompatible` and the default implementation 
> > > checks whether CPU/Feature Strings are equivalent. The frontend should 
> > > ensure that `vscale_range` attributes match up 1:1 with our `+zvl` 
> > > feature strings so I think in practice we won't inline functions with 
> > > different `zvl` values in clang-generated C/C++ code. But users could 
> > > write IR with different `vscale_range` attributes and we'd happily inline 
> > > them, which sounds fishy. What do you think?
> > Thanks for investigation!!! 
> > I think we can postpone this inline issue until we really need to fix it. 
> > at least the function would keep the feature string, which may include 
> > zvl*b, right?
> > 
> > BTW, could you please try the C code in https://godbolt.org/z/6hfTaxTj5 to 
> > see what's `vscale_range` value for function `vadd256` and `vadd512`? Are 
> > they expected value?
> > 
> > 
> Yeah the feature string looks to contain `zvl*b` as we expect -- in simple 
> cases (see below). I've updated this test to check for them too.
> 
> Thanks for the example! I tried it. We have a couple of issues.
> 
> Firstly, the `vscale_range` is not correctly set for the functions. It is 
> taken from whichever `zvl*b` we set on the command line. If I do 
> `-target-feature +zvl128b` all functions have `vscale_range(2,1024)`, if I do 
> `-target-feature +zvl256b` all functions have `(4,1024)`, etc. So something's 
> not being communicated properly.
> 
> The second issue is that, because of this (I think) when using the non-CC1 
> driver, the subtarget initialization crashes if I compile with 
> `-march=rv64gcv` or any `zvl*b` up to `-march=rv64gcv_zvl512b1p0` because the 
> `-march` we specify there determines the `vscale_range` which in turn 
> determines `RVVBitsMin`, but that's "lower than the Zvl*b limitation" so an 
> assert triggers.
Sorry, I have no idea about what's good way to fix them, or maybe RISC-V has 
not already supported ifunc then we could ignore this example, I'm not sure.

BTW, I'm wondering why we want to support `vscale_range` attribute in RISC-V V.
Could we get any benefit after supporting it? 
It seems like SVE does not have a way to encode vector length information, so 
it must introduce a new function attribute `vscale_range` in IR.
But in RISC-V V, we already have zvl*b target-feature to get the minimum vlen 
information, and the maximum vlen is always 65536. In addition, we also have 
default implication rule for zvl*b depend on V/Zve*.

It seem like we are trying to support users's manually IRs which have 
`vscale_range` without zvl*b target-feature, is it?  
Or am I misunderstanding the intention?


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[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:99
+  if (VScaleRangeAttr.isValid()) {
+RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
+if (VScaleRangeAttr.getVScaleRangeMax().hasValue())

Could we have an assertion to prevent RVVBitsMin and Zvl are different?




Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:105
+  RVVBitsMax = RISCV::RVVVLENBitsMax;
+  }
+  // Allow user options to override these.

For forward compatibility, if there is no VScaleRangeAttr, maybe we could 
initialize the RVVBitsMin as zvl*b if it is present?
I guess maybe some exist IRs have zvl with no VScaleRangeAttr?



Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll:162
+
+attributes #0 = { vscale_range(2,1024) }
+attributes #1 = { vscale_range(4,1024) }

frasercrmck wrote:
> khchen wrote:
> > frasercrmck wrote:
> > > khchen wrote:
> > > > I'm thinking do we need to test zvl and vscale_range in the same 
> > > > attribute?
> > > > ex. `attributes #0 = { vscale_range(2,1024) 
> > > > "target-features"="+zvl512b" }`
> > > Perhaps yeah. Just to check - what exactly for? Because we need `zvl` in 
> > > the attributes for correctness, or in order to test the combination of 
> > > `zvl` architecture and `vscale_range` to test what happens when they 
> > > disagree?
> > Just test for they disagree.
> > Do you know what's expected value for different `vscale_range` value in two 
> > function after function inlining? If they are always have the same minimum 
> > value for VLEN, I think we don't need a check.
> Good idea.
> 
> As for inlining, I can't see anything that would //prevent// inlining of 
> functions with different `vscale_range` attributes, per se. However, I was 
> looking at `TTI::areInlineCompatible` and the default implementation checks 
> whether CPU/Feature Strings are equivalent. The frontend should ensure that 
> `vscale_range` attributes match up 1:1 with our `+zvl` feature strings so I 
> think in practice we won't inline functions with different `zvl` values in 
> clang-generated C/C++ code. But users could write IR with different 
> `vscale_range` attributes and we'd happily inline them, which sounds fishy. 
> What do you think?
Thanks for investigation!!! 
I think we can postpone this inline issue until we really need to fix it. 
at least the function would keep the feature string, which may include zvl*b, 
right?

BTW, could you please try the C code in https://godbolt.org/z/6hfTaxTj5 to see 
what's `vscale_range` value for function `vadd256` and `vadd512`? Are they 
expected value?




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[PATCH] D118333: [RISCV] Update computeTargetABI implementation.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D118333#3275940 , @jrtc27 wrote:

> I think this is the same idea as D118333 ? 
> Other than being a cleaner way of achieving the same goal. I've not looked to 
> see if there are any functional differences between the two.

The goal of this patch is making llvm and clang have same way to get default 
target-abi.

D113959  only changes the llvm part and it 
still not same with clang.


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[PATCH] D118333: [RISCV] Update computeTargetABI implementation.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, jrtc27, frasercrmck, kito-cheng, arcbbb, 
monkchiang, eopXD.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
armkevincheng, eric-k256, vkmr, dexonsmith, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, niosHD, sabuasal, 
simoncook, johnrusso, rbar, asb, hiraditya, qcolombet.
Herald added a reviewer: sjarus.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

I think it's good to have one logic to get the default
target-abi if no explicit ABI is given, because currently
we have two different logic in front-end and back-end.

The front-end is defautl to the ilp32/ilp32e/lp64 ABI, and
ilp32d/lp64d when hardware support for extension D.
The backend is default to the ilp32/ilp32e/lp64 ABI.

Due to the default target-abi had changed, I update some tests
by specific the target-abi with old default value to make the
expected result unchanged.


Repository:
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https://reviews.llvm.org/D118333

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-calling-conv.ll
  llvm/test/CodeGen/RISCV/double-imm.ll
  llvm/test/CodeGen/RISCV/double-mem.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
  llvm/test/CodeGen/RISCV/fastcc-float.ll
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/frm-dependency.ll
  llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll
  llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
  llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
  llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
  llvm/test/CodeGen/RISCV/select-const.ll
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
  llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll

Index: llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
===
--- llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
+++ llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 \
 ; RUN:   -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
Index: llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
===
--- llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32IBT
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s 

[PATCH] D118253: [RISCV] Add the passthru operand for some RVV nomask unary and nullary intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, 
jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.

My plan is to handle more complex operations in follow-up patches.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vfclass.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
  llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
  llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vid.ll
  llvm/test/CodeGen/RISCV/rvv/viota.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
  llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll

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[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 403117.
khchen added a comment.

rebase and address Craig's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117681/new/

https://reviews.llvm.org/D117681

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

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