[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-08 Thread Nuno Lopes via Phabricator via cfe-commits 
nlopes added a comment.

In D126745#3693790 , @khchen wrote:

> @nlopes we will update all undef to poison in follow up patches.

Thank you!
The benefit is that we want to remove undef altogether, so I'm trying to avoid 
having more undefs introduced, and if possible have everyone help reducing its 
usage whenever possible.
Thank you for your help!


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-02 Thread Zakk Chen via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7eddeb9e99f3: [RISCV][Clang] Support policy functions for 
vmerge, vfmerge and (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126745?vs=433263=449336#toc

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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
@@ -981,7 +981,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1f16.nxv1f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf4_t test_vmerge_vvm_f16mf4 (vbool64_t mask, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
+vfloat16mf4_t test_vmerge_vvm_f16mf4(vbool64_t mask, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
   return vmerge_vvm_f16mf4(mask, op1, op2, vl);
 }
 
@@ -990,7 +990,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv2f16.nxv2f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf2_t test_vmerge_vvm_f16mf2 (vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
+vfloat16mf2_t test_vmerge_vvm_f16mf2(vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
   return vmerge_vvm_f16mf2(mask, op1, op2, vl);
 }
 
@@ -999,7 +999,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv4f16.nxv4f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m1_t test_vmerge_vvm_f16m1 (vbool16_t mask, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+vfloat16m1_t test_vmerge_vvm_f16m1(vbool16_t mask, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
   return vmerge_vvm_f16m1(mask, op1, op2, vl);
 }
 
@@ -1008,7 +1008,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv8f16.nxv8f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m2_t test_vmerge_vvm_f16m2 (vbool8_t mask, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
+vfloat16m2_t test_vmerge_vvm_f16m2(vbool8_t mask, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
   return vmerge_vvm_f16m2(mask, op1, op2, vl);
 }
 
@@ -1017,7 +1017,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv16f16.nxv16f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m4_t test_vmerge_vvm_f16m4 (vbool4_t mask, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
+vfloat16m4_t test_vmerge_vvm_f16m4(vbool4_t mask, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
   return vmerge_vvm_f16m4(mask, op1, op2, vl);
 }
 
@@ -1026,6 +1026,96 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv32f16.nxv32f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m8_t test_vmerge_vvm_f16m8 (vbool2_t mask, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
+vfloat16m8_t test_vmerge_vvm_f16m8(vbool2_t mask, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
   return vmerge_vvm_f16m8(mask, op1, op2, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmerge_vvm_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1i32.nxv1i32.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint32mf2_t test_vmerge_vvm_i32mf2_tu(vbool64_t mask, vint32mf2_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmerge_vvm_i32mf2_tu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmerge_vxm_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1i32.i32.i64( [[MERGE:%.*]],  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint32mf2_t test_vmerge_vxm_i32mf2_tu(vbool64_t mask, vint32mf2_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
+  return vmerge_vxm_i32mf2_tu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL:

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-02 Thread Zakk Chen via Phabricator via cfe-commits 
khchen added a comment.

@nlopes we will update all undef to poison in follow up patches.


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-01 Thread Zakk Chen via Phabricator via cfe-commits 
khchen added a comment.

oops.. all tests need to updated and include all intrinsic IR tests...
Is there any benefit to switch UndefValue to PoisonValue?
maybe those changed should be in other follow-up patches?


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-01 Thread Zakk Chen via Phabricator via cfe-commits 
khchen added a comment.

In D126745#3691544 , @craig.topper 
wrote:

> In D126745#3691528 , @khchen wrote:
>
>> In D126745#3678776 , @nlopes wrote:
>>
>>> While at it, could you switch those UndefValue with PoisonValue if 
>>> possible?  Thank you!
>>
>> I'm not sure UndefValue will work because the backend would only check 
>> isUndef() to generate correct code...
>
> PoisonValue and UndefValue are both turned into undef in SelectionDAG today.

thanks @craig.topper, I will switch UndefValue with PoisonValue.


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-01 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added a comment.

In D126745#3691528 , @khchen wrote:

> In D126745#3678776 , @nlopes wrote:
>
>> While at it, could you switch those UndefValue with PoisonValue if possible? 
>>  Thank you!
>
> I'm not sure UndefValue will work because the backend would only check 
> isUndef() to generate correct code...

PoisonValue and UndefValue are both turned into undef in SelectionDAG today.


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-01 Thread Zakk Chen via Phabricator via cfe-commits 
khchen added a comment.

In D126745#3678776 , @nlopes wrote:

> While at it, could you switch those UndefValue with PoisonValue if possible?  
> Thank you!

I'm not sure UndefValue will work because the backend would only check 
isUndef() to generate correct code...


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-07-26 Thread Nuno Lopes via Phabricator via cfe-commits 
nlopes added a comment.

While at it, could you switch those UndefValue with PoisonValue if possible?  
Thank you!


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-07-26 Thread Kito Cheng via Phabricator via cfe-commits 
kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.
Herald added a subscriber: nlopes.

LGTM, and verified with internal testsuite :)


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-05-31 Thread Zakk Chen via Phabricator via cfe-commits 
khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

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https://reviews.llvm.org/D126745

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
@@ -981,7 +981,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1f16.nxv1f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf4_t test_vmerge_vvm_f16mf4 (vbool64_t mask, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
+vfloat16mf4_t test_vmerge_vvm_f16mf4(vbool64_t mask, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
   return vmerge_vvm_f16mf4(mask, op1, op2, vl);
 }
 
@@ -990,7 +990,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv2f16.nxv2f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf2_t test_vmerge_vvm_f16mf2 (vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
+vfloat16mf2_t test_vmerge_vvm_f16mf2(vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
   return vmerge_vvm_f16mf2(mask, op1, op2, vl);
 }
 
@@ -999,7 +999,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv4f16.nxv4f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m1_t test_vmerge_vvm_f16m1 (vbool16_t mask, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+vfloat16m1_t test_vmerge_vvm_f16m1(vbool16_t mask, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
   return vmerge_vvm_f16m1(mask, op1, op2, vl);
 }
 
@@ -1008,7 +1008,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv8f16.nxv8f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m2_t test_vmerge_vvm_f16m2 (vbool8_t mask, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
+vfloat16m2_t test_vmerge_vvm_f16m2(vbool8_t mask, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
   return vmerge_vvm_f16m2(mask, op1, op2, vl);
 }
 
@@ -1017,7 +1017,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv16f16.nxv16f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m4_t test_vmerge_vvm_f16m4 (vbool4_t mask, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
+vfloat16m4_t test_vmerge_vvm_f16m4(vbool4_t mask, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
   return vmerge_vvm_f16m4(mask, op1, op2, vl);
 }
 
@@ -1026,6 +1026,96 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv32f16.nxv32f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m8_t test_vmerge_vvm_f16m8 (vbool2_t mask, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
+vfloat16m8_t test_vmerge_vvm_f16m8(vbool2_t mask, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
   return vmerge_vvm_f16m8(mask, op1, op2, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmerge_vvm_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1i32.nxv1i32.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint32mf2_t test_vmerge_vvm_i32mf2_tu(vbool64_t mask, vint32mf2_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmerge_vvm_i32mf2_tu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmerge_vxm_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1i32.i32.i64( [[MERGE:%.*]],  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint32mf2_t