Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2016-01-05 Thread Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rL256822: [ARM] [AARCH64] Add CodeGen IR tests for 
{VS}QRDML{AS}H v8.1a intrinsics. (authored by alelab01).

Changed prior to commit:
  http://reviews.llvm.org/D15223?vs=43885=43969#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D15223

Files:
  cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c
  cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c

Index: cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c
===
--- cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c
+++ cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c
@@ -1,128 +1,198 @@
 // REQUIRES: aarch64-registered-target
 
 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
-// RUN:  -target-feature +v8.1a -O3 -S -o - %s \
-// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
+// RUN:  -target-feature +v8.1a -S -emit-llvm -o - %s | FileCheck %s
 
  #include 
 
-// CHECK-AARCH64-LABEL: test_vqrdmlah_laneq_s16
+// CHECK-LABEL: test_vqrdmlah_laneq_s16
 int16x4_t test_vqrdmlah_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) {
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
+// CHECK: shufflevector <8 x i16> {{%.*}}, <8 x i16> {{%.*}}, <4 x i32> 
+// CHECK: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
+// CHECK: call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
   return vqrdmlah_laneq_s16(a, b, v, 7);
 }
 
-// CHECK-AARCH64-LABEL: test_vqrdmlah_laneq_s32
+// CHECK-LABEL: test_vqrdmlah_laneq_s32
 int32x2_t test_vqrdmlah_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) {
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
+// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <2 x i32> 
+// CHECK: call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
+// CHECK: call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
   return vqrdmlah_laneq_s32(a, b, v, 3);
 }
 
-// CHECK-AARCH64-LABEL: test_vqrdmlahq_laneq_s16
+// CHECK-LABEL: test_vqrdmlahq_laneq_s16
 int16x8_t test_vqrdmlahq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v) {
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
+// CHECK: shufflevector <8 x i16> {{%.*}}, <8 x i16> {{%.*}}, <8 x i32> 
+// CHECK: call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
+// CHECK: call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
   return vqrdmlahq_laneq_s16(a, b, v, 7);
 }
 
-// CHECK-AARCH64-LABEL: test_vqrdmlahq_laneq_s32
+// CHECK-LABEL: test_vqrdmlahq_laneq_s32
 int32x4_t test_vqrdmlahq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v) {
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
+// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> 
+// CHECK: call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
+// CHECK: call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
   return vqrdmlahq_laneq_s32(a, b, v, 3);
 }
 
-// CHECK-AARCH64-LABEL: test_vqrdmlahh_s16
+// CHECK-LABEL: test_vqrdmlahh_s16
 int16_t test_vqrdmlahh_s16(int16_t a, int16_t b, int16_t c) {
-// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}
+// CHECK: [[insb:%.*]] = insertelement <4 x i16> undef, i16 {{%.*}}, i64 0
+// CHECK: [[insc:%.*]] = insertelement <4 x i16> undef, i16 {{%.*}}, i64 0
+// CHECK: [[mul:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> [[insb]], <4 x i16> [[insc]])
+// CHECK: extractelement <4 x i16> [[mul]], i64 0
+// CHECK: [[insa:%.*]] = insertelement <4 x i16> undef, i16 {{%.*}}, i64 0
+// CHECK: [[insmul:%.*]] = insertelement <4 x i16> undef, i16 {{%.*}}, i64 0
+// CHECK: [[add:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> [[insa]], <4 x i16> [[insmul]])
+// CHECK: extractelement <4 x i16> [[add]], i64 0
   return vqrdmlahh_s16(a, b, c);
 }
 
-// CHECK-AARCH64-LABEL: test_vqrdmlahs_s32
+// CHECK-LABEL: test_vqrdmlahs_s32
 int32_t test_vqrdmlahs_s32(int32_t a, int32_t b, int32_t c) {
-// CHECK-AARCH64: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+// CHECK: call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 {{%.*}}, i32 {{%.*}})
+// CHECK: call i32 @llvm.aarch64.neon.sqadd.i32(i32 {{%.*}}, i32 {{%.*}})
   return vqrdmlahs_s32(a, b, c);
 }
 
-// CHECK-AARCH64-LABEL: test_vqrdmlahh_lane_s16
+// CHECK-LABEL: test_vqrdmlahh_lane_s16
 int16_t test_vqrdmlahh_lane_s16(int16_t a, int16_t b, int16x4_t c) {
-// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[3]
+// CHECK: extractelement <4 x i16> {{%.*}}, i32 3
+// CHECK: [[insb:%.*]] = insertelement <4 x i16> undef, i16 {{%.*}}, i64 0
+// CHECK:

Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2016-01-04 Thread Alexandros Lamprineas via cfe-commits 
labrinea updated the summary for this revision.
labrinea updated this revision to Diff 43885.
labrinea added a comment.

Disabled optimizers.


http://reviews.llvm.org/D15223

Files:
  test/CodeGen/aarch64-v8.1a-neon-intrinsics.c
  test/CodeGen/arm-v8.1a-neon-intrinsics.c

Index: test/CodeGen/arm-v8.1a-neon-intrinsics.c
===
--- test/CodeGen/arm-v8.1a-neon-intrinsics.c
+++ test/CodeGen/arm-v8.1a-neon-intrinsics.c
@@ -1,122 +1,187 @@
 // RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-feature +neon \
-// RUN:  -O3 -S -o - %s \
+// RUN:  -S -emit-llvm -o - %s \
 // RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM
+
 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
-// RUN:  -target-feature +v8.1a -O3 -S -o - %s \
+// RUN:  -target-feature +v8.1a -S -emit-llvm -o - %s \
 // RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
+
 // REQUIRES: arm-registered-target,aarch64-registered-target
 
 #include 
 
 // CHECK-LABEL: test_vqrdmlah_s16
 int16x4_t test_vqrdmlah_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
-// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+// CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
+// CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
+
+// CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
+// CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
   return vqrdmlah_s16(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlah_s32
 int32x2_t test_vqrdmlah_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
-// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+// CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
+// CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
+
+// CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
+// CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
   return vqrdmlah_s32(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlahq_s16
 int16x8_t test_vqrdmlahq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {
-// CHECK-ARM: vqrdmlah.s16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+// CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
+// CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
+
+// CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
+// CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
   return vqrdmlahq_s16(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlahq_s32
 int32x4_t test_vqrdmlahq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {
-// CHECK-ARM: vqrdmlah.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+// CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
+// CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
+
+// CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
+// CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
   return vqrdmlahq_s32(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlah_lane_s16
 int16x4_t test_vqrdmlah_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
-// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[3]
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
+// CHECK-ARM: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <4 x i32> 
+// CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
+// CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
+
+// CHECK-AARCH64: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <4 x i32> 
+// CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
+// CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
   return vqrdmlah_lane_s16(a, b, c, 3);
 }
 
 // CHECK-LABEL: test_vqrdmlah_lane_s32
 int32x2_t test_vqrdmlah_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
-// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[1]
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
+// CHECK-ARM: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}},

Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2016-01-04 Thread Eric Christopher via cfe-commits 
echristo accepted this revision.
echristo added a comment.
This revision is now accepted and ready to land.

LGTM, and thanks for all of the iteration.

-eric


http://reviews.llvm.org/D15223



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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-14 Thread Alexandros Lamprineas via cfe-commits 
labrinea added a comment.

Hi Eric,

The main optimization I feel is useful is mem2reg. Without that, if I want to 
properly check the right values go to the right operands of the intrinsic calls 
I have to write FileCheck matchers that match stores and their relevant loads, 
plus bitcasts. This not only looks more obfuscated than matching the mem2reg 
output, but it is also less resilient to changes in the way clang code 
generates.

The generated IR for each intrinsic is around 50 lines. I can just pick out the 
particular instructions I want to check, as you suggested, but they won't we 
connected by the flow of values. In my opinion such a test will be less 
valuable.

I can do this both ways but my preferred way is to run the bare minimum of 
optimization to de-cruft the output and make the test robust and readable. If 
you feel however that you don't want the optimizers run I will make a best 
effort at writing a test that doesn't use them.


http://reviews.llvm.org/D15223



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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-14 Thread Eric Christopher via cfe-commits 
echristo added a comment.

I understand the conflicting priorities here for sure. You'd like a test that's 
as minimal as possible, without having to depend on external (to clang) 
libraries here. I really would appreciate it if you'd make the test not rely on 
mem2reg etc so we can be sure that clang's code generation is the thing tested 
here and not the optimizer. Making sure that the unoptimized output reduces 
properly would be a great opt test for the backend though.

Thanks!

-eric


http://reviews.llvm.org/D15223



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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-14 Thread Eric Christopher via cfe-commits 
On Mon, Dec 14, 2015 at 11:05 AM Tim Northover 
wrote:

> > I don't think it's going to be even vaguely that bad here and that you're
> > blowing it a bit out of proportion. [...] It does make the tests a
> little harder
> > to write, but having done a bunch of them it's not that bad.
>
> I've also tried to write such tests in the past, and I did find it that
> bad.
>
> > Also you're relying on the behavior of
> > backend optimizations to figure out what's going on with your clang IR
> > generation which also seems less than optimal.
>
> I think it's fine if it leads to simpler tests that are easier to
> maintain. It's not completely isolated, but none of the testing we do
> really is.
>
>
There really is a pretty good separation of concerns and for a lot if not
most of the tests here all the difference is checking is the arguments,
keeping track of an alloca and making sure that goes is pretty simple and
not really hard for a test.

-eric
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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-14 Thread Tim Northover via cfe-commits 
On 14 December 2015 at 11:12, Eric Christopher  wrote:
> There really is a pretty good separation of concerns and for a lot if not
> most of the tests here all the difference is checking is the arguments,
> keeping track of an alloca and making sure that goes is pretty simple and
> not really hard for a test.

And the rest! This us the output for a trivial function: vqrdmulh_s16:

define <4 x i16> @foo(<4 x i16> %l, <4 x i16> %r) #0 {
entry:
  %__p0.addr.i = alloca <4 x i16>, align 8
  %__p1.addr.i = alloca <4 x i16>, align 8
  %__ret.i = alloca <4 x i16>, align 8
  %l.addr = alloca <4 x i16>, align 8
  %r.addr = alloca <4 x i16>, align 8
  store <4 x i16> %l, <4 x i16>* %l.addr, align 8
  store <4 x i16> %r, <4 x i16>* %r.addr, align 8
  %0 = load <4 x i16>, <4 x i16>* %l.addr, align 8
  %1 = load <4 x i16>, <4 x i16>* %r.addr, align 8
  store <4 x i16> %0, <4 x i16>* %__p0.addr.i, align 8
  store <4 x i16> %1, <4 x i16>* %__p1.addr.i, align 8
  %2 = load <4 x i16>, <4 x i16>* %__p0.addr.i, align 8
  %3 = bitcast <4 x i16> %2 to <8 x i8>
  %4 = load <4 x i16>, <4 x i16>* %__p1.addr.i, align 8
  %5 = bitcast <4 x i16> %4 to <8 x i8>
  %vqrdmulh_v.i = bitcast <8 x i8> %3 to <4 x i16>
  %vqrdmulh_v1.i = bitcast <8 x i8> %5 to <4 x i16>
  %vqrdmulh_v2.i = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x
i16> %vqrdmulh_v.i, <4 x i16> %vqrdmulh_v1.i) #2
  %vqrdmulh_v3.i = bitcast <4 x i16> %vqrdmulh_v2.i to <8 x i8>
  %6 = bitcast <8 x i8> %vqrdmulh_v3.i to <4 x i16>
  store <4 x i16> %6, <4 x i16>* %__ret.i, align 8
  %7 = load <4 x i16>, <4 x i16>* %__ret.i, align 8
  ret <4 x i16> %7
}

Is that right? Hope so, but I'm buggered if I know. And when anyone
looks at a test based on that they've got to thread 3 datapaths
through about 6 stages each without getting confused to work it out.
Possible, but for the tiny beneficial fuzzies we get from not running
opt, not worth it in my opinion.

Tim.
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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-14 Thread James Molloy via cfe-commits 
Fwiw, I am certainly in Tim'a camp here! Writing a test for that output is
doable, and if that's what people want then that's what we'll do. But it's
certainly not nice or readable !
On Mon, 14 Dec 2015 at 19:25, Tim Northover via cfe-commits <
cfe-commits@lists.llvm.org> wrote:

> On 14 December 2015 at 11:12, Eric Christopher  wrote:
> > There really is a pretty good separation of concerns and for a lot if not
> > most of the tests here all the difference is checking is the arguments,
> > keeping track of an alloca and making sure that goes is pretty simple and
> > not really hard for a test.
>
> And the rest! This us the output for a trivial function: vqrdmulh_s16:
>
> define <4 x i16> @foo(<4 x i16> %l, <4 x i16> %r) #0 {
> entry:
>   %__p0.addr.i = alloca <4 x i16>, align 8
>   %__p1.addr.i = alloca <4 x i16>, align 8
>   %__ret.i = alloca <4 x i16>, align 8
>   %l.addr = alloca <4 x i16>, align 8
>   %r.addr = alloca <4 x i16>, align 8
>   store <4 x i16> %l, <4 x i16>* %l.addr, align 8
>   store <4 x i16> %r, <4 x i16>* %r.addr, align 8
>   %0 = load <4 x i16>, <4 x i16>* %l.addr, align 8
>   %1 = load <4 x i16>, <4 x i16>* %r.addr, align 8
>   store <4 x i16> %0, <4 x i16>* %__p0.addr.i, align 8
>   store <4 x i16> %1, <4 x i16>* %__p1.addr.i, align 8
>   %2 = load <4 x i16>, <4 x i16>* %__p0.addr.i, align 8
>   %3 = bitcast <4 x i16> %2 to <8 x i8>
>   %4 = load <4 x i16>, <4 x i16>* %__p1.addr.i, align 8
>   %5 = bitcast <4 x i16> %4 to <8 x i8>
>   %vqrdmulh_v.i = bitcast <8 x i8> %3 to <4 x i16>
>   %vqrdmulh_v1.i = bitcast <8 x i8> %5 to <4 x i16>
>   %vqrdmulh_v2.i = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x
> i16> %vqrdmulh_v.i, <4 x i16> %vqrdmulh_v1.i) #2
>   %vqrdmulh_v3.i = bitcast <4 x i16> %vqrdmulh_v2.i to <8 x i8>
>   %6 = bitcast <8 x i8> %vqrdmulh_v3.i to <4 x i16>
>   store <4 x i16> %6, <4 x i16>* %__ret.i, align 8
>   %7 = load <4 x i16>, <4 x i16>* %__ret.i, align 8
>   ret <4 x i16> %7
> }
>
> Is that right? Hope so, but I'm buggered if I know. And when anyone
> looks at a test based on that they've got to thread 3 datapaths
> through about 6 stages each without getting confused to work it out.
> Possible, but for the tiny beneficial fuzzies we get from not running
> opt, not worth it in my opinion.
>
> Tim.
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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-14 Thread Tim Northover via cfe-commits 
> I don't think it's going to be even vaguely that bad here and that you're
> blowing it a bit out of proportion. [...] It does make the tests a little 
> harder
> to write, but having done a bunch of them it's not that bad.

I've also tried to write such tests in the past, and I did find it that bad.

> Also you're relying on the behavior of
> backend optimizations to figure out what's going on with your clang IR
> generation which also seems less than optimal.

I think it's fine if it leads to simpler tests that are easier to
maintain. It's not completely isolated, but none of the testing we do
really is.

Tim.
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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-14 Thread Tim Northover via cfe-commits 
On 14 December 2015 at 09:20, Eric Christopher via cfe-commits
 wrote:
> I understand the conflicting priorities here for sure. You'd like a test 
> that's as minimal as possible, without having to depend on external (to 
> clang) libraries here. I really would appreciate it if you'd make the test 
> not rely on mem2reg etc so we can be sure that clang's code generation is the 
> thing tested here and not the optimizer. Making sure that the unoptimized 
> output reduces properly would be a great opt test for the backend though.

I think I'm with Alexandros here. Tests based on raw Clang output are
horrific to write and maintain. They end up relying on implementation
details like just how many allocas and reloads Clang decides it needs
for some random expression, even working out whether the test is
correct changes from a pretty trivial eyeballing to keeping track of
dozens of lines of data-flow.

Tim.
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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-14 Thread Eric Christopher via cfe-commits 
On Mon, Dec 14, 2015 at 10:44 AM Tim Northover 
wrote:

> On 14 December 2015 at 09:20, Eric Christopher via cfe-commits
>  wrote:
> > I understand the conflicting priorities here for sure. You'd like a test
> that's as minimal as possible, without having to depend on external (to
> clang) libraries here. I really would appreciate it if you'd make the test
> not rely on mem2reg etc so we can be sure that clang's code generation is
> the thing tested here and not the optimizer. Making sure that the
> unoptimized output reduces properly would be a great opt test for the
> backend though.
>
> I think I'm with Alexandros here. Tests based on raw Clang output are
> horrific to write and maintain. They end up relying on implementation
> details like just how many allocas and reloads Clang decides it needs
> for some random expression, even working out whether the test is
> correct changes from a pretty trivial eyeballing to keeping track of
> dozens of lines of data-flow.
>
>
I don't think it's going to be even vaguely that bad here and that you're
blowing it a bit out of proportion. Also you're relying on the behavior of
backend optimizations to figure out what's going on with your clang IR
generation which also seems less than optimal. It does make the tests a
little harder to write, but having done a bunch of them it's not that bad.

-eric
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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-12 Thread James Molloy via cfe-commits 
jmolloy resigned from this revision.
jmolloy removed a reviewer: jmolloy.
jmolloy added a comment.

Eric is reviewing this; resigning myself.


http://reviews.llvm.org/D15223



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RE: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-11 Thread Alexandros Lamprineas via cfe-commits 
Ping. http://reviews.llvm.org/D15223 

-Original Message-
From: Eric Christopher [mailto:echri...@gmail.com] 
Sent: 07 December 2015 19:18
To: Alexandros Lamprineas; James Molloy; renato.go...@linaro.org; 
cfe-commits@lists.llvm.org
Cc: Amara Emerson
Subject: Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for 
{VS}QRDML{AS}H v8.1a intrinsics.

echristo added a comment.

One inline comment, thanks!

-eric



Comment at: test/CodeGen/aarch64-v8.1a-neon-intrinsics.c:4
@@ -3,4 +3,3 @@
 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN:  
-target-feature +v8.1a -O3 -S -o - %s \ -// RUN:  | FileCheck %s 
--check-prefix=CHECK --check-prefix=CHECK-AARCH64
+// RUN:  -target-feature +v8.1a -O1 -S -emit-llvm -o - %s | FileCheck 
+%s
 

Why do you need to enable the optimizers?


http://reviews.llvm.org/D15223





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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-11 Thread Eric Christopher via cfe-commits 
echristo added a comment.

Should be pretty easy to either use CHECK-DAG or pick out the particular 
instructions you want to check here. Otherwise you're just checking how the 
optimizer runs. That, in particular, also sounds like a good backend check.


http://reviews.llvm.org/D15223



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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-08 Thread Alexandros Lamprineas via cfe-commits 
labrinea added inline comments.


Comment at: test/CodeGen/aarch64-v8.1a-neon-intrinsics.c:4
@@ -3,4 +3,3 @@
 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
-// RUN:  -target-feature +v8.1a -O3 -S -o - %s \
-// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
+// RUN:  -target-feature +v8.1a -O1 -S -emit-llvm -o - %s | FileCheck %s
 

echristo wrote:
> Why do you need to enable the optimizers?
Our intention with these tests is to check that we are generating a sequence of 
{v/s}qrdmulh, {v/s}q{add/sub}{s}, shufflevector, {insert/extract}element IR 
instructions. Using -O1 promotes memory to registers, combines instructions, 
and therefore decreases the context of IR that we need to check.


http://reviews.llvm.org/D15223



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Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-07 Thread Alexandros Lamprineas via cfe-commits 
labrinea updated this revision to Diff 42035.
labrinea added a comment.

ASM tests have been removed.


http://reviews.llvm.org/D15223

Files:
  test/CodeGen/aarch64-v8.1a-neon-intrinsics.c
  test/CodeGen/arm-v8.1a-neon-intrinsics.c

Index: test/CodeGen/arm-v8.1a-neon-intrinsics.c
===
--- test/CodeGen/arm-v8.1a-neon-intrinsics.c
+++ test/CodeGen/arm-v8.1a-neon-intrinsics.c
@@ -1,122 +1,188 @@
 // RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-feature +neon \
-// RUN:  -O3 -S -o - %s \
+// RUN:  -O1 -S -emit-llvm -o - %s \
 // RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM
+
 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
-// RUN:  -target-feature +v8.1a -O3 -S -o - %s \
+// RUN:  -target-feature +v8.1a -O1 -S -emit-llvm -o - %s \
 // RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
+
 // REQUIRES: arm-registered-target,aarch64-registered-target
 
 #include 
 
 // CHECK-LABEL: test_vqrdmlah_s16
 int16x4_t test_vqrdmlah_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
-// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+// CHECK-ARM: [[mul:%.*]] = tail call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %b, <4 x i16> %c)
+// CHECK-ARM: tail call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %a, <4 x i16> [[mul]])
+
+// CHECK-AARCH64: [[mul:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %b, <4 x i16> %c)
+// CHECK-AARCH64: tail call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %a, <4 x i16> [[mul]])
   return vqrdmlah_s16(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlah_s32
 int32x2_t test_vqrdmlah_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
-// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+// CHECK-ARM: [[mul:%.*]] = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %b, <2 x i32> %c)
+// CHECK-ARM: tail call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %a, <2 x i32> [[mul]])
+
+// CHECK-AARCH64: [[mul:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %b, <2 x i32> %c)
+// CHECK-AARCH64: tail call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %a, <2 x i32> [[mul]])
   return vqrdmlah_s32(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlahq_s16
 int16x8_t test_vqrdmlahq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {
-// CHECK-ARM: vqrdmlah.s16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+// CHECK-ARM: [[mul:%.*]] = tail call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %b, <8 x i16> %c)
+// CHECK-ARM: tail call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %a, <8 x i16> [[mul]])
+
+// CHECK-AARCH64: [[mul:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %b, <8 x i16> %c)
+// CHECK-AARCH64: tail call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %a, <8 x i16> [[mul]])
   return vqrdmlahq_s16(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlahq_s32
 int32x4_t test_vqrdmlahq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {
-// CHECK-ARM: vqrdmlah.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+// CHECK-ARM: [[mul:%.*]] = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %b, <4 x i32> %c)
+// CHECK-ARM: tail call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %a, <4 x i32> [[mul]])
+
+// CHECK-AARCH64: [[mul:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %b, <4 x i32> %c)
+// CHECK-AARCH64: tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> [[mul]])
   return vqrdmlahq_s32(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlah_lane_s16
 int16x4_t test_vqrdmlah_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
-// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[3]
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
+// CHECK-ARM: [[shuffle:%.*]] = shufflevector <4 x i16> %c, <4 x i16> undef, <4 x i32> 
+// CHECK-ARM: [[mul:%.*]] = tail call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %b, <4 x i16> [[shuffle]])
+// CHECK-ARM: tail call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %a, <4 x i16> [[mul]])
+
+// CHECK-AARCH64: [[shuffle:%.*]] = shufflevector <4 x i16> %c, <4 x i16> undef, <4 x i32> 
+// CHECK-AARCH64: [[mul:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %b, <4 x i16> [[shuffle]])
+// CHECK-AARCH64: tail call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %a, <4 x i16> [[mul]])
   return vqrdmlah_lane_s16(a, b, c, 3);
 }
 
 // CHECK-LABEL: test_vqrdmlah_lane_s32
 int32x2_t test_vqrdmlah_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
-// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[1]
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s,

Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-07 Thread Eric Christopher via cfe-commits 
echristo added a comment.

One inline comment, thanks!

-eric



Comment at: test/CodeGen/aarch64-v8.1a-neon-intrinsics.c:4
@@ -3,4 +3,3 @@
 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
-// RUN:  -target-feature +v8.1a -O3 -S -o - %s \
-// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
+// RUN:  -target-feature +v8.1a -O1 -S -emit-llvm -o - %s | FileCheck %s
 

Why do you need to enable the optimizers?


http://reviews.llvm.org/D15223



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[PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-04 Thread Alexandros Lamprineas via cfe-commits 
labrinea created this revision.
labrinea added reviewers: jmolloy, rengolin, echristo, cfe-commits.
Herald added subscribers: rengolin, aemerson.

Existing tests are currently testing generated backend assembly. We want to 
test the generated frontend IR as well. As discussed on the list we would like 
to keep both ASM checks for integration testing and IR checks for unit testing.

http://reviews.llvm.org/D15223

Files:
  test/CodeGen/aarch64-v8.1a-neon-intrinsics.c
  test/CodeGen/arm-v8.1a-neon-intrinsics.c

Index: test/CodeGen/arm-v8.1a-neon-intrinsics.c
===
--- test/CodeGen/arm-v8.1a-neon-intrinsics.c
+++ test/CodeGen/arm-v8.1a-neon-intrinsics.c
@@ -1,122 +1,244 @@
 // RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-feature +neon \
 // RUN:  -O3 -S -o - %s \
-// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM
+// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM-ASM
+
+// RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-feature +neon \
+// RUN:  -O1 -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM-IR
+
 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
 // RUN:  -target-feature +v8.1a -O3 -S -o - %s \
-// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
+// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64-ASM
+
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
+// RUN:  -target-feature +v8.1a -O1 -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64-IR
+
 // REQUIRES: arm-registered-target,aarch64-registered-target
 
 #include 
 
 // CHECK-LABEL: test_vqrdmlah_s16
 int16x4_t test_vqrdmlah_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
-// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+// CHECK-ARM-ASM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-AARCH64-ASM: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+
+// CHECK-ARM-IR: [[mul:%.*]] = tail call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %b, <4 x i16> %c)
+// CHECK-ARM-IR: tail call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %a, <4 x i16> [[mul]])
+
+// CHECK-AARCH64-IR: [[mul:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %b, <4 x i16> %c)
+// CHECK-AARCH64-IR: tail call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %a, <4 x i16> [[mul]])
   return vqrdmlah_s16(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlah_s32
 int32x2_t test_vqrdmlah_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
-// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+// CHECK-ARM-ASM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-AARCH64-ASM: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+
+// CHECK-ARM-IR: [[mul:%.*]] = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %b, <2 x i32> %c)
+// CHECK-ARM-IR: tail call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %a, <2 x i32> [[mul]])
+
+// CHECK-AARCH64-IR: [[mul:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %b, <2 x i32> %c)
+// CHECK-AARCH64-IR: tail call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %a, <2 x i32> [[mul]])
   return vqrdmlah_s32(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlahq_s16
 int16x8_t test_vqrdmlahq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {
-// CHECK-ARM: vqrdmlah.s16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+// CHECK-ARM-ASM: vqrdmlah.s16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
+// CHECK-AARCH64-ASM: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+
+// CHECK-ARM-IR: [[mul:%.*]] = tail call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %b, <8 x i16> %c)
+// CHECK-ARM-IR: tail call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %a, <8 x i16> [[mul]])
+
+// CHECK-AARCH64-IR: [[mul:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %b, <8 x i16> %c)
+// CHECK-AARCH64-IR: tail call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %a, <8 x i16> [[mul]])
   return vqrdmlahq_s16(a, b, c);
 }
 
 // CHECK-LABEL: test_vqrdmlahq_s32
 int32x4_t test_vqrdmlahq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {
-// CHECK-ARM: vqrdmlah.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
-// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+// CHECK-ARM-ASM: vqrdmlah.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
+// CHECK-AARCH64-ASM: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+
+// CHECK-ARM-IR: [[mul:%.*]] = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %b, <4 x i32> %c)
+// CHECK-ARM-IR: tail call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %a, <4 x i32> [[mul]])
+
+// CHECK-AARCH64-IR: [[mul:%.*]] =

Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

2015-12-04 Thread Eric Christopher via cfe-commits 
echristo added a comment.

Please remove the asm tests here. As I stated in the original review thread 
there's no reason for them to be here.

Thanks.

-eric


http://reviews.llvm.org/D15223



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