[PATCH] D104822: [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

2021-06-24 Thread Craig Topper via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf225367305c8: [RISCV] Add vget/vset intrinsics for inserting 
and extracting between different… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D104822/new/

https://reviews.llvm.org/D104822

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
@@ -0,0 +1,546 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) {
+  return vset_v_i8m1_i8m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 24)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, vint8m1_t val) {
+  return vset_v_i8m1_i8m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.nxv16i8( [[DEST:%.*]],  [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, vint8m2_t val) {
+  return vset_v_i8m2_i8m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 56)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, vint8m1_t val) {
+  return vset_v_i8m1_i8m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv16i8( [[DEST:%.*]],  [[VAL:%.*]], i64 32)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, vint8m2_t val) {
+  return vset_v_i8m2_i8m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m4_i8m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv32i8( [[DEST:%.*]],  [[VAL:%.*]], i64 32)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m4_i8m8(vint8m8_t dest, vint8m4_t val) {
+  return vset_v_i8m4_i8m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.nxv4i16( [[DEST:%.*]],  [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m2_t test_vset_v_i16m1_i16m2(vint16m2_t dest, vint16m1_t val) {
+  return vset_v_i16m1_i16m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i16.nxv4i16( [[DEST:%.*]],  [[VAL:%.*]], i64 12)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m4_t test_vset_v_i16m1_i16m4(vint16m4_t dest, vint16m1_t val) {
+  return vset_v_i16m1_i16m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i16.nxv8i16( [[DEST:%.*]],  [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m4_t test_vset_v_i16m2_i16m4(vint16m4_t dest, vint16m2_t val) {
+  return vset_v_i16m2_i16m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i16.nxv4i16( [[DEST:%.*]],  [[VAL:%.*]], i64 28)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m8_t test_vset_v_i16m1_i16m8(vint16m8_t dest, vint16m1_t val) {
+  return vset_v_i16m1_i16m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i16.nxv8i16( [[DEST:%.*]],  [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//

[PATCH] D104822: [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

2021-06-24 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper updated this revision to Diff 354297.
craig.topper added a comment.

Add constant argument range checking to SemaChecking


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104822/new/

https://reviews.llvm.org/D104822

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
@@ -0,0 +1,546 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) {
+  return vset_v_i8m1_i8m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 24)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, vint8m1_t val) {
+  return vset_v_i8m1_i8m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.nxv16i8( [[DEST:%.*]],  [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, vint8m2_t val) {
+  return vset_v_i8m2_i8m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 56)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, vint8m1_t val) {
+  return vset_v_i8m1_i8m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv16i8( [[DEST:%.*]],  [[VAL:%.*]], i64 32)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, vint8m2_t val) {
+  return vset_v_i8m2_i8m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m4_i8m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv32i8( [[DEST:%.*]],  [[VAL:%.*]], i64 32)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m4_i8m8(vint8m8_t dest, vint8m4_t val) {
+  return vset_v_i8m4_i8m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.nxv4i16( [[DEST:%.*]],  [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m2_t test_vset_v_i16m1_i16m2(vint16m2_t dest, vint16m1_t val) {
+  return vset_v_i16m1_i16m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i16.nxv4i16( [[DEST:%.*]],  [[VAL:%.*]], i64 12)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m4_t test_vset_v_i16m1_i16m4(vint16m4_t dest, vint16m1_t val) {
+  return vset_v_i16m1_i16m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i16.nxv8i16( [[DEST:%.*]],  [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m4_t test_vset_v_i16m2_i16m4(vint16m4_t dest, vint16m2_t val) {
+  return vset_v_i16m2_i16m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i16.nxv4i16( [[DEST:%.*]],  [[VAL:%.*]], i64 28)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m8_t test_vset_v_i16m1_i16m8(vint16m8_t dest, vint16m1_t val) {
+  return vset_v_i16m1_i16m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i16.nxv8i16( [[DEST:%.*]],  [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m8_t test_vset_v_i16m2_i16m8(vint16m8_t dest, vint16m2_t val) {
+  return

[PATCH] D104822: [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

2021-06-24 Thread Fraser Cormack via Phabricator via cfe-commits 
frasercrmck added a comment.

What's supposed to happen if the provided index is invalid? I'm suspecting we'd 
currently get a IR verification error on the insert/extract indices. I'm 
wondering if we can/should catch that earlier?


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[PATCH] D104822: [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

2021-06-23 Thread Hsiangkai Wang via Phabricator via cfe-commits 
HsiangKai accepted this revision.
HsiangKai added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D104822: [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

2021-06-23 Thread Jiejie Rong via Phabricator via cfe-commits 
JojoR added a comment.

Thanks for your commit :)


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[PATCH] D104822: [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

2021-06-23 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper created this revision.
craig.topper added reviewers: frasercrmck, rogfer01, kito-cheng, khchen, 
arcbbb, HsiangKai, evandro.
Herald added subscribers: StephenFan, vkmr, dexonsmith, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb.
craig.topper requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

These allow getting a whole register from a larger lmul. Or
inserting a whole register into a larger lmul register. Fractional
lmuls are not supported as they would require a vslide.

Based on this update to the intrinsic doc
https://github.com/riscv/rvv-intrinsic-doc/pull/99


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D104822

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
@@ -0,0 +1,546 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) {
+  return vset_v_i8m1_i8m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 24)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, vint8m1_t val) {
+  return vset_v_i8m1_i8m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.nxv16i8( [[DEST:%.*]],  [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, vint8m2_t val) {
+  return vset_v_i8m2_i8m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 56)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, vint8m1_t val) {
+  return vset_v_i8m1_i8m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv16i8( [[DEST:%.*]],  [[VAL:%.*]], i64 32)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, vint8m2_t val) {
+  return vset_v_i8m2_i8m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m4_i8m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv32i8( [[DEST:%.*]],  [[VAL:%.*]], i64 32)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m4_i8m8(vint8m8_t dest, vint8m4_t val) {
+  return vset_v_i8m4_i8m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.nxv4i16( [[DEST:%.*]],  [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m2_t test_vset_v_i16m1_i16m2(vint16m2_t dest, vint16m1_t val) {
+  return vset_v_i16m1_i16m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i16.nxv4i16( [[DEST:%.*]],  [[VAL:%.*]], i64 12)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m4_t test_vset_v_i16m1_i16m4(vint16m4_t dest, vint16m1_t val) {
+  return vset_v_i16m1_i16m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i16.nxv8i16( [[DEST:%.*]],  [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint16m4_t test_vset_v_i16m2_i16m4(vint16m4_t dest, vint16m2_t val) {
+  return vset_v_i16m2_i16m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call