[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.
craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:25 +defvar TAIL_AGNOSTIC = 0; +defvar TAIL_UNDISTURBED = 1; Why are these the opposite polarity of what's in C? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105092/new/ https://reviews.llvm.org/D105092 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.
craig.topper added a comment.
Does lowerRISCVVMachineInstrToMCInst in RISCVMCInstLower.cpp need to know to
skip the policy op?
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:405
if (RISCVII::hasVLOp(TSFlags)) {
const MachineOperand = MI.getOperand(MI.getNumExplicitOperands() -
2);
if (VLOp.isImm())
Why doesn't this need to be updated?
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[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.
HsiangKai updated this revision to Diff 358205.
HsiangKai added a comment.
Add the TA argument to most of the intrinsics with mask.
Repository:
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Files:
clang/include/clang/Basic/riscv_vector.td
clang/test/CodeGen/RISCV/rvv-intrinsics/vadd-policy.c
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
Index: llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+
+declare @llvm.riscv.vadd.nxv8i8.nxv8i8(
+ ,
+ ,
+ i64);
+
+define @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT:vadd.vv v8, v8, v9
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vadd.nxv8i8.nxv8i8(
+ %0,
+ %1,
+i64 %2)
+
+ ret %a
+}
+
+declare @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ ,
+ ,
+ ,
+ ,
+ i64, i64);
+
+define @intrinsic_vadd_mask_tu( %0, %1, %2, %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_tu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetivli zero, 3, e8, m1, tu, mu
+; CHECK-NEXT:vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ %0,
+ %1,
+ %2,
+ %3,
+i64 %4, i64 0)
+
+ ret %a
+}
+
+define @intrinsic_vadd_mask_ta( %0, %1, %2, %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_ta:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetivli zero, 3, e8, m1, ta, mu
+; CHECK-NEXT:vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ %0,
+ %1,
+ %2,
+ %3,
+i64 %4, i64 1)
+
+ ret %a
+}
+
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -22,6 +22,9 @@
// Helpers to define the VL patterns.
//===--===//
+defvar TAIL_AGNOSTIC = 0;
+defvar TAIL_UNDISTURBED = 1;
+
def SDT_RISCVVLE_VL : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>,
SDTCisVT<2, XLenVT>]>;
def SDT_RISCVVSE_VL : SDTypeProfile<0, 3, [SDTCisVec<0>, SDTCisPtrTy<1>,
@@ -266,7 +269,7 @@
(result_type (IMPLICIT_DEF)),
op_reg_class:$rs1,
op_reg_class:$rs2,
- VMV0:$vm, GPR:$vl, sew)>;
+ VMV0:$vm, GPR:$vl, sew, TAIL_AGNOSTIC)>;
}
multiclass VPatBinaryVL_XI;
+ VMV0:$vm, GPR:$vl, sew, TAIL_AGNOSTIC)>;
}
multiclass VPatBinaryVL_VV_VX {
@@ -604,7 +607,7 @@
VLOpFrag),
(!cast("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK")
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2,
- VMV0:$vm, GPR:$vl, vti.Log2SEW)>;
+ VMV0:$vm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)),
(vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask),
VLOpFrag),
@@ -615,7 +618,7 @@
VLOpFrag),
(!cast("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK")
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, simm5:$rs2,
- VMV0:$vm, GPR:$vl, vti.Log2SEW)>;
+ VMV0:$vm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
// 12.3. Vector Integer Extension
@@ -1210,7 +1213,7 @@
VLOpFrag)),
(!cast("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK")
vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
- vti.Mask:$vm, GPR:$vl, vti.Log2SEW)>;
+ vti.Mask:$vm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
// emul = lmul * 16 / sew
defvar vlmul = vti.LMul;
@@ -1237,7 +1240,7 @@
VLOpFrag)),
(!cast(inst#"_MASK")
vti.RegClass:$merge,
[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.
HsiangKai updated this revision to Diff 355420.
HsiangKai added a comment.
- Use constant value for tail policy argument.
- Rename HasPolicy to HasPolicyOp.
Repository:
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Files:
clang/include/clang/Basic/riscv_vector.td
clang/test/CodeGen/RISCV/rvv-intrinsics/vadd-policy.c
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
Index: llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+
+declare @llvm.riscv.vadd.nxv8i8.nxv8i8(
+ ,
+ ,
+ i64);
+
+define @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT:vadd.vv v8, v8, v9
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vadd.nxv8i8.nxv8i8(
+ %0,
+ %1,
+i64 %2)
+
+ ret %a
+}
+
+declare @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ ,
+ ,
+ ,
+ ,
+ i64, i64);
+
+define @intrinsic_vadd_mask_tu( %0, %1, %2, %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_tu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetivli zero, 3, e8, m1, tu, mu
+; CHECK-NEXT:vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ %0,
+ %1,
+ %2,
+ %3,
+i64 %4, i64 0)
+
+ ret %a
+}
+
+define @intrinsic_vadd_mask_ta( %0, %1, %2, %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_ta:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetivli zero, 3, e8, m1, ta, mu
+; CHECK-NEXT:vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ %0,
+ %1,
+ %2,
+ %3,
+i64 %4, i64 1)
+
+ ret %a
+}
+
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -269,6 +269,36 @@
VMV0:$vm, GPR:$vl, sew)>;
}
+multiclass VPatBinaryVL_VV_WithPolicy {
+ def : Pat<(result_type (vop
+ (op_type op_reg_class:$rs1),
+ (op_type op_reg_class:$rs2),
+ (mask_type true_mask),
+ VLOpFrag)),
+(!cast(instruction_name#"_VV_"# vlmul.MX)
+ op_reg_class:$rs1,
+ op_reg_class:$rs2,
+ GPR:$vl, sew)>;
+ def : Pat<(result_type (vop
+ (op_type op_reg_class:$rs1),
+ (op_type op_reg_class:$rs2),
+ (mask_type VMV0:$vm),
+ VLOpFrag)),
+(!cast(instruction_name#"_VV_"# vlmul.MX#"_MASK")
+ (result_type (IMPLICIT_DEF)),
+ op_reg_class:$rs1,
+ op_reg_class:$rs2,
+ VMV0:$vm, GPR:$vl, sew, 0)>;
+}
+
multiclass VPatBinaryVL_XI;
}
+multiclass VPatBinaryVL_XI_WithPolicy {
+ def : Pat<(result_type (vop
+ (vop_type vop_reg_class:$rs1),
+ (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))),
+ (mask_type true_mask),
+ VLOpFrag)),
+(!cast(instruction_name#_#suffix#_# vlmul.MX)
+ vop_reg_class:$rs1,
+ xop_kind:$rs2,
+ GPR:$vl, sew)>;
+ def : Pat<(result_type (vop
+ (vop_type vop_reg_class:$rs1),
+ (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))),
+ (mask_type VMV0:$vm),
+ VLOpFrag)),
+(!cast(instruction_name#_#suffix#_# vlmul.MX#"_MASK")
+ (result_type (IMPLICIT_DEF)),
+ vop_reg_class:$rs1,
+ xop_kind:$rs2,
+ VMV0:$vm, GPR:$vl, sew, 0)>;
+}
+
multiclass VPatBinaryVL_VV_VX {
foreach vti = AllIntegerVectors in {
defm : VPatBinaryVL_VV {
+ foreach vti = AllIntegerVectors in {
+defm : VPatBinaryVL_VV_WithPolicy;
+defm : VPatBinaryVL_XI_WithPolicy;
+ }
+}
+
[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.
craig.topper added inline comments.
Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1148
+if (HasPolicy) {
+ ProtoMaskSeq.push_back("z");
+}
khchen wrote:
> maybe the policy argument should be a constant value ("Kz")?
Agreed.
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:80
+
+ HasPolicyShift = HasVLOpShift + 1,
+ HasPolicyMask = 1 << HasPolicyShift,
This should be HasPolicyOpShift and HasPolicyOpMask to match SEWOp/VLOp naming.
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:138
+static inline bool hasPolicy(uint64_t TSFlags) {
+ return TSFlags & HasPolicyMask;
hasPolicyOp
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:401
+const MachineOperand = MI.getOperand(NumOperands - 1);
+TailAgnostic = Op.getImm();
+ }
Probably need to mask this to bit 0. `TailAgnostic = Op.getImm() & 1`. As
written we'll set TailAgnostic if any bit in the immediate is non-zero.
Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:182
+
+ bit HasPolicy = false;
+ let TSFlags{16} = HasPolicy;
HasPolicyOp
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[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.
khchen added inline comments.
Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1148
+if (HasPolicy) {
+ ProtoMaskSeq.push_back("z");
+}
maybe the policy argument should be a constant value ("Kz")?
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[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.
HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, frasercrmck, rogfer01, kito-cheng.
Herald added subscribers: StephenFan, vkmr, dexonsmith, evandro, luismarques,
apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,
brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, niosHD,
sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
HsiangKai requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.
This is a proof-of-concept patch. It does not add the tail policy
argument to all the builtins/intrinsics. This patch uses vadd as an
example to add the tail policy argument.
I added several new classes. There is no need to add these classes in
the target description. I do so just to limit the modification to vadd
only.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D105092
Files:
clang/include/clang/Basic/riscv_vector.td
clang/test/CodeGen/RISCV/rvv-intrinsics/vadd-policy.c
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
Index: llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+
+declare @llvm.riscv.vadd.nxv8i8.nxv8i8(
+ ,
+ ,
+ i64);
+
+define @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT:vadd.vv v8, v8, v9
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vadd.nxv8i8.nxv8i8(
+ %0,
+ %1,
+i64 %2)
+
+ ret %a
+}
+
+declare @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ ,
+ ,
+ ,
+ ,
+ i64, i64);
+
+define @intrinsic_vadd_mask_tu( %0, %1, %2, %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_tu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetivli zero, 3, e8, m1, tu, mu
+; CHECK-NEXT:vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ %0,
+ %1,
+ %2,
+ %3,
+i64 %4, i64 0)
+
+ ret %a
+}
+
+define @intrinsic_vadd_mask_ta( %0, %1, %2, %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_ta:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetivli zero, 3, e8, m1, ta, mu
+; CHECK-NEXT:vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ %0,
+ %1,
+ %2,
+ %3,
+i64 %4, i64 1)
+
+ ret %a
+}
+
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -269,6 +269,36 @@
VMV0:$vm, GPR:$vl, sew)>;
}
+multiclass VPatBinaryVL_VV_WithPolicy {
+ def : Pat<(result_type (vop
+ (op_type op_reg_class:$rs1),
+ (op_type op_reg_class:$rs2),
+ (mask_type true_mask),
+ VLOpFrag)),
+(!cast(instruction_name#"_VV_"# vlmul.MX)
+ op_reg_class:$rs1,
+ op_reg_class:$rs2,
+ GPR:$vl, sew)>;
+ def : Pat<(result_type (vop
+ (op_type op_reg_class:$rs1),
+ (op_type op_reg_class:$rs2),
+ (mask_type VMV0:$vm),
+ VLOpFrag)),
+(!cast(instruction_name#"_VV_"# vlmul.MX#"_MASK")
+ (result_type (IMPLICIT_DEF)),
+ op_reg_class:$rs1,
+ op_reg_class:$rs2,
+ VMV0:$vm, GPR:$vl, sew, 0)>;
+}
+
multiclass VPatBinaryVL_XI;
}
+multiclass VPatBinaryVL_XI_WithPolicy {
+ def : Pat<(result_type (vop
+ (vop_type vop_reg_class:$rs1),
+ (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))),
+ (mask_type true_mask),
+ VLOpFrag)),
+(!cast(instruction_name#_#suffix#_# vlmul.MX)
+ vop_reg_class:$rs1,
+ xop_kind:$rs2,
+ GPR:$vl, sew)>;
+ def : Pat<(result_type (vop
+ (vop_type
