[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
NeHuang added subscribers: jroelofs, NeHuang. NeHuang added a comment. @jroelofs committed `f6769b663a0d4432b5e00e0c03904a5dfba7b077` to move the backend test cases from `CodeGen` -> `CodeGen/PowerPC` so they don't fail when the PPC backend isn't built. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap added a comment. issue should be fixed now; pushed with this: https://reviews.llvm.org/D106130#change-PZi4uueeCg9i (I just had to move the test files into the `PowerPC` folder). Will continue to monitor Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap added a comment. I'm aware of the getting target issue; the fix will be up soon. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3434ac9e3902: [PowerPC] Store, load, move from and to
registers related builtins (authored by Conanap).
Changed prior to commit:
https://reviews.llvm.org/D105946?vs=359945=360259#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 =
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 359945.
Conanap added a comment.
Fixed a typo
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+;
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 359850.
Conanap added a comment.
Changed flags for intrinsic of dcbtt and dcbtstt
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+;
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 359516.
Conanap marked an inline comment as done.
Conanap added a comment.
Moved pattern to a more appropriate place, updated test cases
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+;
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap marked 4 inline comments as done.
Conanap added a comment.
Addressed comments
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:15
+ // CHECK-LABEL: @test_lwarx
// CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}",
"=r,*Z,~{memory}"(i32* %a)
return __lwarx(a);
lei wrote:
> where is the check for `CHECK-NON-PWR8-ERR:`?
`lwarx` and `stwcx` are both available before power8, so the check is not
needed.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 359433.
Conanap marked an inline comment as done.
Conanap added a comment.
Updated test cases
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3,
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
lei added inline comments.
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:15
+ // CHECK-LABEL: @test_lwarx
// CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}",
"=r,*Z,~{memory}"(i32* %a)
return __lwarx(a);
where is the check for `CHECK-NON-PWR8-ERR:`?
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:36
// CHECK: %0 = bitcast i32* %a to i8*
// CHECK: %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %val)
return __stwcx(a, val);
`CHECK-NON-PWR8-ERR:` check?
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c:2
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
why are we only testing this for pwr9 vs pwr7/8 similar to other tests added?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:4072 + +def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), + (STXSIWX f64:$XT, ForceXForm:$dst)>; I just realized this is in the wrong place. STXSIWX was added in Power8 not in Power9. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll:10 +; RUN: -mcpu=pwr9 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \ +; RUN: -mcpu=pwr9 < %s | FileCheck %s Don't make all of these `pwr9`. Make some of them `pwr7` and some `pwr8`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 359380.
Conanap added a comment.
Updated a test case
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+;
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 359322.
Conanap marked 5 inline comments as done.
Conanap added a comment.
Added non-vsx pattern for stfiw, extra testline for that pattern,
some nits
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: #
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. This is getting close to approval. The newly added `__stfiw` needs to be fixed and some nits need to be addressed. Comment at: clang/lib/Sema/SemaChecking.cpp:3369 + case PPC::BI__builtin_ppc_stfiw: +return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions", +diag::err_ppc_builtin_only_on_arch, "9"); This is not correct. The instruction (non-VSX version) has existed since Power3. The VSX version was added in Power8. No changes to the instruction came in Power9 so I have no idea where the decision to add this check came from. In fact, this would also blow up in the back end if you compiled with something like `-mcpu=pwr9 -mno-altivec` or `-mcpu=pwr9 -mno-vsx`. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1568 [IntrWriteMem]>; + def int_ppc_sthcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem]>; + def int_ppc_dcbtstt : GCCBuiltin<"__builtin_ppc_dcbtstt">, Nit: line too long. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1577 + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; +def int_ppc_stfiw : GCCBuiltin<"__builtin_ppc_stfiw">, +Intrinsic<[], [llvm_ptr_ty, llvm_double_ty], [IntrWriteMem]>; Nit: indentation is inconsistent here. Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:4072 + +def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), + (STXSIWX f64:$XT, ForceXForm:$dst)>; This needs the non-VSX pattern as well. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll:1 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ One of the run lines should be with `-mattr=-vsx`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 359259.
Conanap added a comment.
Updated lharx and lbarx to inline asm implementation, implemented stfiw.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Taking this off the review queue until `lharx/lbarx` are changed to emit inline asm in line with `lwarx/ldarx`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 359104.
Conanap added a comment.
Changed more xoaddr to ForceXForm
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mfmsr:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mfmsr 4
+; CHECK-32BIT-NEXT:li 3, 0
+;
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 359097.
Conanap marked 2 inline comments as done.
Conanap added a comment.
Changed xoaddr, removed extws, changed check prefix
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mfmsr:
+; CHECK-32BIT: # %bb.0: # %entry
+;
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
lei added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1569 } - nit: un-related line deletion Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:5449 + def : Pat<(int_ppc_sthcx xoaddr:$dst, gprc:$A), + (STHCX (EXTSH gprc:$A), xoaddr:$dst)>; +} `EXTSH` should not be needed and we should not be using `xoaddr` Comment at: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll:7 +; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \ +; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \ this is confusing... maybe this shouldjust be `CHECK-32BIT` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 359066.
Conanap added a comment.
Added more tests, corrected sema checking and intrinsic flag
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_mftbu:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:mftbu 3
+; CHECK-AIX-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_mfmsr:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:mfmsr 4
+; CHECK-AIX-NEXT:li 3, 0
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. We have encountered an issue with `lwarx/ldarx` that required that they emit inline asm rather than an intrinsic. What makes `lbarx/lharx` different? Comment at: clang/lib/Sema/SemaChecking.cpp:3370 + case PPC::BI__builtin_ppc_lbarx: +return SemaFeatureCheck(*this, TheCall, "extdiv", +diag::err_ppc_builtin_only_on_arch, "8"); Why do these need the `extdiv` feature? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
lei added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3371 +return SemaFeatureCheck(*this, TheCall, "extdiv", +diag::err_ppc_builtin_only_on_arch, "8"); #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \ need tests for these. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
lei added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1569 + def int_ppc_sthcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem]>; + def int_ppc_lharx : GCCBuiltin<"__builtin_ppc_lharx">, + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; do these loads not need `IntrReadMem`? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap updated this revision to Diff 358738.
Conanap marked an inline comment as done.
Conanap added a comment.
Added more sema checking, test case update
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_mftbu:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:mftbu 3
+; CHECK-AIX-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_mfmsr:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:mfmsr 4
+;
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
lei added a comment.
please add sema checking for pwr8 builtins.
Comment at:
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll:80
+declare i32 @llvm.ppc.lharx(i8*)
+define dso_local signext i16 @test_lharx(i16* %a) local_unnamed_addr #0 {
+; CHECK-64-LABEL: test_lharx:
remove all reference to attributes, `local_unnamed_addr #[0..9]` since it's not
in the IR.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105946/new/
https://reviews.llvm.org/D105946
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
Conanap created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
Conanap requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.
This patch implements store, load, move from and to registers related
builtins. The patch aims to provide feature parady with xlC on AIX.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D105946
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtstt(i8* %0)
+ ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+ %0 = load i8*, i8** @vpa, align 8
+ tail call void @llvm.ppc.dcbtt(i8* %0)
+ ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_mftbu:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:mftbu 3
+; CHECK-AIX-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.mftbu()
+ ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:
