[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units
kamaub marked an inline comment as done. kamaub added a comment. Updated an existing test for the backend with pwr8 and pwr9 be/le targets during commit Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109599/new/ https://reviews.llvm.org/D109599 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units
This revision was automatically updated to reflect the committed changes. Closed by commit rG8737c74fab3a: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units (authored by kamaub). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit: https://reviews.llvm.org/D109599?vs=376300=377172#toc Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109599/new/ https://reviews.llvm.org/D109599 Files: clang/include/clang/Sema/Sema.h clang/lib/AST/ASTContext.cpp clang/lib/Sema/Sema.cpp clang/lib/Sema/SemaChecking.cpp clang/test/AST/ast-dump-ppc-types.c clang/test/CodeGen/ppc-mma-types.c clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp clang/test/Sema/ppc-mma-builtins.c clang/test/Sema/ppc-paired-vector-builtins.c llvm/test/CodeGen/PowerPC/mma-acc-memops.ll Index: llvm/test/CodeGen/PowerPC/mma-acc-memops.ll === --- llvm/test/CodeGen/PowerPC/mma-acc-memops.ll +++ llvm/test/CodeGen/PowerPC/mma-acc-memops.ll @@ -5,6 +5,18 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=BE-PAIRED +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ +; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \ +; RUN: | FileCheck %s --check-prefix=LE-PWR9 +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ +; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \ +; RUN: | FileCheck %s --check-prefix=LE-PWR8 +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ +; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \ +; RUN: | FileCheck %s --check-prefix=BE-PWR9 +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ +; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \ +; RUN: | FileCheck %s --check-prefix=BE-PWR8 @f = common dso_local local_unnamed_addr global <512 x i1> zeroinitializer, align 16 @g = common dso_local local_unnamed_addr global <256 x i1> zeroinitializer, align 16 @@ -35,6 +47,78 @@ ; BE-PAIRED-NEXT:stxv vs3, 176(r3) ; BE-PAIRED-NEXT:stxv vs2, 160(r3) ; BE-PAIRED-NEXT:blr +; +; LE-PWR9-LABEL: testLdSt: +; LE-PWR9: # %bb.0: # %entry +; LE-PWR9-NEXT:addis r3, r2, f@toc@ha +; LE-PWR9-NEXT:addi r3, r3, f@toc@l +; LE-PWR9-NEXT:lxv vs1, 96(r3) +; LE-PWR9-NEXT:lxv vs0, 64(r3) +; LE-PWR9-NEXT:lxv vs2, 112(r3) +; LE-PWR9-NEXT:stxv vs1, 160(r3) +; LE-PWR9-NEXT:lxv vs1, 80(r3) +; LE-PWR9-NEXT:stxv vs2, 176(r3) +; LE-PWR9-NEXT:stxv vs0, 128(r3) +; LE-PWR9-NEXT:stxv vs1, 144(r3) +; LE-PWR9-NEXT:blr +; +; LE-PWR8-LABEL: testLdSt: +; LE-PWR8: # %bb.0: # %entry +; LE-PWR8-NEXT:addis r3, r2, f@toc@ha +; LE-PWR8-NEXT:li r4, 96 +; LE-PWR8-NEXT:li r5, 112 +; LE-PWR8-NEXT:addi r3, r3, f@toc@l +; LE-PWR8-NEXT:lxvd2x vs0, r3, r4 +; LE-PWR8-NEXT:li r4, 64 +; LE-PWR8-NEXT:lxvd2x vs1, r3, r5 +; LE-PWR8-NEXT:li r5, 80 +; LE-PWR8-NEXT:lxvd2x vs2, r3, r4 +; LE-PWR8-NEXT:lxvd2x vs3, r3, r5 +; LE-PWR8-NEXT:li r4, 176 +; LE-PWR8-NEXT:li r5, 160 +; LE-PWR8-NEXT:stxvd2x vs1, r3, r4 +; LE-PWR8-NEXT:li r4, 144 +; LE-PWR8-NEXT:stxvd2x vs0, r3, r5 +; LE-PWR8-NEXT:li r5, 128 +; LE-PWR8-NEXT:stxvd2x vs3, r3, r4 +; LE-PWR8-NEXT:stxvd2x vs2, r3, r5 +; LE-PWR8-NEXT:blr +; +; BE-PWR9-LABEL: testLdSt: +; BE-PWR9: # %bb.0: # %entry +; BE-PWR9-NEXT:addis r3, r2, f@toc@ha +; BE-PWR9-NEXT:addi r3, r3, f@toc@l +; BE-PWR9-NEXT:lxv vs1, 96(r3) +; BE-PWR9-NEXT:lxv vs0, 64(r3) +; BE-PWR9-NEXT:lxv vs2, 112(r3) +; BE-PWR9-NEXT:stxv vs1, 160(r3) +; BE-PWR9-NEXT:lxv vs1, 80(r3) +; BE-PWR9-NEXT:stxv vs2, 176(r3) +; BE-PWR9-NEXT:stxv vs0, 128(r3) +; BE-PWR9-NEXT:stxv vs1, 144(r3) +; BE-PWR9-NEXT:blr +; +; BE-PWR8-LABEL: testLdSt: +; BE-PWR8: # %bb.0: # %entry +; BE-PWR8-NEXT:addis r3, r2, f@toc@ha +; BE-PWR8-NEXT:li r4, 96 +; BE-PWR8-NEXT:li r5, 112 +; BE-PWR8-NEXT:addi r3, r3, f@toc@l +; BE-PWR8-NEXT:lxvd2x vs0, r3, r4 +; BE-PWR8-NEXT:li r4, 64 +; BE-PWR8-NEXT:lxvd2x vs1, r3, r5 +; BE-PWR8-NEXT:li r5, 80 +; BE-PWR8-NEXT:lxvd2x vs2, r3, r4 +; BE-PWR8-NEXT:lxvd2x vs3, r3, r5 +; BE-PWR8-NEXT:li r4, 176 +; BE-PWR8-NEXT:li r5, 160 +; BE-PWR8-NEXT:stxvd2x vs1, r3, r4 +; BE-PWR8-NEXT:li r4, 144 +; BE-PWR8-NEXT:stxvd2x vs0, r3, r5 +; BE-PWR8-NEXT:li r5, 128 +; BE-PWR8-NEXT:stxvd2x vs3, r3, r4 +; BE-PWR8-NEXT:stxvd2x vs2, r3, r5 +; BE-PWR8-NEXT:blr entry: %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 1 %0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64 @@ -78,6 +162,84 @@ ; BE-PAIRED-NEXT:stxv vs3, 48(r3) ;
[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units
nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM as long as you add the back end test. Comment at: clang/test/CodeGen/ppc-mma-types.c:2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future \ +// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 \ +// RUN: -emit-llvm -O3 -o - %s | FileCheck %s Please add this IR test to the back end codegen tests (for older CPUs). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109599/new/ https://reviews.llvm.org/D109599 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units
kamaub updated this revision to Diff 376300.
kamaub added a comment.
Rebasing this patch and addressing review comments
An upstream commit removed the need for this patch to modify a few
test cases so it has been rebased to remain up-to-date, also addressing
review comments.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109599/new/
https://reviews.llvm.org/D109599
Files:
clang/include/clang/Sema/Sema.h
clang/lib/AST/ASTContext.cpp
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/AST/ast-dump-ppc-types.c
clang/test/CodeGen/ppc-mma-types.c
clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
clang/test/Sema/ppc-mma-builtins.c
clang/test/Sema/ppc-paired-vector-builtins.c
Index: clang/test/Sema/ppc-paired-vector-builtins.c
===
--- /dev/null
+++ clang/test/Sema/ppc-paired-vector-builtins.c
@@ -0,0 +1,28 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: -target-feature -paired-vector-memops -fsyntax-only %s -verify
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 \
+// RUN: -fsyntax-only %s -verify
+
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_pair res;
+ __builtin_vsx_assemble_pair(, vc, vc); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test3(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
+ __vector_pair vp = __builtin_vsx_lxvp(offset, vpp); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+ __builtin_vsx_stxvp(vp, offset, vp2); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_xxmtacc(); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+ *((__vector_quad *)resp) = vq;
+}
+
+
Index: clang/test/Sema/ppc-mma-builtins.c
===
--- /dev/null
+++ clang/test/Sema/ppc-mma-builtins.c
@@ -0,0 +1,33 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: -target-feature -mma -fsyntax-only %s -verify
+
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_pair res;
+ __builtin_vsx_assemble_pair(, vc, vc);
+}
+
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp);
+}
+
+void test3(const __vector_pair *vpp, signed long offset, const __vector_pair *vp2) {
+ __vector_pair vp = __builtin_vsx_lxvp(offset, vpp);
+ __builtin_vsx_stxvp(vp, offset, vp2);
+}
+
+void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_xxmtacc(); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+ *((__vector_quad *)resp) = vq;
+}
+
+void test5(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_pmxvf64ger(, vp, vc, 0, 0); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+ *((__vector_quad *)resp) = vq;
+}
+
+
Index: clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
===
--- clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
+++ clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future %s \
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 %s \
+// RUN: -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 %s \
+// RUN: -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 %s \
// RUN: -emit-llvm -o - | FileCheck %s
// CHECK: _Z2f1Pu13__vector_quad
Index: clang/test/CodeGen/ppc-mma-types.c
===
--- clang/test/CodeGen/ppc-mma-types.c
+++ clang/test/CodeGen/ppc-mma-types.c
@@ -1,5 +1,9 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN:
[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units
NeHuang added inline comments. Comment at: clang/test/Sema/ppc-mma-builtins.c:1 +// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \ +// RUN: -target-feature -mma -fsyntax-only %s -verify can you please add `// REQUIRES: powerpc-registered-target` for the ppc specific test? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109599/new/ https://reviews.llvm.org/D109599 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units
kamaub updated this revision to Diff 371954.
kamaub added a comment.
The condition for failing semantic chequing on mma builtins was incorrect,
updating this patch to correctly check the semantics and associated testing.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109599/new/
https://reviews.llvm.org/D109599
Files:
clang/include/clang/Sema/Sema.h
clang/lib/AST/ASTContext.cpp
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/AST/ast-dump-ppc-types.c
clang/test/CodeGen/builtins-ppc-pair-mma.c
clang/test/CodeGen/ppc-mma-types.c
clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
clang/test/Sema/ppc-mma-builtins.c
clang/test/Sema/ppc-pair-mma-types.c
clang/test/Sema/ppc-paired-vector-builtins.c
Index: clang/test/Sema/ppc-paired-vector-builtins.c
===
--- /dev/null
+++ clang/test/Sema/ppc-paired-vector-builtins.c
@@ -0,0 +1,25 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: -target-feature -paired-vector-memops -fsyntax-only %s -verify
+
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_pair res;
+ __builtin_vsx_assemble_pair(, vc, vc); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test3(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
+ __vector_pair vp = __builtin_vsx_lxvp(offset, vpp); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+ __builtin_vsx_stxvp(vp, offset, vp2); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_xxmtacc(); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+ *((__vector_quad *)resp) = vq;
+}
+
+
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN: -target-cpu future %s -verify
+// RUN: -target-cpu pwr10 %s -verify
// The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
// can only be declared in functions and a limited number of operations are
Index: clang/test/Sema/ppc-mma-builtins.c
===
--- /dev/null
+++ clang/test/Sema/ppc-mma-builtins.c
@@ -0,0 +1,32 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: -target-feature -mma -fsyntax-only %s -verify
+
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_pair res;
+ __builtin_vsx_assemble_pair(, vc, vc);
+}
+
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp);
+}
+
+void test3(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
+ __vector_pair vp = __builtin_vsx_lxvp(offset, vpp);
+ __builtin_vsx_stxvp(vp, offset, vp2);
+}
+
+void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_xxmtacc(); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+ *((__vector_quad *)resp) = vq;
+}
+
+void test5(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_pmxvf64ger(, vp, vc, 0, 0); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+ *((__vector_quad *)resp) = vq;
+}
+
+
Index: clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
===
--- clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
+++ clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future %s \
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 %s \
+// RUN: -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 %s \
+// RUN: -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 %s \
// RUN:
[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units
kamaub created this revision. kamaub added reviewers: PowerPC, nemanjai, lei, saghir, stefanp. Herald added subscribers: steven.zhang, shchenz, kbarton. kamaub requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. This patch allows the use of__vector_quad and __vector_pair, PPC MMA builtin types, on all PowerPC 64-bit compilation units. When these types are made available the builtins that use them automatically become available so semantic checking for mma and pair vector memop __builtins is also expanded to ensure these builtin function call are only allowed on Power10 and new architectures. All related test cases are updated to ensure test coverage. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D109599 Files: clang/include/clang/Sema/Sema.h clang/lib/AST/ASTContext.cpp clang/lib/Sema/Sema.cpp clang/lib/Sema/SemaChecking.cpp clang/test/AST/ast-dump-ppc-types.c clang/test/CodeGen/builtins-ppc-pair-mma.c clang/test/CodeGen/ppc-mma-types.c clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp clang/test/Sema/ppc-pair-mma-types.c Index: clang/test/Sema/ppc-pair-mma-types.c === --- clang/test/Sema/ppc-pair-mma-types.c +++ clang/test/Sema/ppc-pair-mma-types.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \ -// RUN: -target-cpu future %s -verify +// RUN: -target-cpu pwr10 %s -verify // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables // can only be declared in functions and a limited number of operations are Index: clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp === --- clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp +++ clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp @@ -1,4 +1,8 @@ -// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future %s \ +// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 %s \ +// RUN: -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 %s \ +// RUN: -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 %s \ // RUN: -emit-llvm -o - | FileCheck %s // CHECK: _Z2f1Pu13__vector_quad Index: clang/test/CodeGen/ppc-mma-types.c === --- clang/test/CodeGen/ppc-mma-types.c +++ clang/test/CodeGen/ppc-mma-types.c @@ -1,5 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future \ +// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 \ +// RUN: -emit-llvm -O3 -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 \ +// RUN: -emit-llvm -O3 -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 \ // RUN: -emit-llvm -O3 -o - %s | FileCheck %s // CHECK-LABEL: @test1( Index: clang/test/CodeGen/builtins-ppc-pair-mma.c === --- clang/test/CodeGen/builtins-ppc-pair-mma.c +++ clang/test/CodeGen/builtins-ppc-pair-mma.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 -emit-llvm %s -o - | FileCheck %s // CHECK-LABEL: @test1( // CHECK-NEXT: entry: Index: clang/test/AST/ast-dump-ppc-types.c === --- clang/test/AST/ast-dump-ppc-types.c +++ clang/test/AST/ast-dump-ppc-types.c @@ -1,13 +1,9 @@ -// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \ +// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \ // RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s -// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \ -// RUN: -target-feature -mma -ast-dump %s | FileCheck %s \ -// RUN: --check-prefix=CHECK-NO-MMA -// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \ -// RUN: -target-feature -paired-vector-memops -ast-dump %s | FileCheck %s \ -// RUN: --check-prefix=CHECK-NO-PAIRED // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 \ -// RUN: -ast-dump %s | FileCheck %s --check-prefix=CHECK-PWR9 +// RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr8 \ +// RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s // RUN: %clang_cc1 -triple x86_64-unknown-unknown -ast-dump %s | FileCheck %s \ // RUN: --check-prefix=CHECK-X86_64 // RUN: %clang_cc1 -triple
