[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.
eopXD added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:180 + // The nomask intrinsic IR have the passthru operand. + bit HasNoMaskPassThru = false; eopXD wrote: > Nit: V-spec prefers to call instructions without masking operands "unmasked > instructions"? Maybe a RFC patch later? I mean an NFC patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117989/new/ https://reviews.llvm.org/D117989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.
eopXD added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:180 + // The nomask intrinsic IR have the passthru operand. + bit HasNoMaskPassThru = false; Nit: V-spec prefers to call instructions without masking operands "unmasked instructions"? Maybe a RFC patch later? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117989/new/ https://reviews.llvm.org/D117989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGb7847199044e: [RISCV] Add the passthru operand for RVV nomask binary intrinsics. (authored by khchen). Herald added a subscriber: qcolombet. Changed prior to commit: https://reviews.llvm.org/D117989?vs=408696=409119#toc Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117989/new/ https://reviews.llvm.org/D117989 Files: clang/include/clang/Basic/riscv_vector.td clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul-eew64.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul-eew64.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c
[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.
craig.topper added a comment. LGTM other than what I think is an unnecessary include. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:15 #include "RISCVISelLowering.h" +#include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVMatInt.h" This file is included in RISCV.h can we remove this change? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117989/new/ https://reviews.llvm.org/D117989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.
craig.topper added inline comments.
Comment at: clang/include/clang/Basic/riscv_vector.td:181
+ // The nomask intrinsic IR have the passthru operand.
+ bit HasNoMaskPolicy = false;
+
Should this be `HasNoMaskPassThru` rather than `Policy`?
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4733
} else {
- Vec = DAG.getNode(RISCVISD::VSLIDE1DOWN_VL, DL, I32VT, Vec, ScalarLo,
-I32Mask, I32VL);
- Vec = DAG.getNode(RISCVISD::VSLIDE1DOWN_VL, DL, I32VT, Vec, ScalarHi,
-I32Mask, I32VL);
+ // TODO Those VSLDIE1 could be TAMA because we use vmerge to select
maskedoff
+ SDValue Undef = DAG.getUNDEF(I32VT);
VSLDIE1 -> VSLIDE1
Fix the clang-format warning
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4760
+if (MaskedOff.isUndef()) {
+ assert(Policy == (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC) &&
+ "Invalid policy, undef maskedoff need to have tail and mask "
I don't think you can assert the policy here. The mask can be folded to undef
without the user knowing.
Comment at: llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll:56
+
+; Fallback vslide1 to mask undisturbed untill InsertVSETVLI supports mask
agnostic.
+define
@intrinsic_vslide1down_mask_tuma_vx_nxv1i64_nxv1i64_i64( %0,
%1, i64 %2, %3, i32 %4) nounwind {
untill -> until
Comment at: llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll:78
+
+; Fallback vslide1 to mask undisturbed untill InsertVSETVLI supports mask
agnostic.
+define
@intrinsic_vslide1down_mask_tama_vx_nxv1i64_nxv1i64_i64( %0,
i64 %1, %2, i32 %3) nounwind {
untill -> until
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[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.
khchen added a comment. Gentle ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117989/new/ https://reviews.llvm.org/D117989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.
craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4503
case Intrinsic::riscv_vslide1down_mask: {
// We need to special case these when the scalar is larger than XLen.
unsigned NumOps = Op.getNumOperands();
Are we dropping the policy operand for masked intrinsics here?
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4539
+if (!IsMasked) {
+ SDValue passthru = DAG.getBitcast(I32VT, Op.getOperand(1));
+ if (IntNo == Intrinsic::riscv_vslide1up) {
Capitalize variable name
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[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.
rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. Looks reasonable to me. Thans @khchen! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117989/new/ https://reviews.llvm.org/D117989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
