[PATCH] D120976: [AMDGPU] Add llvm.amdgcn.s.setprio intrinsic
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG62bcfcb5a588: [AMDGPU] Add llvm.amdgcn.s.setprio intrinsic (authored by kerbowa). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120976/new/ https://reviews.llvm.org/D120976 Files: clang/include/clang/Basic/BuiltinsAMDGPU.def clang/test/CodeGenOpenCL/builtins-amdgcn.cl clang/test/SemaOpenCL/builtins-amdgcn-error.cl llvm/include/llvm/IR/IntrinsicsAMDGPU.td llvm/lib/Target/AMDGPU/SOPInstructions.td llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll Index: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll === --- /dev/null +++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll @@ -0,0 +1,49 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx90a -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -march=amdgcn -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -global-isel -march=amdgcn -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx90a -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s + +declare void @llvm.amdgcn.s.setprio(i16) #0 + +define void @test_llvm_amdgcn_s_setprio() #0 { +; GFX9-LABEL: test_llvm_amdgcn_s_setprio: +; GFX9: ; %bb.0: +; GFX9-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] +; GFX9-NEXT:s_setprio 0 ; encoding: [0x00,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio 2 ; encoding: [0x02,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio 3 ; encoding: [0x03,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio 10 ; encoding: [0x0a,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio -1 ; encoding: [0xff,0xff,0x8f,0xbf] +; GFX9-NEXT:s_setprio 0 ; encoding: [0x00,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio -1 ; encoding: [0xff,0xff,0x8f,0xbf] +; GFX9-NEXT:s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] +; +; SI-LABEL: test_llvm_amdgcn_s_setprio: +; SI: ; %bb.0: +; SI-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] +; SI-NEXT:s_setprio 0 ; encoding: [0x00,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio 2 ; encoding: [0x02,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio 3 ; encoding: [0x03,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio 10 ; encoding: [0x0a,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio -1 ; encoding: [0xff,0xff,0x8f,0xbf] +; SI-NEXT:s_setprio 0 ; encoding: [0x00,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio -1 ; encoding: [0xff,0xff,0x8f,0xbf] +; SI-NEXT:s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] + call void @llvm.amdgcn.s.setprio(i16 0) + call void @llvm.amdgcn.s.setprio(i16 1) + call void @llvm.amdgcn.s.setprio(i16 2) + call void @llvm.amdgcn.s.setprio(i16 3) + call void @llvm.amdgcn.s.setprio(i16 10) + call void @llvm.amdgcn.s.setprio(i16 65535) + call void @llvm.amdgcn.s.setprio(i16 65536) + call void @llvm.amdgcn.s.setprio(i16 65537) + call void @llvm.amdgcn.s.setprio(i16 -1) + ret void +} + +attributes #0 = { nounwind } Index: llvm/lib/Target/AMDGPU/SOPInstructions.td === --- llvm/lib/Target/AMDGPU/SOPInstructions.td +++ llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1278,7 +1278,10 @@ let hasSideEffects = 1; } -def S_SETPRIO : SOPP_Pseudo <"s_setprio" , (ins i16imm:$simm16), "$simm16">; +def S_SETPRIO : SOPP_Pseudo <"s_setprio", (ins i16imm:$simm16), "$simm16", + [(int_amdgcn_s_setprio timm:$simm16)]> { + let hasSideEffects = 1; +} let Uses = [EXEC, M0] in { // FIXME: Should this be mayLoad+mayStore? Index: llvm/include/llvm/IR/IntrinsicsAMDGPU.td === --- llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -1329,6 +1329,11 @@ Intrinsic<[], [llvm_i32_ty], [ImmArg>, IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; +def int_amdgcn_s_setprio : + GCCBuiltin<"__builtin_amdgcn_s_setprio">, + Intrinsic<[], [llvm_i16_ty], [ImmArg>, IntrNoMem, +IntrHasSideEffects, IntrWillReturn]>; + def int_amdgcn_s_getreg : GCCBuiltin<"__builtin_amdgcn_s_getreg">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty], Index: clang/test/SemaOpenCL/builtins-amdgcn-error.cl === --- clang/test/SemaOpenCL/builtins-amdgcn-error.cl +++ clang/test/SemaOpenCL/builtins-amdgcn-error.cl
[PATCH] D120976: [AMDGPU] Add llvm.amdgcn.s.setprio intrinsic
kerbowa updated this revision to Diff 414559. kerbowa added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Add clang builtin and tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120976/new/ https://reviews.llvm.org/D120976 Files: clang/include/clang/Basic/BuiltinsAMDGPU.def clang/test/CodeGenOpenCL/builtins-amdgcn.cl clang/test/SemaOpenCL/builtins-amdgcn-error.cl llvm/include/llvm/IR/IntrinsicsAMDGPU.td llvm/lib/Target/AMDGPU/SOPInstructions.td llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll Index: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll === --- /dev/null +++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll @@ -0,0 +1,49 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx90a -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -march=amdgcn -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -global-isel -march=amdgcn -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx90a -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s + +declare void @llvm.amdgcn.s.setprio(i16) #0 + +define void @test_llvm_amdgcn_s_setprio() #0 { +; GFX9-LABEL: test_llvm_amdgcn_s_setprio: +; GFX9: ; %bb.0: +; GFX9-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] +; GFX9-NEXT:s_setprio 0 ; encoding: [0x00,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio 2 ; encoding: [0x02,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio 3 ; encoding: [0x03,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio 10 ; encoding: [0x0a,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio -1 ; encoding: [0xff,0xff,0x8f,0xbf] +; GFX9-NEXT:s_setprio 0 ; encoding: [0x00,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf] +; GFX9-NEXT:s_setprio -1 ; encoding: [0xff,0xff,0x8f,0xbf] +; GFX9-NEXT:s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] +; +; SI-LABEL: test_llvm_amdgcn_s_setprio: +; SI: ; %bb.0: +; SI-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] +; SI-NEXT:s_setprio 0 ; encoding: [0x00,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio 2 ; encoding: [0x02,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio 3 ; encoding: [0x03,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio 10 ; encoding: [0x0a,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio -1 ; encoding: [0xff,0xff,0x8f,0xbf] +; SI-NEXT:s_setprio 0 ; encoding: [0x00,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf] +; SI-NEXT:s_setprio -1 ; encoding: [0xff,0xff,0x8f,0xbf] +; SI-NEXT:s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] + call void @llvm.amdgcn.s.setprio(i16 0) + call void @llvm.amdgcn.s.setprio(i16 1) + call void @llvm.amdgcn.s.setprio(i16 2) + call void @llvm.amdgcn.s.setprio(i16 3) + call void @llvm.amdgcn.s.setprio(i16 10) + call void @llvm.amdgcn.s.setprio(i16 65535) + call void @llvm.amdgcn.s.setprio(i16 65536) + call void @llvm.amdgcn.s.setprio(i16 65537) + call void @llvm.amdgcn.s.setprio(i16 -1) + ret void +} + +attributes #0 = { nounwind } Index: llvm/lib/Target/AMDGPU/SOPInstructions.td === --- llvm/lib/Target/AMDGPU/SOPInstructions.td +++ llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1278,7 +1278,10 @@ let hasSideEffects = 1; } -def S_SETPRIO : SOPP_Pseudo <"s_setprio" , (ins i16imm:$simm16), "$simm16">; +def S_SETPRIO : SOPP_Pseudo <"s_setprio", (ins i16imm:$simm16), "$simm16", + [(int_amdgcn_s_setprio timm:$simm16)]> { + let hasSideEffects = 1; +} let Uses = [EXEC, M0] in { // FIXME: Should this be mayLoad+mayStore? Index: llvm/include/llvm/IR/IntrinsicsAMDGPU.td === --- llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -1329,6 +1329,11 @@ Intrinsic<[], [llvm_i32_ty], [ImmArg>, IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; +def int_amdgcn_s_setprio : + GCCBuiltin<"__builtin_amdgcn_s_setprio">, + Intrinsic<[], [llvm_i16_ty], [ImmArg>, IntrNoMem, +IntrHasSideEffects, IntrWillReturn]>; + def int_amdgcn_s_getreg : GCCBuiltin<"__builtin_amdgcn_s_getreg">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty], Index: clang/test/SemaOpenCL/builtins-amdgcn-error.cl === --- clang/test/SemaOpenCL/builtins-amdgcn-error.cl +++ clang/test/SemaOpenCL/builtins-amdgcn-error.cl @@ -54,6 +54,12 @@ __builtin_amdgcn_s_decperflevel(x);