[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

2022-10-06 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD added a comment.

Hi @fhahn,

After a second thought, I think posting a clear RFC [0] to the community that 
defines the
problem and goal this patch tries to achieve so the community is notified of 
such change
is a better approach than directly updating this patch. Please consider to drop 
by and
give a review.

Thank you very much for your time.

[0] [[RFC] Enabling LoopVectorizer for vectorization width of 
1](https://discourse.llvm.org/t/rfc-enabling-loopvectorizer-for-vectorization-width-of-1/65769)

Regards,

eop Chen


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

2022-10-06 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD added a comment.

@fhahn Thank you very much for the review, backward compatibility is a good 
point. I will update the revision.


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

2022-10-06 Thread Florian Hahn via Phabricator via cfe-commits 
fhahn added a comment.

> Adding this metadata allows {loop.vectorize.enable, false} to be used without 
> disabling the whole pass.

Could you please describe the behavior in more detail here? The new metadata 
should also be documented in `LangRef`, the new pragma in 
https://clang.llvm.org/docs/LanguageExtensions.htm.

Will this change the existing behavior if only `llvm.loop.vectorize.enable == 
false`? To preserve backwards compatibility, I think the behavior shouldn;t 
change unless `llvm.loop.interleave.enable` is provided.

Also, shouldn't `#pragma clang loop vectorize(disable) interleave(enable)` be 
equivalent to `#pragma clang loop vectorize(enable) vectorize_width(1)`?




Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:2142
 
-  if (Hints.getInterleave() > 1) {
+  if (Hints.getInterleaveForce()) {
 // TODO: Interleave support is future work.

Will `getInterleaveForce()` return `ENABLED` if an interleave count > 1 is set 
through metadata?



Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:3013
   assert(!(SCEVCheckBlock->getParent()->hasOptSize() ||
-   (OptForSizeBasedOnProfile &&
-Cost->Hints->getForce() != LoopVectorizeHints::FK_Enabled)) &&
+   (OptForSizeBasedOnProfile && Cost->Hints->getVectorizationForce() !=
+LoopVectorizeHints::FK_Enabled)) &&

Should this check interleaving or vectorization forced?


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

2022-10-06 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD added a comment.

Gentle ping, thank you ;)


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

2022-09-27 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 463299.
eopXD added a comment.

Fix grammar error in comment.


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Files:
  clang/lib/CodeGen/CGLoopInfo.cpp
  clang/lib/CodeGen/CGLoopInfo.h
  clang/test/CodeGenCXX/pragma-loop-predicate.cpp
  clang/test/CodeGenCXX/pragma-loop-safety.cpp
  clang/test/CodeGenCXX/pragma-loop.cpp
  llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
  llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  
llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
  llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
  llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
  
llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
  llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
  llvm/test/Transforms/LoopVectorize/no_switch.ll
  llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll
  llvm/test/Transforms/LoopVectorize/nounroll.ll
  llvm/test/Transforms/LoopVectorize/optsize.ll
  llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
  llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
  llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
  llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
  llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll

Index: llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
@@ -196,5 +196,6 @@
 exit:
   ret void
 }
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
@@ -68,5 +68,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
@@ -77,5 +77,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
@@ -69,6 +69,7 @@
   ret void
 }
 
-!1 = distinct !{!1, !2, !3}
+!1 = distinct !{!1, !2, !3, !4}
 !2 = !{!"llvm.loop.vectorize.width", i32 4}
 !3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
@@ -43,5 +43,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
===
--- llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
+++ llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
@@ -2,7 +2,7 @@
 ; REQUIRES: asserts
 
 ; CHECK: LV: Checking a loop in 'foo'
-; CHECK:

[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

2022-09-27 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD marked an inline comment as done.
eopXD added a comment.

After this patch, we can remove setVectorizeWidth(1) and setInterleaveCount(1) 
when vectorize(disable) and interleave(disable) is specified. For now it is not 
removed to keep the patch limited and simple enough.


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

2022-09-27 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 463261.
eopXD added a comment.

Update comment.


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Files:
  clang/lib/CodeGen/CGLoopInfo.cpp
  clang/lib/CodeGen/CGLoopInfo.h
  clang/test/CodeGenCXX/pragma-loop-predicate.cpp
  clang/test/CodeGenCXX/pragma-loop-safety.cpp
  clang/test/CodeGenCXX/pragma-loop.cpp
  llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
  llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  
llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
  llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
  llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
  
llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
  llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
  llvm/test/Transforms/LoopVectorize/no_switch.ll
  llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll
  llvm/test/Transforms/LoopVectorize/nounroll.ll
  llvm/test/Transforms/LoopVectorize/optsize.ll
  llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
  llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
  llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
  llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
  llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll

Index: llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
@@ -196,5 +196,6 @@
 exit:
   ret void
 }
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
@@ -68,5 +68,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
@@ -77,5 +77,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
@@ -69,6 +69,7 @@
   ret void
 }
 
-!1 = distinct !{!1, !2, !3}
+!1 = distinct !{!1, !2, !3, !4}
 !2 = !{!"llvm.loop.vectorize.width", i32 4}
 !3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
@@ -43,5 +43,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
===
--- llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
+++ llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
@@ -2,7 +2,7 @@
 ; REQUIRES: asserts
 
 ; CHECK: LV: Checking a loop in 'foo'
-; CHECK: LV: Loop hints:

[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

2022-09-27 Thread Michael Berg via Phabricator via cfe-commits 
mcberg2021 added inline comments.



Comment at: clang/lib/CodeGen/CGLoopInfo.cpp:673
+setInterleaveEnable(false);
 setInterleaveCount(1);
 break;

Can you update the comments on lines: 665 and 671 as they both need update.


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

2022-09-27 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD added a comment.

Please feel free to add appropriate reviewer to this patch.


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

2022-09-27 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD created this revision.
eopXD added reviewers: sdesmalen, paulwalker-arm, fhahn, reames, hfinkel.
Herald added subscribers: frasercrmck, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, 
asb, hiraditya.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

Adding this metadata allows {loop.vectorize.enable, false} to be used
without disabling the whole pass.


Repository:
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https://reviews.llvm.org/D134745

Files:
  clang/lib/CodeGen/CGLoopInfo.cpp
  clang/lib/CodeGen/CGLoopInfo.h
  clang/test/CodeGenCXX/pragma-loop-predicate.cpp
  clang/test/CodeGenCXX/pragma-loop-safety.cpp
  clang/test/CodeGenCXX/pragma-loop.cpp
  llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
  llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  
llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
  llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
  llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
  
llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
  llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
  llvm/test/Transforms/LoopVectorize/no_switch.ll
  llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll
  llvm/test/Transforms/LoopVectorize/nounroll.ll
  llvm/test/Transforms/LoopVectorize/optsize.ll
  llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
  llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
  llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
  llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
  llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll

Index: llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
@@ -196,5 +196,6 @@
 exit:
   ret void
 }
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
@@ -68,5 +68,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
@@ -77,5 +77,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
@@ -69,6 +69,7 @@
   ret void
 }
 
-!1 = distinct !{!1, !2, !3}
+!1 = distinct !{!1, !2, !3, !4}
 !2 = !{!"llvm.loop.vectorize.width", i32 4}
 !3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
@@ -43,5 +43,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 =