This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4d2536c82fc4: [RISCV] Enable more builtin for zvfhmin
without zvfh (authored by jacquesguan).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D151869/new/
https://reviews.llvm.org/D151869
Files:
clang/include/clang/Basic/riscv_vector.td
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -9,7 +9,7 @@
// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
// CHECK-ZVFHMIN-NEXT: entry:
-// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, [[SRC:%.*]], i64 7, i64 [[VL:%.*]])
// CHECK-ZVFHMIN-NEXT:ret [[TMP0]]
//
vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
@@ -25,3 +25,192 @@
vfloat32m2_t test_vfwcvt_f_f_v_f16m1(vfloat16m1_t src, size_t vl) {
return __riscv_vfwcvt_f(src, vl);
}
+
+// CHECK-ZVFHMIN-LABEL: @test_vle16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call @llvm.riscv.vle.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret [[TMP0]]
+//
+vfloat16m1_t test_vle16_v_f16m1(const _Float16 *base, size_t vl) {
+ return __riscv_vle16_v_f16m1(base, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vse.nxv4f16.i64( [[VALUE:%.*]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vse16_v_f16m1(_Float16 *base, vfloat16m1_t value, size_t vl) {
+ return __riscv_vse16_v_f16m1(base, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vlse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call @llvm.riscv.vlse.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret [[TMP0]]
+//
+vfloat16m1_t test_vlse16_v_f16m1(const _Float16 *base, ptrdiff_t bstride, size_t vl) {
+ return __riscv_vlse16_v_f16m1(base, bstride, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsse.nxv4f16.i64( [[VALUE:%.*]], ptr [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsse16_v_f16m1(_Float16 *base, ptrdiff_t bstride, vfloat16m1_t value, size_t vl) {
+ return __riscv_vsse16_v_f16m1(base, bstride, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vluxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv4f16.nxv4i32.i64( poison, ptr [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret [[TMP0]]
+//
+vfloat16m1_t test_vluxei32_v_f16m1(const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+ return __riscv_vluxei32_v_f16m1(base, bindex, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsuxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsuxei.nxv4f16.nxv4i32.i64( [[VALUE:%.*]], ptr [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsuxei32_v_f16m1(_Float16 *base, vuint32m2_t bindex, vfloat16m1_t value, size_t vl) {
+ return __riscv_vsuxei32_v_f16m1(base, bindex, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vloxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv4f16.nxv4i32.i64( poison, ptr [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret [[TMP0]]
+//
+vfloat16m1_t test_vloxei32_v_f16m1(const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+ return __riscv_vloxei32_v_f16m1(base, bindex, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsoxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsoxei.nxv4f16.nxv4i32.i64( [[VALUE:%.*]], ptr [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsoxei32_v_f16m1(_Float16 *base, vuint32m2_t bindex, vfloat16m1_t value, size_t vl) {
+ return __riscv_vsoxei32_v_f16m1(base, bindex, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vle16ff_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:[[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0
+// CHECK-ZVFHMIN-NEXT:[[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1
