ManuelJBrito planned changes to this revision.
ManuelJBrito added a comment.
Hello @aqjune thanks for the comments !! Some users of
SimplifyDemandedVectorElts might need some more tweaking to prevent regressions
for the cases you noted. I'll work on this as soon as I can!
Repository:
rG
aqjune added inline comments.
Comment at: llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:1653
- if (ShMask[I] >= 0) {
-assert(ShMask[I] < (int)NumElts && "Not expecting narrowing shuffle");
Constant *NewCElt = NewVecC[ShMask[I]];
aqjune added a comment.
Hi, thanks for your hard work!
Comment at: llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:1653
- if (ShMask[I] >= 0) {
-assert(ShMask[I] < (int)NumElts && "Not expecting narrowing shuffle");
Constant *NewCElt =
ManuelJBrito added a comment.
Herald added a subscriber: wangpc.
ping :)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D152658/new/
https://reviews.llvm.org/D152658
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ManuelJBrito added a comment.
Ping
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D152658/new/
https://reviews.llvm.org/D152658
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ManuelJBrito added inline comments.
Comment at: llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp:3102-3105
case Intrinsic::x86_sse4a_extrqi:
case Intrinsic::x86_sse4a_insertq:
case Intrinsic::x86_sse4a_insertqi:
+PoisonElts.setHighBits(VWidth / 2);
nlopes added inline comments.
Comment at: llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp:3102-3105
case Intrinsic::x86_sse4a_extrqi:
case Intrinsic::x86_sse4a_insertq:
case Intrinsic::x86_sse4a_insertqi:
+PoisonElts.setHighBits(VWidth / 2);
this
