[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

[Craig Topper via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa64b3e92c7cb: [RISCV] Re-define sha256, Zksed, and Zksh 
intrinsics to use i32 types. (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154647/new/

https://reviews.llvm.org/D154647

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
  llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll

Index: llvm/test/CodeGen/RISCV/sextw-removal.ll
===
--- llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1319,13 +1319,11 @@
 ; NOREMOVAL-NEXT:addi sp, sp, 32
 ; NOREMOVAL-NEXT:ret
 bb:
-  %sext = sext i32 %arg1 to i64
-  %i = call i64 @llvm.riscv.sha256sig0.i64(i64 %sext)
-  %trunc = trunc i64 %i to i32
+  %i = call i32 @llvm.riscv.sha256sig0(i32 %arg1)
   br label %bb2
 
 bb2:  ; preds = %bb2, %bb
-  %i3 = phi i32 [ %trunc, %bb ], [ %i5, %bb2 ]
+  %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ]
   %i4 = tail call signext i32 @bar(i32 signext %i3)
   %i5 = shl i32 %i3, %arg1
   %i6 = icmp eq i32 %i4, 0
@@ -1334,7 +1332,7 @@
 bb7:  ; preds = %bb2
   ret void
 }
-declare i64 @llvm.riscv.sha256sig0.i64(i64)
+declare i32 @llvm.riscv.sha256sig0(i32)
 
 ; The type promotion of %7 forms a sext_inreg, but %7 and %6 are combined to
 ; form a sh2add. This leaves behind a sext.w that isn't needed.
Index: llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksh -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSH
 
-declare i64 @llvm.riscv.sm3p0.i64(i64);
+declare i32 @llvm.riscv.sm3p0(i32);
 
-define i64 @sm3p0_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p0_i64:
+define signext i32 @sm3p0_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p0_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p0 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p0.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p0(i32 signext %a)
+  ret i32 %val
 }
 
-declare i64 @llvm.riscv.sm3p1.i64(i64);
+declare i32 @llvm.riscv.sm3p1(i32);
 
-define i64 @sm3p1_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p1_i64:
+define signext i32 @sm3p1_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p1_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p1 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p1.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p1(i32 signext %a)
+  ret i32 %val
 }
Index: llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksed -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSED
 
-declare i64 @llvm.riscv.sm4ks.i64(i64, i64, i32);
+declare i32 @llvm.riscv.sm4ks(i32, i32, i32);
 
-define i64 @sm4ks_i64(i64 %a, i64 %b) nounwind {
-; RV64ZKSED-LABEL: sm4ks_i64:
+define signext i32 @sm4ks_i32(i32 signext %a, i32 signext %b) nounwind {
+; RV64ZKSED-LABEL: sm4ks_i32:
 ; RV64ZKSED:   # %bb.0:
-; RV64ZKSED-NEXT:sm4ks a0, a0, a1, 0
+; RV64ZKSED-NEXT:sm4ks a0, a0, a1, 2
 ; RV64ZKSED-NEXT:ret
-  %val = call i64 @llvm.riscv.sm4ks.i64(i64 %a, i64 %b, i32 0)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm4ks(i32 %a, i32 %b, i32 2)
+  ret i32 %val
 }
 

[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

[Xinlong Wu via Phabricator via cfe-commits]

VincentWu accepted this revision.
VincentWu added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 540716.
craig.topper added a comment.

Merge identical tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
  llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll

Index: llvm/test/CodeGen/RISCV/sextw-removal.ll
===
--- llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1319,13 +1319,11 @@
 ; NOREMOVAL-NEXT:addi sp, sp, 32
 ; NOREMOVAL-NEXT:ret
 bb:
-  %sext = sext i32 %arg1 to i64
-  %i = call i64 @llvm.riscv.sha256sig0.i64(i64 %sext)
-  %trunc = trunc i64 %i to i32
+  %i = call i32 @llvm.riscv.sha256sig0(i32 %arg1)
   br label %bb2
 
 bb2:  ; preds = %bb2, %bb
-  %i3 = phi i32 [ %trunc, %bb ], [ %i5, %bb2 ]
+  %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ]
   %i4 = tail call signext i32 @bar(i32 signext %i3)
   %i5 = shl i32 %i3, %arg1
   %i6 = icmp eq i32 %i4, 0
@@ -1334,7 +1332,7 @@
 bb7:  ; preds = %bb2
   ret void
 }
-declare i64 @llvm.riscv.sha256sig0.i64(i64)
+declare i32 @llvm.riscv.sha256sig0(i32)
 
 ; The type promotion of %7 forms a sext_inreg, but %7 and %6 are combined to
 ; form a sh2add. This leaves behind a sext.w that isn't needed.
Index: llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksh -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSH
 
-declare i64 @llvm.riscv.sm3p0.i64(i64);
+declare i32 @llvm.riscv.sm3p0(i32);
 
-define i64 @sm3p0_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p0_i64:
+define signext i32 @sm3p0_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p0_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p0 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p0.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p0(i32 signext %a)
+  ret i32 %val
 }
 
-declare i64 @llvm.riscv.sm3p1.i64(i64);
+declare i32 @llvm.riscv.sm3p1(i32);
 
-define i64 @sm3p1_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p1_i64:
+define signext i32 @sm3p1_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p1_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p1 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p1.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p1(i32 signext %a)
+  ret i32 %val
 }
Index: llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksed -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSED
 
-declare i64 @llvm.riscv.sm4ks.i64(i64, i64, i32);
+declare i32 @llvm.riscv.sm4ks(i32, i32, i32);
 
-define i64 @sm4ks_i64(i64 %a, i64 %b) nounwind {
-; RV64ZKSED-LABEL: sm4ks_i64:
+define signext i32 @sm4ks_i32(i32 signext %a, i32 signext %b) nounwind {
+; RV64ZKSED-LABEL: sm4ks_i32:
 ; RV64ZKSED:   # %bb.0:
-; RV64ZKSED-NEXT:sm4ks a0, a0, a1, 0
+; RV64ZKSED-NEXT:sm4ks a0, a0, a1, 2
 ; RV64ZKSED-NEXT:ret
-  %val = call i64 @llvm.riscv.sm4ks.i64(i64 %a, i64 %b, i32 0)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm4ks(i32 %a, i32 %b, i32 2)
+  ret i32 %val
 }
 
-declare i64 @llvm.riscv.sm4ed.i64(i64, i64, i32);
+declare i32 @llvm.riscv.sm4ed(i32, i32, i32);
 
-define i64 @sm4ed_i64(i64 %a, i64 %b) nounwind {
-; 

[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 540714.
craig.topper added a comment.

Rebase. Will merge tests next.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154647/new/

https://reviews.llvm.org/D154647

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
  llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll

Index: llvm/test/CodeGen/RISCV/sextw-removal.ll
===
--- llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1319,13 +1319,11 @@
 ; NOREMOVAL-NEXT:addi sp, sp, 32
 ; NOREMOVAL-NEXT:ret
 bb:
-  %sext = sext i32 %arg1 to i64
-  %i = call i64 @llvm.riscv.sha256sig0.i64(i64 %sext)
-  %trunc = trunc i64 %i to i32
+  %i = call i32 @llvm.riscv.sha256sig0(i32 %arg1)
   br label %bb2
 
 bb2:  ; preds = %bb2, %bb
-  %i3 = phi i32 [ %trunc, %bb ], [ %i5, %bb2 ]
+  %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ]
   %i4 = tail call signext i32 @bar(i32 signext %i3)
   %i5 = shl i32 %i3, %arg1
   %i6 = icmp eq i32 %i4, 0
@@ -1334,7 +1332,7 @@
 bb7:  ; preds = %bb2
   ret void
 }
-declare i64 @llvm.riscv.sha256sig0.i64(i64)
+declare i32 @llvm.riscv.sha256sig0(i32)
 
 ; The type promotion of %7 forms a sext_inreg, but %7 and %6 are combined to
 ; form a sh2add. This leaves behind a sext.w that isn't needed.
Index: llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksh -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSH
 
-declare i64 @llvm.riscv.sm3p0.i64(i64);
+declare i32 @llvm.riscv.sm3p0(i32);
 
-define i64 @sm3p0_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p0_i64:
+define signext i32 @sm3p0_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p0_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p0 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p0.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p0(i32 signext %a)
+  ret i32 %val
 }
 
-declare i64 @llvm.riscv.sm3p1.i64(i64);
+declare i32 @llvm.riscv.sm3p1(i32);
 
-define i64 @sm3p1_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p1_i64:
+define signext i32 @sm3p1_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p1_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p1 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p1.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p1(i32 signext %a)
+  ret i32 %val
 }
Index: llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksed -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSED
 
-declare i64 @llvm.riscv.sm4ks.i64(i64, i64, i32);
+declare i32 @llvm.riscv.sm4ks(i32, i32, i32);
 
-define i64 @sm4ks_i64(i64 %a, i64 %b) nounwind {
-; RV64ZKSED-LABEL: sm4ks_i64:
+define signext i32 @sm4ks_i32(i32 signext %a, i32 signext %b) nounwind {
+; RV64ZKSED-LABEL: sm4ks_i32:
 ; RV64ZKSED:   # %bb.0:
-; RV64ZKSED-NEXT:sm4ks a0, a0, a1, 0
+; RV64ZKSED-NEXT:sm4ks a0, a0, a1, 2
 ; RV64ZKSED-NEXT:ret
-  %val = call i64 @llvm.riscv.sm4ks.i64(i64 %a, i64 %b, i32 0)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm4ks(i32 %a, i32 %b, i32 2)
+  ret i32 %val
 }
 
-declare i64 @llvm.riscv.sm4ed.i64(i64, i64, i32);
+declare i32 @llvm.riscv.sm4ed(i32, i32, i32);
 
-define i64 @sm4ed_i64(i64 %a, i64 %b) nounwind {
-; RV64ZKSED-LABEL: sm4ed_i64:
+define signext i32 @sm4ed_i32(i32 signext %a, i32 signext %b) nounwind {

[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

[Xinlong Wu via Phabricator via cfe-commits]

VincentWu added a comment.

What about combine the rv32 and rv64 into one file, since they are entire same.


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[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

[Xinlong Wu via Phabricator via cfe-commits]

VincentWu accepted this revision.
VincentWu added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
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[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Ping


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[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 538239.
craig.topper added a comment.

Rebase and add the missing autoupgrade tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154647/new/

https://reviews.llvm.org/D154647

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
  llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll

Index: llvm/test/CodeGen/RISCV/sextw-removal.ll
===
--- llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1319,13 +1319,11 @@
 ; NOREMOVAL-NEXT:addi sp, sp, 32
 ; NOREMOVAL-NEXT:ret
 bb:
-  %sext = sext i32 %arg1 to i64
-  %i = call i64 @llvm.riscv.sha256sig0.i64(i64 %sext)
-  %trunc = trunc i64 %i to i32
+  %i = call i32 @llvm.riscv.sha256sig0(i32 %arg1)
   br label %bb2
 
 bb2:  ; preds = %bb2, %bb
-  %i3 = phi i32 [ %trunc, %bb ], [ %i5, %bb2 ]
+  %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ]
   %i4 = tail call signext i32 @bar(i32 signext %i3)
   %i5 = shl i32 %i3, %arg1
   %i6 = icmp eq i32 %i4, 0
@@ -1334,7 +1332,7 @@
 bb7:  ; preds = %bb2
   ret void
 }
-declare i64 @llvm.riscv.sha256sig0.i64(i64)
+declare i32 @llvm.riscv.sha256sig0(i32)
 
 ; The type promotion of %7 forms a sext_inreg, but %7 and %6 are combined to
 ; form a sh2add. This leaves behind a sext.w that isn't needed.
Index: llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksh -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSH
 
-declare i64 @llvm.riscv.sm3p0.i64(i64);
+declare i32 @llvm.riscv.sm3p0(i32);
 
-define i64 @sm3p0_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p0_i64:
+define signext i32 @sm3p0_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p0_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p0 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p0.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p0(i32 signext %a)
+  ret i32 %val
 }
 
-declare i64 @llvm.riscv.sm3p1.i64(i64);
+declare i32 @llvm.riscv.sm3p1(i32);
 
-define i64 @sm3p1_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p1_i64:
+define signext i32 @sm3p1_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p1_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p1 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p1.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p1(i32 signext %a)
+  ret i32 %val
 }
Index: llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksed -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSED
 
-declare i64 @llvm.riscv.sm4ks.i64(i64, i64, i32);
+declare i32 @llvm.riscv.sm4ks(i32, i32, i32);
 
-define i64 @sm4ks_i64(i64 %a, i64 %b) nounwind {
-; RV64ZKSED-LABEL: sm4ks_i64:
+define signext i32 @sm4ks_i32(i32 signext %a, i32 signext %b) nounwind {
+; RV64ZKSED-LABEL: sm4ks_i32:
 ; RV64ZKSED:   # %bb.0:
-; RV64ZKSED-NEXT:sm4ks a0, a0, a1, 0
+; RV64ZKSED-NEXT:sm4ks a0, a0, a1, 2
 ; RV64ZKSED-NEXT:ret
-  %val = call i64 @llvm.riscv.sm4ks.i64(i64 %a, i64 %b, i32 0)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm4ks(i32 %a, i32 %b, i32 2)
+  ret i32 %val
 }
 
-declare i64 @llvm.riscv.sm4ed.i64(i64, i64, i32);
+declare i32 @llvm.riscv.sm4ed(i32, i32, i32);
 
-define i64 @sm4ed_i64(i64 %a, i64 %b) nounwind {
-; RV64ZKSED-LABEL: sm4ed_i64:
+define signext i32 @sm4ed_i32(i32 signext %a, i32 signext 

[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
craig.topper added reviewers: asb, VincentWu, kito-cheng, reames.
Herald added subscribers: jobnoorman, luke, vkmr, frasercrmck, luismarques, 
apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: wangpc, eopXD, MaskRay.
Herald added projects: clang, LLVM.

Previously we returned i32 on RV32 and i64 on RV64. The instructions
only consume 32 bits and only produce 32 bits. For RV64, the result
is sign extended to 64 bits like *W instructions.

This patch removes this detail from the interface to improve
portability and consistency. This matches the proposal for scalar
intrinsics here https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

I've included IR autoupgrade support as well.

I'll be doing this for other builtins/intrinsics that currently use
'long' in other patches.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154647

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
  llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll

Index: llvm/test/CodeGen/RISCV/sextw-removal.ll
===
--- llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1319,13 +1319,11 @@
 ; NOREMOVAL-NEXT:addi sp, sp, 32
 ; NOREMOVAL-NEXT:ret
 bb:
-  %sext = sext i32 %arg1 to i64
-  %i = call i64 @llvm.riscv.sha256sig0.i64(i64 %sext)
-  %trunc = trunc i64 %i to i32
+  %i = call i32 @llvm.riscv.sha256sig0(i32 %arg1)
   br label %bb2
 
 bb2:  ; preds = %bb2, %bb
-  %i3 = phi i32 [ %trunc, %bb ], [ %i5, %bb2 ]
+  %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ]
   %i4 = tail call signext i32 @bar(i32 signext %i3)
   %i5 = shl i32 %i3, %arg1
   %i6 = icmp eq i32 %i4, 0
@@ -1334,7 +1332,7 @@
 bb7:  ; preds = %bb2
   ret void
 }
-declare i64 @llvm.riscv.sha256sig0.i64(i64)
+declare i32 @llvm.riscv.sha256sig0(i32)
 
 ; The type promotion of %7 forms a sext_inreg, but %7 and %6 are combined to
 ; form a sh2add. This leaves behind a sext.w that isn't needed.
Index: llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksh -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSH
 
-declare i64 @llvm.riscv.sm3p0.i64(i64);
+declare i32 @llvm.riscv.sm3p0(i32);
 
-define i64 @sm3p0_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p0_i64:
+define signext i32 @sm3p0_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p0_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p0 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p0.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p0(i32 signext %a)
+  ret i32 %val
 }
 
-declare i64 @llvm.riscv.sm3p1.i64(i64);
+declare i32 @llvm.riscv.sm3p1(i32);
 
-define i64 @sm3p1_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p1_i64:
+define signext i32 @sm3p1_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p1_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p1 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p1.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p1(i32 signext %a)
+  ret i32 %val
 }
Index: llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksed -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSED
 
-declare i64 @llvm.riscv.sm4ks.i64(i64, i64, i32);
+declare i32 @llvm.riscv.sm4ks(i32, i32, i32);