[PATCH] D155146: [X86] Add SHA512 instructions.
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGfc3b7874b6c9: [X86] Add SHA512 instructions. (authored by FreddyYe). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155146/new/ https://reviews.llvm.org/D155146 Files: clang/docs/ReleaseNotes.rst clang/include/clang/Basic/BuiltinsX86.def clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/X86.cpp clang/lib/Basic/Targets/X86.h clang/lib/Headers/CMakeLists.txt clang/lib/Headers/immintrin.h clang/lib/Headers/sha512intrin.h clang/test/CodeGen/X86/sha512-builtins.c clang/test/CodeGen/attr-target-x86.c clang/test/Driver/x86-target-features.c clang/test/Preprocessor/x86_target_features.c llvm/docs/ReleaseNotes.rst llvm/include/llvm/IR/IntrinsicsX86.td llvm/include/llvm/TargetParser/X86TargetParser.def llvm/lib/Target/X86/X86.td llvm/lib/Target/X86/X86InstrInfo.td llvm/lib/Target/X86/X86InstrSSE.td llvm/lib/TargetParser/Host.cpp llvm/lib/TargetParser/X86TargetParser.cpp llvm/test/CodeGen/X86/sha512-intrinsics.ll llvm/test/MC/Disassembler/X86/sha512-32.txt llvm/test/MC/Disassembler/X86/sha512-64.txt llvm/test/MC/X86/sha512-32-att.s llvm/test/MC/X86/sha512-32-intel.s llvm/test/MC/X86/sha512-64-att.s llvm/test/MC/X86/sha512-64-intel.s Index: llvm/test/MC/X86/sha512-64-intel.s === --- /dev/null +++ llvm/test/MC/X86/sha512-64-intel.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 ymm12, xmm3 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] + vsha512msg1 ymm12, xmm3 + +// CHECK: vsha512msg2 ymm12, ymm3 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] + vsha512msg2 ymm12, ymm3 + +// CHECK: vsha512rnds2 ymm12, ymm3, xmm4 +// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] + vsha512rnds2 ymm12, ymm3, xmm4 + Index: llvm/test/MC/X86/sha512-64-att.s === --- /dev/null +++ llvm/test/MC/X86/sha512-64-att.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 %xmm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] + vsha512msg1 %xmm3, %ymm12 + +// CHECK: vsha512msg2 %ymm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] + vsha512msg2 %ymm3, %ymm12 + +// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] + vsha512rnds2 %xmm4, %ymm3, %ymm12 + Index: llvm/test/MC/X86/sha512-32-intel.s === --- /dev/null +++ llvm/test/MC/X86/sha512-32-intel.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 ymm2, xmm3 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] + vsha512msg1 ymm2, xmm3 + +// CHECK: vsha512msg2 ymm2, ymm3 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] + vsha512msg2 ymm2, ymm3 + +// CHECK: vsha512rnds2 ymm2, ymm3, xmm4 +// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] + vsha512rnds2 ymm2, ymm3, xmm4 Index: llvm/test/MC/X86/sha512-32-att.s === --- /dev/null +++ llvm/test/MC/X86/sha512-32-att.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 %xmm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] + vsha512msg1 %xmm3, %ymm2 + +// CHECK: vsha512msg2 %ymm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] + vsha512msg2 %ymm3, %ymm2 + +// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] + vsha512rnds2 %xmm4, %ymm3, %ymm2 Index: llvm/test/MC/Disassembler/X86/sha512-64.txt === --- /dev/null +++ llvm/test/MC/Disassembler/X86/sha512-64.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: vsha512msg1 %xmm3, %ymm12 +# INTEL: vsha512msg1 ymm12, xmm3 +0xc4,0x62,0x7f,0xcc,0xe3 + +# ATT: vsha512msg2 %ymm3, %ymm12 +# INTEL: vsha512msg2 ymm12, ymm3 +0xc4,0x62,0x7f,0xcd,0xe3 + +# ATT: vsha512rnds2 %xmm4, %ymm3, %ymm12 +# INTEL: vsha512rnds2 ymm12, ymm3, xmm4 +0xc4,0x62,0x67,0xcb,0xe4 + Index: llvm/test/MC/Disassembler/X86/sha512-32.txt === --- /dev/null +++ llvm/test/MC/Disassembler/X86/sha512-32.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=i386 |
[PATCH] D155146: [X86] Add SHA512 instructions.
FreddyYe updated this revision to Diff 542267. FreddyYe added a comment. rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155146/new/ https://reviews.llvm.org/D155146 Files: clang/docs/ReleaseNotes.rst clang/include/clang/Basic/BuiltinsX86.def clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/X86.cpp clang/lib/Basic/Targets/X86.h clang/lib/Headers/CMakeLists.txt clang/lib/Headers/immintrin.h clang/lib/Headers/sha512intrin.h clang/test/CodeGen/X86/sha512-builtins.c clang/test/CodeGen/attr-target-x86.c clang/test/Driver/x86-target-features.c clang/test/Preprocessor/x86_target_features.c llvm/docs/ReleaseNotes.rst llvm/include/llvm/IR/IntrinsicsX86.td llvm/include/llvm/TargetParser/X86TargetParser.def llvm/lib/Target/X86/X86.td llvm/lib/Target/X86/X86InstrInfo.td llvm/lib/Target/X86/X86InstrSSE.td llvm/lib/TargetParser/Host.cpp llvm/lib/TargetParser/X86TargetParser.cpp llvm/test/CodeGen/X86/sha512-intrinsics.ll llvm/test/MC/Disassembler/X86/sha512-32.txt llvm/test/MC/Disassembler/X86/sha512-64.txt llvm/test/MC/X86/sha512-32-att.s llvm/test/MC/X86/sha512-32-intel.s llvm/test/MC/X86/sha512-64-att.s llvm/test/MC/X86/sha512-64-intel.s Index: llvm/test/MC/X86/sha512-64-intel.s === --- /dev/null +++ llvm/test/MC/X86/sha512-64-intel.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 ymm12, xmm3 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] + vsha512msg1 ymm12, xmm3 + +// CHECK: vsha512msg2 ymm12, ymm3 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] + vsha512msg2 ymm12, ymm3 + +// CHECK: vsha512rnds2 ymm12, ymm3, xmm4 +// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] + vsha512rnds2 ymm12, ymm3, xmm4 + Index: llvm/test/MC/X86/sha512-64-att.s === --- /dev/null +++ llvm/test/MC/X86/sha512-64-att.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 %xmm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] + vsha512msg1 %xmm3, %ymm12 + +// CHECK: vsha512msg2 %ymm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] + vsha512msg2 %ymm3, %ymm12 + +// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] + vsha512rnds2 %xmm4, %ymm3, %ymm12 + Index: llvm/test/MC/X86/sha512-32-intel.s === --- /dev/null +++ llvm/test/MC/X86/sha512-32-intel.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 ymm2, xmm3 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] + vsha512msg1 ymm2, xmm3 + +// CHECK: vsha512msg2 ymm2, ymm3 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] + vsha512msg2 ymm2, ymm3 + +// CHECK: vsha512rnds2 ymm2, ymm3, xmm4 +// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] + vsha512rnds2 ymm2, ymm3, xmm4 Index: llvm/test/MC/X86/sha512-32-att.s === --- /dev/null +++ llvm/test/MC/X86/sha512-32-att.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 %xmm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] + vsha512msg1 %xmm3, %ymm2 + +// CHECK: vsha512msg2 %ymm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] + vsha512msg2 %ymm3, %ymm2 + +// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] + vsha512rnds2 %xmm4, %ymm3, %ymm2 Index: llvm/test/MC/Disassembler/X86/sha512-64.txt === --- /dev/null +++ llvm/test/MC/Disassembler/X86/sha512-64.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: vsha512msg1 %xmm3, %ymm12 +# INTEL: vsha512msg1 ymm12, xmm3 +0xc4,0x62,0x7f,0xcc,0xe3 + +# ATT: vsha512msg2 %ymm3, %ymm12 +# INTEL: vsha512msg2 ymm12, ymm3 +0xc4,0x62,0x7f,0xcd,0xe3 + +# ATT: vsha512rnds2 %xmm4, %ymm3, %ymm12 +# INTEL: vsha512rnds2 ymm12, ymm3, xmm4 +0xc4,0x62,0x67,0xcb,0xe4 + Index: llvm/test/MC/Disassembler/X86/sha512-32.txt === --- /dev/null +++ llvm/test/MC/Disassembler/X86/sha512-32.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +#
[PATCH] D155146: [X86] Add SHA512 instructions.
FreddyYe marked 3 inline comments as done. FreddyYe added a comment. I think we can discuss this issue first in https://reviews.llvm.org/D155662 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155146/new/ https://reviews.llvm.org/D155146 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D155146: [X86] Add SHA512 instructions.
FreddyYe updated this revision to Diff 541793. FreddyYe added a comment. Add missing doxygen Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155146/new/ https://reviews.llvm.org/D155146 Files: clang/docs/ReleaseNotes.rst clang/include/clang/Basic/BuiltinsX86.def clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/X86.cpp clang/lib/Basic/Targets/X86.h clang/lib/Headers/CMakeLists.txt clang/lib/Headers/immintrin.h clang/lib/Headers/sha512intrin.h clang/test/CodeGen/X86/sha512-builtins.c clang/test/CodeGen/attr-target-x86.c clang/test/Driver/x86-target-features.c clang/test/Preprocessor/x86_target_features.c llvm/docs/ReleaseNotes.rst llvm/include/llvm/IR/IntrinsicsX86.td llvm/include/llvm/TargetParser/X86TargetParser.def llvm/lib/Target/X86/X86.td llvm/lib/Target/X86/X86InstrInfo.td llvm/lib/Target/X86/X86InstrSSE.td llvm/lib/TargetParser/Host.cpp llvm/lib/TargetParser/X86TargetParser.cpp llvm/test/CodeGen/X86/sha512-intrinsics.ll llvm/test/MC/Disassembler/X86/sha512-32.txt llvm/test/MC/Disassembler/X86/sha512-64.txt llvm/test/MC/X86/sha512-32-att.s llvm/test/MC/X86/sha512-32-intel.s llvm/test/MC/X86/sha512-64-att.s llvm/test/MC/X86/sha512-64-intel.s Index: llvm/test/MC/X86/sha512-64-intel.s === --- /dev/null +++ llvm/test/MC/X86/sha512-64-intel.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 ymm12, xmm3 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] + vsha512msg1 ymm12, xmm3 + +// CHECK: vsha512msg2 ymm12, ymm3 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] + vsha512msg2 ymm12, ymm3 + +// CHECK: vsha512rnds2 ymm12, ymm3, xmm4 +// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] + vsha512rnds2 ymm12, ymm3, xmm4 + Index: llvm/test/MC/X86/sha512-64-att.s === --- /dev/null +++ llvm/test/MC/X86/sha512-64-att.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 %xmm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] + vsha512msg1 %xmm3, %ymm12 + +// CHECK: vsha512msg2 %ymm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] + vsha512msg2 %ymm3, %ymm12 + +// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] + vsha512rnds2 %xmm4, %ymm3, %ymm12 + Index: llvm/test/MC/X86/sha512-32-intel.s === --- /dev/null +++ llvm/test/MC/X86/sha512-32-intel.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 ymm2, xmm3 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] + vsha512msg1 ymm2, xmm3 + +// CHECK: vsha512msg2 ymm2, ymm3 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] + vsha512msg2 ymm2, ymm3 + +// CHECK: vsha512rnds2 ymm2, ymm3, xmm4 +// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] + vsha512rnds2 ymm2, ymm3, xmm4 Index: llvm/test/MC/X86/sha512-32-att.s === --- /dev/null +++ llvm/test/MC/X86/sha512-32-att.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 %xmm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] + vsha512msg1 %xmm3, %ymm2 + +// CHECK: vsha512msg2 %ymm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] + vsha512msg2 %ymm3, %ymm2 + +// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] + vsha512rnds2 %xmm4, %ymm3, %ymm2 Index: llvm/test/MC/Disassembler/X86/sha512-64.txt === --- /dev/null +++ llvm/test/MC/Disassembler/X86/sha512-64.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: vsha512msg1 %xmm3, %ymm12 +# INTEL: vsha512msg1 ymm12, xmm3 +0xc4,0x62,0x7f,0xcc,0xe3 + +# ATT: vsha512msg2 %ymm3, %ymm12 +# INTEL: vsha512msg2 ymm12, ymm3 +0xc4,0x62,0x7f,0xcd,0xe3 + +# ATT: vsha512rnds2 %xmm4, %ymm3, %ymm12 +# INTEL: vsha512rnds2 ymm12, ymm3, xmm4 +0xc4,0x62,0x67,0xcb,0xe4 + Index: llvm/test/MC/Disassembler/X86/sha512-32.txt === --- /dev/null +++ llvm/test/MC/Disassembler/X86/sha512-32.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s
[PATCH] D155146: [X86] Add SHA512 instructions.
FreddyYe updated this revision to Diff 541503. FreddyYe added a comment. Remove -x86-asm-syntax=intel Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155146/new/ https://reviews.llvm.org/D155146 Files: clang/docs/ReleaseNotes.rst clang/include/clang/Basic/BuiltinsX86.def clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/X86.cpp clang/lib/Basic/Targets/X86.h clang/lib/Headers/CMakeLists.txt clang/lib/Headers/immintrin.h clang/lib/Headers/sha512intrin.h clang/test/CodeGen/X86/sha512-builtins.c clang/test/CodeGen/attr-target-x86.c clang/test/Driver/x86-target-features.c clang/test/Preprocessor/x86_target_features.c llvm/docs/ReleaseNotes.rst llvm/include/llvm/IR/IntrinsicsX86.td llvm/include/llvm/TargetParser/X86TargetParser.def llvm/lib/Target/X86/X86.td llvm/lib/Target/X86/X86InstrInfo.td llvm/lib/Target/X86/X86InstrSSE.td llvm/lib/TargetParser/Host.cpp llvm/lib/TargetParser/X86TargetParser.cpp llvm/test/CodeGen/X86/sha512-intrinsics.ll llvm/test/MC/Disassembler/X86/sha512-32.txt llvm/test/MC/Disassembler/X86/sha512-64.txt llvm/test/MC/X86/sha512-32-att.s llvm/test/MC/X86/sha512-32-intel.s llvm/test/MC/X86/sha512-64-att.s llvm/test/MC/X86/sha512-64-intel.s Index: llvm/test/MC/X86/sha512-64-intel.s === --- /dev/null +++ llvm/test/MC/X86/sha512-64-intel.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 ymm12, xmm3 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] + vsha512msg1 ymm12, xmm3 + +// CHECK: vsha512msg2 ymm12, ymm3 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] + vsha512msg2 ymm12, ymm3 + +// CHECK: vsha512rnds2 ymm12, ymm3, xmm4 +// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] + vsha512rnds2 ymm12, ymm3, xmm4 + Index: llvm/test/MC/X86/sha512-64-att.s === --- /dev/null +++ llvm/test/MC/X86/sha512-64-att.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 %xmm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] + vsha512msg1 %xmm3, %ymm12 + +// CHECK: vsha512msg2 %ymm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] + vsha512msg2 %ymm3, %ymm12 + +// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] + vsha512rnds2 %xmm4, %ymm3, %ymm12 + Index: llvm/test/MC/X86/sha512-32-intel.s === --- /dev/null +++ llvm/test/MC/X86/sha512-32-intel.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 ymm2, xmm3 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] + vsha512msg1 ymm2, xmm3 + +// CHECK: vsha512msg2 ymm2, ymm3 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] + vsha512msg2 ymm2, ymm3 + +// CHECK: vsha512rnds2 ymm2, ymm3, xmm4 +// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] + vsha512rnds2 ymm2, ymm3, xmm4 Index: llvm/test/MC/X86/sha512-32-att.s === --- /dev/null +++ llvm/test/MC/X86/sha512-32-att.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 %xmm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] + vsha512msg1 %xmm3, %ymm2 + +// CHECK: vsha512msg2 %ymm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] + vsha512msg2 %ymm3, %ymm2 + +// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] + vsha512rnds2 %xmm4, %ymm3, %ymm2 Index: llvm/test/MC/Disassembler/X86/sha512-64.txt === --- /dev/null +++ llvm/test/MC/Disassembler/X86/sha512-64.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: vsha512msg1 %xmm3, %ymm12 +# INTEL: vsha512msg1 ymm12, xmm3 +0xc4,0x62,0x7f,0xcc,0xe3 + +# ATT: vsha512msg2 %ymm3, %ymm12 +# INTEL: vsha512msg2 ymm12, ymm3 +0xc4,0x62,0x7f,0xcd,0xe3 + +# ATT: vsha512rnds2 %xmm4, %ymm3, %ymm12 +# INTEL: vsha512rnds2 ymm12, ymm3, xmm4 +0xc4,0x62,0x67,0xcb,0xe4 + Index: llvm/test/MC/Disassembler/X86/sha512-32.txt === --- /dev/null +++ llvm/test/MC/Disassembler/X86/sha512-32.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s
[PATCH] D155146: [X86] Add SHA512 instructions.
FreddyYe updated this revision to Diff 541502. FreddyYe added a comment. Split assembly tests and cover more registers. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155146/new/ https://reviews.llvm.org/D155146 Files: clang/docs/ReleaseNotes.rst clang/include/clang/Basic/BuiltinsX86.def clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/X86.cpp clang/lib/Basic/Targets/X86.h clang/lib/Headers/CMakeLists.txt clang/lib/Headers/immintrin.h clang/lib/Headers/sha512intrin.h clang/test/CodeGen/X86/sha512-builtins.c clang/test/CodeGen/attr-target-x86.c clang/test/Driver/x86-target-features.c clang/test/Preprocessor/x86_target_features.c llvm/docs/ReleaseNotes.rst llvm/include/llvm/IR/IntrinsicsX86.td llvm/include/llvm/TargetParser/X86TargetParser.def llvm/lib/Target/X86/X86.td llvm/lib/Target/X86/X86InstrInfo.td llvm/lib/Target/X86/X86InstrSSE.td llvm/lib/TargetParser/Host.cpp llvm/lib/TargetParser/X86TargetParser.cpp llvm/test/CodeGen/X86/sha512-intrinsics.ll llvm/test/MC/Disassembler/X86/sha512-32.txt llvm/test/MC/Disassembler/X86/sha512-64.txt llvm/test/MC/X86/sha512-32-att.s llvm/test/MC/X86/sha512-32-intel.s llvm/test/MC/X86/sha512-64-att.s llvm/test/MC/X86/sha512-64-intel.s Index: llvm/test/MC/X86/sha512-64-intel.s === --- /dev/null +++ llvm/test/MC/X86/sha512-64-intel.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 ymm12, xmm3 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] + vsha512msg1 ymm12, xmm3 + +// CHECK: vsha512msg2 ymm12, ymm3 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] + vsha512msg2 ymm12, ymm3 + +// CHECK: vsha512rnds2 ymm12, ymm3, xmm4 +// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] + vsha512rnds2 ymm12, ymm3, xmm4 + Index: llvm/test/MC/X86/sha512-64-att.s === --- /dev/null +++ llvm/test/MC/X86/sha512-64-att.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 %xmm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] + vsha512msg1 %xmm3, %ymm12 + +// CHECK: vsha512msg2 %ymm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] + vsha512msg2 %ymm3, %ymm12 + +// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12 +// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] + vsha512rnds2 %xmm4, %ymm3, %ymm12 + Index: llvm/test/MC/X86/sha512-32-intel.s === --- /dev/null +++ llvm/test/MC/X86/sha512-32-intel.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 ymm2, xmm3 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] + vsha512msg1 ymm2, xmm3 + +// CHECK: vsha512msg2 ymm2, ymm3 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] + vsha512msg2 ymm2, ymm3 + +// CHECK: vsha512rnds2 ymm2, ymm3, xmm4 +// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] + vsha512rnds2 ymm2, ymm3, xmm4 Index: llvm/test/MC/X86/sha512-32-att.s === --- /dev/null +++ llvm/test/MC/X86/sha512-32-att.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s + +// CHECK: vsha512msg1 %xmm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] + vsha512msg1 %xmm3, %ymm2 + +// CHECK: vsha512msg2 %ymm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] + vsha512msg2 %ymm3, %ymm2 + +// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm2 +// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] + vsha512rnds2 %xmm4, %ymm3, %ymm2 Index: llvm/test/MC/Disassembler/X86/sha512-64.txt === --- /dev/null +++ llvm/test/MC/Disassembler/X86/sha512-64.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: vsha512msg1 %xmm3, %ymm12 +# INTEL: vsha512msg1 ymm12, xmm3 +0xc4,0x62,0x7f,0xcc,0xe3 + +# ATT: vsha512msg2 %ymm3, %ymm12 +# INTEL: vsha512msg2 ymm12, ymm3 +0xc4,0x62,0x7f,0xcd,0xe3 + +# ATT: vsha512rnds2 %xmm4, %ymm3, %ymm12 +# INTEL: vsha512rnds2 ymm12, ymm3, xmm4 +0xc4,0x62,0x67,0xcb,0xe4 + Index: llvm/test/MC/Disassembler/X86/sha512-32.txt === --- /dev/null +++ llvm/test/MC/Disassembler/X86/sha512-32.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=i386
[PATCH] D155146: [X86] Add SHA512 instructions.
RKSimon accepted this revision. RKSimon added a comment. LGTM - but I'd prefer more complete 32-bit vs 64-bit test coverage (similar to the SM3/SM4 patches) if its possible. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155146/new/ https://reviews.llvm.org/D155146 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D155146: [X86] Add SHA512 instructions.
FreddyYe updated this revision to Diff 541392.
FreddyYe marked 2 inline comments as done.
FreddyYe added a comment.
Address comments.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155146/new/
https://reviews.llvm.org/D155146
Files:
clang/docs/ReleaseNotes.rst
clang/include/clang/Basic/BuiltinsX86.def
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/X86.cpp
clang/lib/Basic/Targets/X86.h
clang/lib/Headers/CMakeLists.txt
clang/lib/Headers/immintrin.h
clang/lib/Headers/sha512intrin.h
clang/test/CodeGen/X86/sha512-builtins.c
clang/test/CodeGen/attr-target-x86.c
clang/test/Driver/x86-target-features.c
clang/test/Preprocessor/x86_target_features.c
llvm/docs/ReleaseNotes.rst
llvm/include/llvm/IR/IntrinsicsX86.td
llvm/include/llvm/TargetParser/X86TargetParser.def
llvm/lib/Target/X86/X86.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/lib/Target/X86/X86InstrSSE.td
llvm/lib/TargetParser/Host.cpp
llvm/lib/TargetParser/X86TargetParser.cpp
llvm/test/CodeGen/X86/sha512-intrinsics.ll
llvm/test/MC/Disassembler/X86/sha512.txt
llvm/test/MC/X86/sha512-att.s
llvm/test/MC/X86/sha512-intel.s
Index: llvm/test/MC/X86/sha512-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+ vsha512msg1 ymm2, xmm3
+
+// CHECK: vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+ vsha512msg2 ymm2, ymm3
+
+// CHECK: vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+ vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+ vsha512msg1 %xmm3, %ymm2
+
+// CHECK: vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+ vsha512msg2 %ymm3, %ymm2
+
+// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+ vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL: vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL: vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL: vsha512rnds2 ymm2, ymm3, xmm4
+0xc4,0xe2,0x67,0xcb,0xd4
+
Index: llvm/test/CodeGen/X86/sha512-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/sha512-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+
+define <4 x i64> @test_int_x86_vsha512msg1(<4 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg1:
+; CHECK: # %bb.0:
+; CHECK-NEXT:vsha512msg1 %xmm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcc,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+ ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+
+define <4 x i64> @test_int_x86_vsha512msg2(<4 x i64> %A, <4 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg2:
+; CHECK: # %bb.0:
+; CHECK-NEXT:vsha512msg2 %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcd,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+ ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x
