[PATCH] D155146: Add SHA512 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 540951.
FreddyYe added a comment.

Remove #include 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155146/new/

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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512.txt
  llvm/test/MC/X86/sha512-att.s
  llvm/test/MC/X86/sha512-intel.s

Index: llvm/test/MC/X86/sha512-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4
+0xc4,0xe2,0x67,0xcb,0xd4
+
Index: llvm/test/CodeGen/X86/sha512-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/sha512-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+
+define <4 x i64> @test_int_x86_vsha512msg1(<4 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg1 %xmm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcc,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+
+define <4 x i64> @test_int_x86_vsha512msg2(<4 x i64> %A, <4 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg2 %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcd,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+
+define <4 x i64>

[PATCH] D155146: Add SHA512 instructions.

2023-07-17 Thread Simon Pilgrim via Phabricator via cfe-commits 
RKSimon added inline comments.



Comment at: clang/lib/Headers/sha512intrin.h:21
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_sha512msg1_epi64(__m256i __A, __m128i __B) {

doxygen descriptions?



Comment at: clang/test/CodeGen/X86/sha512-builtins.c:5
+#include 
+#include 
+

why do you need stddef.h?


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  rG LLVM Github Monorepo

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[PATCH] D155146: Add SHA512 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 540909.
FreddyYe added a comment.

Remove `-check-prefix=CHECK`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512.txt
  llvm/test/MC/X86/sha512-att.s
  llvm/test/MC/X86/sha512-intel.s

Index: llvm/test/MC/X86/sha512-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4
+0xc4,0xe2,0x67,0xcb,0xd4
+
Index: llvm/test/CodeGen/X86/sha512-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/sha512-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+
+define <4 x i64> @test_int_x86_vsha512msg1(<4 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg1 %xmm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcc,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+
+define <4 x i64> @test_int_x86_vsha512msg2(<4 x i64> %A, <4 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg2 %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcd,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+
+define <4 x i64>

[PATCH] D155146: Add SHA512 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 540893.
FreddyYe added a comment.

Added FIXME for schedule


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512.txt
  llvm/test/MC/X86/sha512-att.s
  llvm/test/MC/X86/sha512-intel.s

Index: llvm/test/MC/X86/sha512-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4
+0xc4,0xe2,0x67,0xcb,0xd4
+
Index: llvm/test/CodeGen/X86/sha512-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/sha512-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s -check-prefixes=CHECK
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s -check-prefixes=CHECK
+
+define <4 x i64> @test_int_x86_vsha512msg1(<4 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg1 %xmm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcc,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+
+define <4 x i64> @test_int_x86_vsha512msg2(<4 x i64> %A, <4 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg2 %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcd,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg2(<4 x i64>

[PATCH] D155146: Add SHA512 instructions.

2023-07-17 Thread Kan Shengchen via Phabricator via cfe-commits 
skan accepted this revision.
skan added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D155146: Add SHA512 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 540885.
FreddyYe marked 15 inline comments as done.
FreddyYe added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512.txt
  llvm/test/MC/X86/sha512-att.s
  llvm/test/MC/X86/sha512-intel.s

Index: llvm/test/MC/X86/sha512-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4
+0xc4,0xe2,0x67,0xcb,0xd4
+
Index: llvm/test/CodeGen/X86/sha512-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/sha512-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s -check-prefixes=CHECK
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s -check-prefixes=CHECK
+
+define <4 x i64> @test_int_x86_vsha512msg1(<4 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg1 %xmm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcc,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+
+define <4 x i64> @test_int_x86_vsha512msg2(<4 x i64> %A, <4 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg2 %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcd,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x

[PATCH] D155146: Add SHA512 instructions.

2023-07-13 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:243
+  "Support SHA512 instructions",
+  [FeatureAVX]>;
 // Processor supports CET SHSTK - Control-Flow Enforcement Technology

craig.topper wrote:
> AVX2 like other integer features?
ISE says it only requires AVX


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[PATCH] D155146: Add SHA512 instructions.

2023-07-13 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:243
+  "Support SHA512 instructions",
+  [FeatureAVX]>;
 // Processor supports CET SHSTK - Control-Flow Enforcement Technology

AVX2 like other integer features?



Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8304
+[(set VR256:$dst,
+ (int_x86_vsha512msg1 VR256:$src1, VR128:$src2))]>, VEX_L,
+VEX, T8XD, Sched<[WriteVecIMul]>;

This paren should be indented 1 more space so that it's not at the same column 
as the one above it.



Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8310
+[(set VR256:$dst,
+ (int_x86_vsha512msg2 VR256:$src1, VR256:$src2))]>, VEX_L,
+VEX, T8XD, Sched<[WriteVecIMul]>;

ditto



Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8316
+  [(set VR256:$dst,
+   (int_x86_vsha512rnds2 VR256:$src1, VR256:$src2, 
VR128:$src3))]>,
+  VEX_L, VEX_4V, T8XD, Sched<[WriteVecIMul]>;

ditto



Comment at: llvm/lib/TargetParser/X86TargetParser.cpp:214
 FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
+FeatureSHA512 |
 FeatureAMX_COMPLEX;

Unnecessary line break



Comment at: llvm/lib/TargetParser/X86TargetParser.cpp:659
 constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2;
+constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX;
 constexpr FeatureBitset ImpliedFeaturesAVX512FP16 =

Should this be AVX2 like all the other integer features?


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[PATCH] D155146: Add SHA512 instructions.

2023-07-13 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei added inline comments.



Comment at: clang/lib/Headers/CMakeLists.txt:207
   shaintrin.h
+  sha512intrin.h
   smmintrin.h

alphabetical order



Comment at: llvm/include/llvm/IR/IntrinsicsX86.td:5112
+def int_x86_vsha512msg1 : ClangBuiltin<"__builtin_ia32_vsha512msg1">,
+Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v2i64_ty], 
[IntrNoMem]>;
+def int_x86_vsha512msg2 : ClangBuiltin<"__builtin_ia32_vsha512msg2">,

DefaultAttrsIntrinsic



Comment at: llvm/include/llvm/IR/IntrinsicsX86.td:5114
+def int_x86_vsha512msg2 : ClangBuiltin<"__builtin_ia32_vsha512msg2">,
+Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty], 
[IntrNoMem]>;
+def int_x86_vsha512rnds2 : ClangBuiltin<"__builtin_ia32_vsha512rnds2">,

ditto.



Comment at: llvm/include/llvm/IR/IntrinsicsX86.td:5116
+def int_x86_vsha512rnds2 : ClangBuiltin<"__builtin_ia32_vsha512rnds2">,
+Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty, 
llvm_v2i64_ty],
+[IntrNoMem]>;

ditto.



Comment at: llvm/test/CodeGen/X86/sha512-intrinsics.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=x86_64-unknown-unknown 
--show-mc-encoding -mattr=+sha512 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=i686-unknown-unknown 
--show-mc-encoding -mattr=+sha512 | FileCheck %s --check-prefixes=X86

`X64,CHECK`



Comment at: llvm/test/CodeGen/X86/sha512-intrinsics.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=x86_64-unknown-unknown 
--show-mc-encoding -mattr=+sha512 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=i686-unknown-unknown 
--show-mc-encoding -mattr=+sha512 | FileCheck %s --check-prefixes=X86

pengfei wrote:
> `X64,CHECK`
No need O0



Comment at: llvm/test/CodeGen/X86/sha512-intrinsics.ll:3
+; ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=x86_64-unknown-unknown 
--show-mc-encoding -mattr=+sha512 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=i686-unknown-unknown 
--show-mc-encoding -mattr=+sha512 | FileCheck %s --check-prefixes=X86
+

`X86,CHECK`



Comment at: llvm/test/CodeGen/X86/sha512-intrinsics.ll:3
+; ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=x86_64-unknown-unknown 
--show-mc-encoding -mattr=+sha512 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=i686-unknown-unknown 
--show-mc-encoding -mattr=+sha512 | FileCheck %s --check-prefixes=X86
+

pengfei wrote:
> `X86,CHECK`
ditto.



Comment at: llvm/test/MC/Disassembler/X86/sha512-64.txt:1-2
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s 
--check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel 
--output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+

This can be merged with `sha512-32.txt`



Comment at: llvm/test/MC/X86/sha512-att-64.s:1
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+

ditto.



Comment at: llvm/test/MC/X86/sha512-intel-64.s:1
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 
--show-encoding %s | FileCheck %s
+

ditto.


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[PATCH] D155146: Add SHA512 instructions.

2023-07-12 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe created this revision.
Herald added subscribers: pengfei, hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

For more details about this instruction, please refer to the latest ISE 
document: 
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html


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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512-32.txt
  llvm/test/MC/Disassembler/X86/sha512-64.txt
  llvm/test/MC/X86/sha512-att-32.s
  llvm/test/MC/X86/sha512-att-64.s
  llvm/test/MC/X86/sha512-intel-32.s
  llvm/test/MC/X86/sha512-intel-64.s

Index: llvm/test/MC/X86/sha512-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel-64.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-intel-32.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel-32.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att-64.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/X86/sha512-att-32.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att-32.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512-64.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-64.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4