[PATCH] D156321: [Clang][RISCV] Remove RVV intrinsics `vread_csr`,`vwrite_csr`

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7cb81c1b8ce5: [Clang][RISCV] Remove RVV intrinsics 
`vread_csr`,`vwrite_csr` (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156321/new/

https://reviews.llvm.org/D156321

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c
+++ /dev/null
@@ -1,42 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
-// RUN: | opt -S -O2 | FileCheck  %s
-
-#include 
-
-// CHECK-LABEL: @vwrite_csr_vstart(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
-// CHECK-NEXT:ret void
-//
-void vwrite_csr_vstart(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VSTART, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vxsat(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
-// CHECK-NEXT:ret void
-//
-void vwrite_csr_vxsat(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VXSAT, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vxrm(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
-// CHECK-NEXT:ret void
-//
-void vwrite_csr_vxrm(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VXRM, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vcsr(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
-// CHECK-NEXT:ret void
-//
-void vwrite_csr_vcsr(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VCSR, value);
-}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c
+++ /dev/null
@@ -1,42 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
-// RUN: | opt -S -O2 | FileCheck  %s
-
-#include 
-
-// CHECK-LABEL: @vread_csr_vstart(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
-// CHECK-NEXT:ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vstart(void) {
-  return __riscv_vread_csr(RVV_VSTART);
-}
-
-// CHECK-LABEL: @vread_csr_vxsat(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
-// CHECK-NEXT:ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vxsat(void) {
-  return __riscv_vread_csr(RVV_VXSAT);
-}
-
-// CHECK-LABEL: @vread_csr_vxrm(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
-// CHECK-NEXT:ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vxrm(void) {
-  return __riscv_vread_csr(RVV_VXRM);
-}
-
-// CHECK-LABEL: @vread_csr_vcsr(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
-// CHECK-NEXT:ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vcsr(void) {
-  return __riscv_vread_csr(RVV_VCSR);
-}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -990,56 +990,6 @@
   }
 }
 
-// Define vread_csr_csr described in RVV intrinsics doc.
-let HeaderCode =
-[{
-enum RVV_CSR {
-  RVV_VSTART = 0,
-  RVV_VXSAT,
-  RVV_VXRM,
-  RVV_VCSR,
-};
-
-static __inline__ __attribute__((__always_inline__, __nodebug__))
-unsigned long __riscv_vread_csr(enum RVV_CSR __csr) {
-  unsigned long __rv = 0;
-  switch (__csr) {
-case RVV_VSTART:
-  __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
-  break;
-case RVV_VXSAT:
-  __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
-  break;
-case RVV_VXRM:
-  __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
-  break;
-case RVV_VCSR:
- 

[PATCH] D156321: [Clang][RISCV] Remove RVV intrinsics `vread_csr`,`vwrite_csr`

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156321/new/

https://reviews.llvm.org/D156321

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[PATCH] D156321: [Clang[RISCV] Remove RVV intrinsics `vread_csr`,`vwrite_csr`

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: kito-cheng, craig.topper, rogfer01.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, MaskRay.
Herald added a project: clang.

As proposed in riscv-non-isa/rvv-intrinsic-doc#249, removing the interface.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156321

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c
+++ /dev/null
@@ -1,42 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
-// RUN: | opt -S -O2 | FileCheck  %s
-
-#include 
-
-// CHECK-LABEL: @vwrite_csr_vstart(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
-// CHECK-NEXT:ret void
-//
-void vwrite_csr_vstart(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VSTART, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vxsat(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
-// CHECK-NEXT:ret void
-//
-void vwrite_csr_vxsat(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VXSAT, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vxrm(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
-// CHECK-NEXT:ret void
-//
-void vwrite_csr_vxrm(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VXRM, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vcsr(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
-// CHECK-NEXT:ret void
-//
-void vwrite_csr_vcsr(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VCSR, value);
-}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c
+++ /dev/null
@@ -1,42 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
-// RUN: | opt -S -O2 | FileCheck  %s
-
-#include 
-
-// CHECK-LABEL: @vread_csr_vstart(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
-// CHECK-NEXT:ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vstart(void) {
-  return __riscv_vread_csr(RVV_VSTART);
-}
-
-// CHECK-LABEL: @vread_csr_vxsat(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
-// CHECK-NEXT:ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vxsat(void) {
-  return __riscv_vread_csr(RVV_VXSAT);
-}
-
-// CHECK-LABEL: @vread_csr_vxrm(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
-// CHECK-NEXT:ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vxrm(void) {
-  return __riscv_vread_csr(RVV_VXRM);
-}
-
-// CHECK-LABEL: @vread_csr_vcsr(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
-// CHECK-NEXT:ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vcsr(void) {
-  return __riscv_vread_csr(RVV_VCSR);
-}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -990,56 +990,6 @@
   }
 }
 
-// Define vread_csr_csr described in RVV intrinsics doc.
-let HeaderCode =
-[{
-enum RVV_CSR {
-  RVV_VSTART = 0,
-  RVV_VXSAT,
-  RVV_VXRM,
-  RVV_VCSR,
-};
-
-static __inline__ __attribute__((__always_inline__, __nodebug__))
-unsigned long __riscv_vread_csr(enum RVV_CSR __csr) {
-  unsigned long __rv = 0;
-  switch (__csr) {
-case RVV_VSTART:
-  __asm__