[PATCH] D158065: [PowerPC] Implement builtin for mffsl

2023-09-04 Thread Qiu Chaofan via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG082c5d7f63c4: [PowerPC] Implement builtin for mffsl 
(authored by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158065/new/

https://reviews.llvm.org/D158065

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/PowerPC/builtins-ppc.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/read-set-flm.ll


Index: llvm/test/CodeGen/PowerPC/read-set-flm.ll
===
--- llvm/test/CodeGen/PowerPC/read-set-flm.ll
+++ llvm/test/CodeGen/PowerPC/read-set-flm.ll
@@ -148,8 +148,19 @@
   ret void
 }
 
+define double @mffsl() {
+; CHECK-LABEL: mffsl:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffsl 1
+; CHECK-NEXT:blr
+entry:
+  %x = call double @llvm.ppc.mffsl()
+  ret double %x
+}
+
 declare void @effect_func()
 declare void @readonly_func() #1
+declare double @llvm.ppc.mffsl()
 declare double @llvm.ppc.readflm()
 declare double @llvm.ppc.setflm(double)
 declare double @llvm.experimental.constrained.fadd.f64(double, double, 
metadata, metadata)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3180,6 +3180,7 @@
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
 def : Pat<(int_ppc_readflm), (MFFS)>;
+def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
 // Hi and Lo for Darwin Global Addresses.
 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -33,6 +33,10 @@
   def int_ppc_readflm : ClangBuiltin<"__builtin_readflm">,
 DefaultAttrsIntrinsic<[llvm_double_ty], [],
   [IntrNoMerge, 
IntrHasSideEffects]>;
+  def int_ppc_mffsl : ClangBuiltin<"__builtin_ppc_mffsl">,
+  DefaultAttrsIntrinsic<[llvm_double_ty], [],
+[IntrNoMerge, IntrHasSideEffects]>;
+
   // Set FPSCR register, and return previous content
   def int_ppc_setflm : ClangBuiltin<"__builtin_setflm">,
DefaultAttrsIntrinsic<[llvm_double_ty], 
[llvm_double_ty],
Index: clang/test/CodeGen/PowerPC/builtins-ppc.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc.c
@@ -35,6 +35,11 @@
 
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
+
+#ifdef _ARCH_PWR9
+  // P9: call double @llvm.ppc.mffsl()
+  res = __builtin_ppc_mffsl();
+#endif
 }
 
 double test_builtin_unpack_ldbl(long double x) {
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -151,6 +151,7 @@
 TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector")
 BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
 BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
+TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions")
 BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
 BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
 TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector")


Index: llvm/test/CodeGen/PowerPC/read-set-flm.ll
===
--- llvm/test/CodeGen/PowerPC/read-set-flm.ll
+++ llvm/test/CodeGen/PowerPC/read-set-flm.ll
@@ -148,8 +148,19 @@
   ret void
 }
 
+define double @mffsl() {
+; CHECK-LABEL: mffsl:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffsl 1
+; CHECK-NEXT:blr
+entry:
+  %x = call double @llvm.ppc.mffsl()
+  ret double %x
+}
+
 declare void @effect_func()
 declare void @readonly_func() #1
+declare double @llvm.ppc.mffsl()
 declare double @llvm.ppc.readflm()
 declare double @llvm.ppc.setflm(double)
 declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3180,6 +3180,7 @@
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
 def : Pat<(int_ppc_readflm), (MFFS)>;
+def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
 // Hi and Lo for Darwin Global Addresses.
 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++

[PATCH] D158065: [PowerPC] Implement builtin for mffsl

2023-08-20 Thread Nemanja Ivanovic via Phabricator via cfe-commits 
nemanjai accepted this revision.
nemanjai added a comment.

Thanks for implementing this.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D158065/new/

https://reviews.llvm.org/D158065

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[PATCH] D158065: [PowerPC] Implement builtin for mffsl

2023-08-16 Thread Tulio Magno Quites Machado Filho via Phabricator via cfe-commits 
tuliom accepted this revision.
tuliom added a comment.
This revision is now accepted and ready to land.

LGTM


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https://reviews.llvm.org/D158065

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[PATCH] D158065: [PowerPC] Implement builtin for mffsl

2023-08-16 Thread Qiu Chaofan via Phabricator via cfe-commits 
qiucf created this revision.
qiucf added reviewers: nemanjai, stefanp, shchenz, PowerPC.
Herald added subscribers: kbarton, hiraditya.
Herald added a project: All.
qiucf requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

`mffsl` is available since ISA 3.0.

GCC emits extra code to support `__builtin_mffsl` on targets earlier than 
Power9, while this patch doesn't do it. In this patch it is actually named 
`__builtin_ppc_mffsl` to follow our convention.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158065

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/PowerPC/builtins-ppc.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/read-set-flm.ll


Index: llvm/test/CodeGen/PowerPC/read-set-flm.ll
===
--- llvm/test/CodeGen/PowerPC/read-set-flm.ll
+++ llvm/test/CodeGen/PowerPC/read-set-flm.ll
@@ -148,8 +148,19 @@
   ret void
 }
 
+define double @mffsl() {
+; CHECK-LABEL: mffsl:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffsl 1
+; CHECK-NEXT:blr
+entry:
+  %x = call double @llvm.ppc.mffsl()
+  ret double %x
+}
+
 declare void @effect_func()
 declare void @readonly_func() #1
+declare double @llvm.ppc.mffsl()
 declare double @llvm.ppc.readflm()
 declare double @llvm.ppc.setflm(double)
 declare double @llvm.experimental.constrained.fadd.f64(double, double, 
metadata, metadata)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3180,6 +3180,7 @@
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
 def : Pat<(int_ppc_readflm), (MFFS)>;
+def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
 // Hi and Lo for Darwin Global Addresses.
 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -33,6 +33,10 @@
   def int_ppc_readflm : ClangBuiltin<"__builtin_readflm">,
 DefaultAttrsIntrinsic<[llvm_double_ty], [],
   [IntrNoMerge, 
IntrHasSideEffects]>;
+  def int_ppc_mffsl : ClangBuiltin<"__builtin_ppc_mffsl">,
+  DefaultAttrsIntrinsic<[llvm_double_ty], [],
+[IntrNoMerge, IntrHasSideEffects]>;
+
   // Set FPSCR register, and return previous content
   def int_ppc_setflm : ClangBuiltin<"__builtin_setflm">,
DefaultAttrsIntrinsic<[llvm_double_ty], 
[llvm_double_ty],
Index: clang/test/CodeGen/PowerPC/builtins-ppc.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc.c
@@ -35,6 +35,11 @@
 
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
+
+#ifdef _ARCH_PWR9
+  // P9: call double @llvm.ppc.mffsl()
+  res = __builtin_ppc_mffsl();
+#endif
 }
 
 double test_builtin_unpack_ldbl(long double x) {
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -151,6 +151,7 @@
 TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector")
 BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
 BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
+TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions")
 BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
 BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
 TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector")


Index: llvm/test/CodeGen/PowerPC/read-set-flm.ll
===
--- llvm/test/CodeGen/PowerPC/read-set-flm.ll
+++ llvm/test/CodeGen/PowerPC/read-set-flm.ll
@@ -148,8 +148,19 @@
   ret void
 }
 
+define double @mffsl() {
+; CHECK-LABEL: mffsl:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffsl 1
+; CHECK-NEXT:blr
+entry:
+  %x = call double @llvm.ppc.mffsl()
+  ret double %x
+}
+
 declare void @effect_func()
 declare void @readonly_func() #1
+declare double @llvm.ppc.mffsl()
 declare double @llvm.ppc.readflm()
 declare double @llvm.ppc.setflm(double)
 declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3180,6 +3180,7 @@
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
 def : Pat<(int_ppc_readflm), (MFFS)>;
+def : Pat<(int_ppc_mffsl),