[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[ZiXuan Wu via Phabricator via cfe-commits]

Zeson abandoned this revision.
Zeson added a comment.

I think this revision is out-of-date. I'd like to abandon it.


https://reviews.llvm.org/D27251



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[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[Nemanja Ivanovic via Phabricator via cfe-commits]

nemanjai added a comment.

@Zeson are you working on an update to this or is this to be abandoned?


https://reviews.llvm.org/D27251



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[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[Kit Barton via Phabricator via cfe-commits]

kbarton added a comment.

Sorry, I don't have time to go through the entire patch in detail right now. 
But I did notice several places where the lines are too long, which need to get 
fixed.




Comment at: lib/Headers/altivec.h:14206
   vector signed long long __b) {
-  return __builtin_altivec_vcmpgtud_p(__CR6_LT, (vector unsigned long long)__a,
-  (vector unsigned long long)__b);
+  return __builtin_altivec_vcmpgtsd_p(__CR6_LT, (vector signed long long)__a, 
__b);
 }

line too long



Comment at: lib/Headers/altivec.h:14381
   vector signed long long __b) {
-  return __builtin_altivec_vcmpgtud_p(__CR6_EQ, (vector unsigned long long)__a,
-  (vector unsigned long long)__b);
+  return __builtin_altivec_vcmpgtsd_p(__CR6_EQ, (vector signed long long)__a, 
__b);
 }

line too long



Comment at: lib/Headers/altivec.h:14549
   vector signed long long __b) {
-  return __builtin_altivec_vcmpgtud_p(__CR6_LT, (vector unsigned long long)__b,
-  (vector unsigned long long)__a);
+  return __builtin_altivec_vcmpgtsd_p(__CR6_LT, __b, (vector signed long 
long)__a);
 }

line too long


https://reviews.llvm.org/D27251



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[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[ZiXuan Wu via Phabricator via cfe-commits]

Zeson marked 2 inline comments as done.
Zeson added a comment.

Hi, All.

The revision has been updated, please review it again. 
Thanks a lot.


https://reviews.llvm.org/D27251



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[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[ZiXuan Wu via Phabricator via cfe-commits]

Zeson added a comment.

In https://reviews.llvm.org/D27251#610629, @kbarton wrote:

> Please make explicit the signed for the parameters to the functions you are 
> changing and remove unnecessary casts. I marked the first few that I found, 
> but stopped marking them after the first several.


I think it does not need to make explicit signed for the parameters such as 
making `vector int` to `vector signed int`, making `vector short` to `vector 
signed short`.
The whole file containing lots of such issues can be modified or fixed in 
another single patch to avoid introducing noise in this patch.


https://reviews.llvm.org/D27251



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[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[ZiXuan Wu via Phabricator via cfe-commits]

Zeson updated this revision to Diff 80021.
Zeson marked 3 inline comments as done.
Zeson added a comment.

Remove some unnecessary cast


https://reviews.llvm.org/D27251

Files:
  lib/Headers/altivec.h
  test/CodeGen/builtins-ppc-altivec.c
  test/CodeGen/builtins-ppc-p8vector.c
  test/CodeGen/builtins-ppc-vsx.c

Index: test/CodeGen/builtins-ppc-vsx.c
===
--- test/CodeGen/builtins-ppc-vsx.c
+++ test/CodeGen/builtins-ppc-vsx.c
@@ -1592,11 +1592,11 @@
 // CHECK: @llvm.ppc.altivec.vsl
 // CHECK-LE: @llvm.ppc.altivec.vsl
 
-res_vull = vec_sll(vull, vuc);
+  res_vull = vec_sll(vull, vuc);
 // CHECK: @llvm.ppc.altivec.vsl
 // CHECK-LE: @llvm.ppc.altivec.vsl
 
-res_vsll = vec_slo(vsll, vsc);
+  res_vsll = vec_slo(vsll, vsc);
 // CHECK: @llvm.ppc.altivec.vslo
 // CHECK-LE: @llvm.ppc.altivec.vslo
 
@@ -1636,59 +1636,134 @@
 // CHECK: @llvm.ppc.altivec.vsro
 // CHECK-LE: @llvm.ppc.altivec.vsro
 
-res_vsll = vec_xl(sll, asll);
+  res_vsll = vec_xl(sll, asll);
 // CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
 // CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
 
-res_vull = vec_xl(sll, aull);
+  res_vull = vec_xl(sll, aull);
 // CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
 // CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
 
-res_vd = vec_xl(sll, ad);
+  res_vd = vec_xl(sll, ad);
 // CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
 // CHECK-LE: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
 
-vec_xst(vsll, sll, asll);
+  vec_xst(vsll, sll, asll);
 // CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
 // CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
 
-vec_xst(vull, sll, aull);
+  vec_xst(vull, sll, aull);
 // CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
 // CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
 
-vec_xst(vd, sll, ad);
+  vec_xst(vd, sll, ad);
 // CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
 // CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
 
-res_vsll = vec_xl_be(sll, asll);
-// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
-// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
-
-res_vull = vec_xl_be(sll, aull);
-// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
-// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
-
-res_vd = vec_xl_be(sll, ad);
-// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
-// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
-
-vec_xst_be(vsll, sll, asll);
-// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
-// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
-
-vec_xst_be(vull, sll, aull);
-// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
-// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
-
-vec_xst_be(vd, sll, ad);
-// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
-// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
-
   res_vf = vec_neg(vf);
 // CHECK: fsub <4 x float> , {{%[0-9]+}}
 // CHECK-LE: fsub <4 x float> , {{%[0-9]+}}
 
   res_vd = vec_neg(vd);
 // CHECK: fsub <2 x double> , {{%[0-9]+}}
 // CHECK-LE: fsub <2 x double> , {{%[0-9]+}}
 }
+
+
+/* - vec_xl_be -- */
+void test2() {
+  // CHECK-LABEL: define void @test2
+  // CHECK-LE-LABEL: define void @test2
+  vec_xl_be(sll, asc);
+  // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+  // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> 
+
+  vec_xl_be(sll, auc);
+  // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+  // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> 
+
+  vec_xl_be(sll, ass);
+  // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+  // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> 
+
+  vec_xl_be(sll, aus);
+  // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+  // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> 
+
+  vec_xl_be(sll, asi);
+  // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %{{[0-9]+}})
+
+  vec_xl_be(sll, aui);
+  // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %{{[0-9]+}})
+
+  

[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[Kit Barton via Phabricator via cfe-commits]

kbarton requested changes to this revision.
kbarton added a comment.
This revision now requires changes to proceed.

Please make explicit the signed for the parameters to the functions you are 
changing and remove unnecessary casts. I marked the first few that I found, but 
stopped marking them after the first several.




Comment at: lib/Headers/altivec.h:13928
   vector signed char __b) {
-  return __builtin_altivec_vcmpgtub_p(__CR6_EQ, (vector unsigned char)__b,
-  (vector unsigned char)__a);
+  return __builtin_altivec_vcmpgtsb_p(__CR6_EQ, (vector signed char)__b,
+  (vector signed char)__a);

The cast for  __b is necessary, since it is already a vector signed char. 
I don't know whether this will generate superfluous warnings or not, but it's 
probably best to remove it.



Comment at: lib/Headers/altivec.h:13965
 static __inline__ int __ATTRS_o_ai vec_all_ge(vector bool short __a,
   vector short __b) {
+  return __builtin_altivec_vcmpgtsh_p(__CR6_EQ, (vector signed short)__b,

It's better to make the parameter explicitly vector signed short, and remove 
the cast on the next line, for consistency with other builtins. 



Comment at: lib/Headers/altivec.h:14002
 static __inline__ int __ATTRS_o_ai vec_all_ge(vector bool int __a,
   vector int __b) {
+  return __builtin_altivec_vcmpgtsw_p(__CR6_EQ, (vector signed int)__b,

same comment - explicitly vector signed int



Comment at: lib/Headers/altivec.h:14042
   vector signed long long __b) {
-  return __builtin_altivec_vcmpgtud_p(__CR6_EQ, (vector unsigned long long)__b,
-  (vector unsigned long long)__a);
+  return __builtin_altivec_vcmpgtsd_p(__CR6_EQ, (vector signed long long)__b,
+  (vector signed long long)__a);

No cast needed here



Comment at: lib/Headers/altivec.h:14099
   vector signed char __b) {
-  return __builtin_altivec_vcmpgtub_p(__CR6_LT, (vector unsigned char)__a,
-  (vector unsigned char)__b);
+  return __builtin_altivec_vcmpgtsb_p(__CR6_LT, (vector signed char)__a,
+  (vector signed char)__b);

No cast needed here 



Comment at: lib/Headers/altivec.h:14136
 static __inline__ int __ATTRS_o_ai vec_all_gt(vector bool short __a,
   vector short __b) {
+  return __builtin_altivec_vcmpgtsh_p(__CR6_LT, (vector signed short)__a,

Make signed explicit here


https://reviews.llvm.org/D27251



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[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[ZiXuan Wu via Phabricator via cfe-commits]

Zeson updated this revision to Diff 79856.
Zeson added a comment.

Make vec_xst_be and vec_xl_be test cases put together seperately in 
`builtins-ppc-vsx.c`
Move up macro `__VSX__` to make all vec_xst_be functions included


https://reviews.llvm.org/D27251

Files:
  lib/Headers/altivec.h
  test/CodeGen/builtins-ppc-altivec.c
  test/CodeGen/builtins-ppc-p8vector.c
  test/CodeGen/builtins-ppc-vsx.c

Index: test/CodeGen/builtins-ppc-vsx.c
===
--- test/CodeGen/builtins-ppc-vsx.c
+++ test/CodeGen/builtins-ppc-vsx.c
@@ -1592,11 +1592,11 @@
 // CHECK: @llvm.ppc.altivec.vsl
 // CHECK-LE: @llvm.ppc.altivec.vsl
 
-res_vull = vec_sll(vull, vuc);
+  res_vull = vec_sll(vull, vuc);
 // CHECK: @llvm.ppc.altivec.vsl
 // CHECK-LE: @llvm.ppc.altivec.vsl
 
-res_vsll = vec_slo(vsll, vsc);
+  res_vsll = vec_slo(vsll, vsc);
 // CHECK: @llvm.ppc.altivec.vslo
 // CHECK-LE: @llvm.ppc.altivec.vslo
 
@@ -1636,59 +1636,134 @@
 // CHECK: @llvm.ppc.altivec.vsro
 // CHECK-LE: @llvm.ppc.altivec.vsro
 
-res_vsll = vec_xl(sll, asll);
+  res_vsll = vec_xl(sll, asll);
 // CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
 // CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
 
-res_vull = vec_xl(sll, aull);
+  res_vull = vec_xl(sll, aull);
 // CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
 // CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
 
-res_vd = vec_xl(sll, ad);
+  res_vd = vec_xl(sll, ad);
 // CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
 // CHECK-LE: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
 
-vec_xst(vsll, sll, asll);
+  vec_xst(vsll, sll, asll);
 // CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
 // CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
 
-vec_xst(vull, sll, aull);
+  vec_xst(vull, sll, aull);
 // CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
 // CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
 
-vec_xst(vd, sll, ad);
+  vec_xst(vd, sll, ad);
 // CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
 // CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
 
-res_vsll = vec_xl_be(sll, asll);
-// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
-// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
-
-res_vull = vec_xl_be(sll, aull);
-// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
-// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
-
-res_vd = vec_xl_be(sll, ad);
-// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
-// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
-
-vec_xst_be(vsll, sll, asll);
-// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
-// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
-
-vec_xst_be(vull, sll, aull);
-// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
-// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
-
-vec_xst_be(vd, sll, ad);
-// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
-// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
-
   res_vf = vec_neg(vf);
 // CHECK: fsub <4 x float> , {{%[0-9]+}}
 // CHECK-LE: fsub <4 x float> , {{%[0-9]+}}
 
   res_vd = vec_neg(vd);
 // CHECK: fsub <2 x double> , {{%[0-9]+}}
 // CHECK-LE: fsub <2 x double> , {{%[0-9]+}}
 }
+
+
+/* - vec_xl_be -- */
+void test2() {
+  // CHECK-LABEL: define void @test2
+  // CHECK-LE-LABEL: define void @test2
+  vec_xl_be(sll, asc);
+  // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+  // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> 
+
+  vec_xl_be(sll, auc);
+  // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+  // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> 
+
+  vec_xl_be(sll, ass);
+  // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+  // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> 
+
+  vec_xl_be(sll, aus);
+  // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+  // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> 
+
+  vec_xl_be(sll, asi);
+  // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 16
+  // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %{{[0-9]+}})
+
+  vec_xl_be(sll, aui);
+  // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, 

[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[Tony Jiang via Phabricator via cfe-commits]

jtony added inline comments.



Comment at: lib/Headers/altivec.h:16456
 
 #ifdef __VSX__
 static __inline__ vector signed long long __ATTRS_o_ai

Thanks  a lot for your good catch for the macro issue in vec_xst_be, that's a 
good catch. BTW, Can you move this up also like vec_xst_be?



Comment at: test/CodeGen/builtins-ppc-vsx.c:1696
+
+signed char param_sc;
+unsigned char param_uc;

I would prefer these definitions occur at the beginning of the file like 
before. 



Comment at: test/CodeGen/builtins-ppc-vsx.c:1706
+/* - vec_xl_be -- 
*/
+void test2() {
+  // CHECK-LABEL: define void @test2

These test cases should be grouped together with the test  cases from 1663 - 
1683. Put the vec_xl_be overloads together,  and the vec_xst_be together (maybe 
after vec_xl_be). I am OK with either put these test2 and test3 into test 1, or 
make them stand-alone, as long as these overloaded test cases for vec_xst_be 
and vec_xl_be are put together seperately. Thanks for you good catch, this 
problem is not found in our previous code review.


https://reviews.llvm.org/D27251



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[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[ZiXuan Wu via Phabricator via cfe-commits]

Zeson added a comment.

In https://reviews.llvm.org/D27251#609014, @nemanjai wrote:

> Thank you for fixing these issues. I certainly see how the shifts really need 
> to get the signedness right because the right shifts need to fill with the 
> sign bit (so that vector bool will still have all 0 or all 1 bits). However, 
> I don't really follow why the comparisons need to be signed. Could you just 
> elaborate a bit on that?
>  Other than satisfying my curiosity on that, this LGTM.


In my opinion, from the table in the PDF above, it seems that vector bool would 
be treated as unsigned or signed depending on the other argument type and it 
would be mapped to related machine instruction. As machine instruction, it is 
just treated as signed or unsigned operand.
F2627693: Screen Shot 2016-11-30 at 9.54.40 PM.png 



https://reviews.llvm.org/D27251



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[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

[Nemanja Ivanovic via Phabricator via cfe-commits]

nemanjai added a comment.

Thank you for fixing these issues. I certainly see how the shifts really need 
to get the signedness right because the right shifts need to fill with the sign 
bit (so that vector bool will still have all 0 or all 1 bits). However, I don't 
really follow why the comparisons need to be signed. Could you just elaborate a 
bit on that?
Other than satisfying my curiosity on that, this LGTM.


https://reviews.llvm.org/D27251



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