This revision was automatically updated to reflect the committed changes.
Closed by commit rL302913: [SPARC] Support 'f' and 'e' inline asm constraints.
(authored by jyknight).
Changed prior to commit:
https://reviews.llvm.org/D29117?vs=85708=98782#toc
Repository:
rL LLVM
sdardis added a comment.
> How do I create full-context-patches? Does this mean just more context lines?
> Like 500 or 1000 lines?
http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface
https://reviews.llvm.org/D29117
___
pboettch added a comment.
On SparcV8 there is no %e register.
Regarding soft-float, good question, I'll try.
How do I create full-context-patches? Does this mean just more context lines?
Like 500 or 1000 lines?
https://reviews.llvm.org/D29117
bruno added a comment.
Hi,
Thanks for working on this. Few questions:
- What happens with the validation if +soft-float is used?
- What about the 'e' mode, can you double check if the sparc backend support
these instructions? If so it might be interesting to add it here.
Also, please attach
pboettch updated this revision to Diff 85708.
pboettch added a comment.
Added test-code.
https://reviews.llvm.org/D29117
Files:
lib/Basic/Targets.cpp
test/CodeGen/sparcv8-inline-asm.c
Index: test/CodeGen/sparcv8-inline-asm.c
pboettch created this revision.
Herald added a subscriber: jyknight.
Make clang recognize floating point registers in inline assembler
when using the targeting Sparc.
This code now works:
static inline float fabsf(float a)
{
float res;
__asm __volatile__("fabss %1, %0;"
