[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

2018-01-13 Thread Alex Bradbury via Phabricator via cfe-commits 
asb added a comment.

Hi Petr, thanks for the report. This should be addressed in 
https://reviews.llvm.org/rL322435.


Repository:
  rC Clang

https://reviews.llvm.org/D39963



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[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

2018-01-12 Thread Petr Hosek via Phabricator via cfe-commits 
phosek added a comment.
Herald added a subscriber: niosHD.

This has broken our toolchain build, the log is here: 
https://logs.chromium.org/v/?s=fuchsia%2Fbuildbucket%2Fcr-buildbucket.appspot.com%2F8957686819564148864%2F%2B%2Fsteps%2Fcheck_clang%2F0%2Fstdout.
 The failure is:

   TEST 'Clang :: Driver/riscv32-toolchain.c' FAILED 

  Script:
  --
  /b/s/w/ir/tmp/rt/clangM7g4Ie/llvm_build_dir/tools/clang/stage2-bins/bin/clang 
/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/riscv32-toolchain.c 
-### -no-canonical-prefixes -target riscv32 2>&1 | 
/b/s/w/ir/tmp/rt/clangM7g4Ie/llvm_build_dir/tools/clang/stage2-bins/bin/FileCheck
 -check-prefix=CC1 
/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/riscv32-toolchain.c
  /b/s/w/ir/tmp/rt/clangM7g4Ie/llvm_build_dir/tools/clang/stage2-bins/bin/clang 
/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/riscv32-toolchain.c 
-### -no-canonical-prefixes-target riscv32-linux-unknown-elf
--gcc-toolchain=/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/Inputs/multilib_riscv_linux_sdk

--sysroot=/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot
 2>&1| 
/b/s/w/ir/tmp/rt/clangM7g4Ie/llvm_build_dir/tools/clang/stage2-bins/bin/FileCheck
 -check-prefix=CC1-RV32-LINUX-ILP32 
/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/riscv32-toolchain.c
  /b/s/w/ir/tmp/rt/clangM7g4Ie/llvm_build_dir/tools/clang/stage2-bins/bin/clang 
/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/riscv32-toolchain.c 
-### -no-canonical-prefixes-target riscv32-linux-unknown-elf 
-march=rv32imafd -mabi=ilp32d
--gcc-toolchain=/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/Inputs/multilib_riscv_linux_sdk

--sysroot=/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot
 2>&1| 
/b/s/w/ir/tmp/rt/clangM7g4Ie/llvm_build_dir/tools/clang/stage2-bins/bin/FileCheck
 -check-prefix=CC1-RV32-LINUX-ILP32D 
/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/riscv32-toolchain.c
  /b/s/w/ir/tmp/rt/clangM7g4Ie/llvm_build_dir/tools/clang/stage2-bins/bin/clang 
-target riscv32 
/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/riscv32-toolchain.c 
-emit-llvm -S -o - | 
/b/s/w/ir/tmp/rt/clangM7g4Ie/llvm_build_dir/tools/clang/stage2-bins/bin/FileCheck
 /b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/riscv32-toolchain.c
  --
  Exit Code: 1
  Command Output (stderr):
  --
  
/b/s/w/ir/kitchen-workdir/llvm-project/clang/test/Driver/riscv32-toolchain.c:13:26:
 error: expected string not found in input
  // CC1-RV32-LINUX-ILP32: 
"{{.*}}/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/../../../../riscv64-unknown-linux-gnu/bin{{/|}}ld"
   ^
  :1:1: note: scanning from here
  Fuchsia clang version 7.0.0 
(https://fuchsia.googlesource.com/a/third_party/clang 
6d538af698b9b96bc18bfbe62173dca1c103aaca) 
(https://fuchsia.googlesource.com/a/third_party/llvm 
0b5677cbf87647986caf9fa818adb7f8c355cf1f) (based on LLVM 7.0.0svn)
  ^
  --

I think the problem is that in our toolchain, we configure LLD as the default 
linker which is why that check is failing.


Repository:
  rC Clang

https://reviews.llvm.org/D39963



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[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

2018-01-11 Thread Alex Bradbury via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rC322276: [RISCV] Add the RISCV target and compiler driver 
(authored by asb, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D39963?vs=126771=129436#toc

Repository:
  rC Clang

https://reviews.llvm.org/D39963

Files:
  lib/Basic/CMakeLists.txt
  lib/Basic/Targets.cpp
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  lib/Driver/CMakeLists.txt
  lib/Driver/ToolChains/Arch/RISCV.cpp
  lib/Driver/ToolChains/Arch/RISCV.h
  lib/Driver/ToolChains/Clang.cpp
  lib/Driver/ToolChains/Clang.h
  lib/Driver/ToolChains/Gnu.cpp
  lib/Driver/ToolChains/Linux.cpp
  test/Driver/Inputs/multilib_riscv_linux_sdk/bin/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/include/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/riscv64-unknown-linux-gnu/bin/ld
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib32/ilp32/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib32/ilp32d/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64d/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32d/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64d/.keep
  test/Driver/frame-pointer.c
  test/Driver/riscv-abi.c
  test/Driver/riscv-features.c
  test/Driver/riscv32-toolchain.c
  test/Driver/riscv64-toolchain.c
  test/Preprocessor/init.c

Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -10003,3 +10003,398 @@
 // ARM-DARWIN-BAREMETAL-64: #define __PTRDIFF_TYPE__ long int
 // ARM-DARWIN-BAREMETAL-64: #define __SIZE_TYPE__ long unsigned int
 
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=riscv32 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix=RISCV32 %s
+// RISCV32: #define _ILP32 1
+// RISCV32: #define __ATOMIC_ACQUIRE 2
+// RISCV32: #define __ATOMIC_ACQ_REL 4
+// RISCV32: #define __ATOMIC_CONSUME 1
+// RISCV32: #define __ATOMIC_RELAXED 0
+// RISCV32: #define __ATOMIC_RELEASE 3
+// RISCV32: #define __ATOMIC_SEQ_CST 5
+// RISCV32: #define __BIGGEST_ALIGNMENT__ 16
+// RISCV32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// RISCV32: #define __CHAR16_TYPE__ unsigned short
+// RISCV32: #define __CHAR32_TYPE__ unsigned int
+// RISCV32: #define __CHAR_BIT__ 8
+// RISCV32: #define __DBL_DECIMAL_DIG__ 17
+// RISCV32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// RISCV32: #define __DBL_DIG__ 15
+// RISCV32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// RISCV32: #define __DBL_HAS_DENORM__ 1
+// RISCV32: #define __DBL_HAS_INFINITY__ 1
+// RISCV32: #define __DBL_HAS_QUIET_NAN__ 1
+// RISCV32: #define __DBL_MANT_DIG__ 53
+// RISCV32: #define __DBL_MAX_10_EXP__ 308
+// RISCV32: #define __DBL_MAX_EXP__ 1024
+// RISCV32: #define __DBL_MAX__ 1.7976931348623157e+308
+// RISCV32: #define __DBL_MIN_10_EXP__ (-307)
+// RISCV32: #define __DBL_MIN_EXP__ (-1021)
+// RISCV32: #define __DBL_MIN__ 2.2250738585072014e-308
+// RISCV32: #define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__
+// RISCV32: #define __ELF__ 1
+// RISCV32: #define __FINITE_MATH_ONLY__ 0
+// RISCV32: #define __FLT_DECIMAL_DIG__ 9
+// RISCV32: #define __FLT_DENORM_MIN__ 1.40129846e-45F
+// RISCV32: #define __FLT_DIG__ 6
+// RISCV32: #define __FLT_EPSILON__ 1.19209290e-7F
+// RISCV32: #define __FLT_EVAL_METHOD__ 0
+// RISCV32: #define __FLT_HAS_DENORM__ 1
+// RISCV32: #define __FLT_HAS_INFINITY__ 1
+// RISCV32: #define __FLT_HAS_QUIET_NAN__ 1
+// RISCV32: #define __FLT_MANT_DIG__ 24
+// RISCV32: #define __FLT_MAX_10_EXP__ 38
+// RISCV32: #define __FLT_MAX_EXP__ 128
+// RISCV32: #define __FLT_MAX__ 3.40282347e+38F
+// RISCV32: #define __FLT_MIN_10_EXP__ (-37)
+// RISCV32: #define __FLT_MIN_EXP__ (-125)
+// RISCV32: #define __FLT_MIN__ 1.17549435e-38F
+// RISCV32: #define __FLT_RADIX__ 2
+// RISCV32: #define __GCC_ATOMIC_BOOL_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_CHAR_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_INT_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_LONG_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_POINTER_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_SHORT_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// RISCV32: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 1
+// RISCV32: #define __GNUC_MINOR__ {{.*}}
+// RISCV32: #define __GNUC_PATCHLEVEL__ {{.*}}
+// RISCV32: #define __GNUC_STDC_INLINE__ 1
+// RISCV32: #define __GNUC__ {{.*}}
+// RISCV32: #define __GXX_ABI_VERSION {{.*}}
+//

[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

2018-01-08 Thread Ana Pazos via Phabricator via cfe-commits 
apazos accepted this revision.
apazos added a comment.
This revision is now accepted and ready to land.

Please merge this patch, it looks in good shape. This patch is required for any 
RISCV build.


https://reviews.llvm.org/D39963



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[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

2017-12-13 Thread Eli Friedman via Phabricator via cfe-commits 
efriedma added reviewers: mgorny, efriedma, bkramer, sylvestre.ledru.
efriedma added a comment.

Adding some reviewers to hopefully find someone comfortable reviewing the Linux 
multilib bits.  (Not sure I'm adding the right people; this stuff hasn't been 
touched for a while, as far as I can tell.)

The rest LGTM.


https://reviews.llvm.org/D39963



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[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

2017-12-13 Thread Alex Bradbury via Phabricator via cfe-commits 
asb updated this revision to Diff 126771.
asb added a comment.

Apologies, the last version had a few lines of debug code left in.

I should say that this is to the best of my knowledge ready to merge (i.e. 
there are no outstanding flagged issues). Particularly now that the majority of 
the RV32I codegen patches are merged in LLVM, it would be really helpful to get 
this merged in to clang asap in order to make larger scale testing of the LLVM 
backend possible without out-of-tree patches.


https://reviews.llvm.org/D39963

Files:
  lib/Basic/CMakeLists.txt
  lib/Basic/Targets.cpp
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  lib/Driver/CMakeLists.txt
  lib/Driver/ToolChains/Arch/RISCV.cpp
  lib/Driver/ToolChains/Arch/RISCV.h
  lib/Driver/ToolChains/Clang.cpp
  lib/Driver/ToolChains/Clang.h
  lib/Driver/ToolChains/Gnu.cpp
  lib/Driver/ToolChains/Linux.cpp
  test/Driver/Inputs/multilib_riscv_linux_sdk/bin/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/include/.keep
  
test/Driver/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/crtbegin.o
  
test/Driver/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/lib32/ilp32/crtbegin.o
  
test/Driver/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/lib32/ilp32d/crtbegin.o
  
test/Driver/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/lib64/lp64/crtbegin.o
  
test/Driver/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/lib64/lp64d/crtbegin.o
  test/Driver/Inputs/multilib_riscv_linux_sdk/riscv64-unknown-linux-gnu/bin/ld
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib32/ilp32/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib32/ilp32d/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64d/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32d/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64d/.keep
  test/Driver/frame-pointer.c
  test/Driver/riscv-abi.c
  test/Driver/riscv-features.c
  test/Driver/riscv32-toolchain.c
  test/Driver/riscv64-toolchain.c
  test/Preprocessor/init.c

Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -10003,3 +10003,398 @@
 // ARM-DARWIN-BAREMETAL-64: #define __PTRDIFF_TYPE__ long int
 // ARM-DARWIN-BAREMETAL-64: #define __SIZE_TYPE__ long unsigned int
 
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=riscv32 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix=RISCV32 %s
+// RISCV32: #define _ILP32 1
+// RISCV32: #define __ATOMIC_ACQUIRE 2
+// RISCV32: #define __ATOMIC_ACQ_REL 4
+// RISCV32: #define __ATOMIC_CONSUME 1
+// RISCV32: #define __ATOMIC_RELAXED 0
+// RISCV32: #define __ATOMIC_RELEASE 3
+// RISCV32: #define __ATOMIC_SEQ_CST 5
+// RISCV32: #define __BIGGEST_ALIGNMENT__ 16
+// RISCV32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// RISCV32: #define __CHAR16_TYPE__ unsigned short
+// RISCV32: #define __CHAR32_TYPE__ unsigned int
+// RISCV32: #define __CHAR_BIT__ 8
+// RISCV32: #define __DBL_DECIMAL_DIG__ 17
+// RISCV32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// RISCV32: #define __DBL_DIG__ 15
+// RISCV32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// RISCV32: #define __DBL_HAS_DENORM__ 1
+// RISCV32: #define __DBL_HAS_INFINITY__ 1
+// RISCV32: #define __DBL_HAS_QUIET_NAN__ 1
+// RISCV32: #define __DBL_MANT_DIG__ 53
+// RISCV32: #define __DBL_MAX_10_EXP__ 308
+// RISCV32: #define __DBL_MAX_EXP__ 1024
+// RISCV32: #define __DBL_MAX__ 1.7976931348623157e+308
+// RISCV32: #define __DBL_MIN_10_EXP__ (-307)
+// RISCV32: #define __DBL_MIN_EXP__ (-1021)
+// RISCV32: #define __DBL_MIN__ 2.2250738585072014e-308
+// RISCV32: #define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__
+// RISCV32: #define __ELF__ 1
+// RISCV32: #define __FINITE_MATH_ONLY__ 0
+// RISCV32: #define __FLT_DECIMAL_DIG__ 9
+// RISCV32: #define __FLT_DENORM_MIN__ 1.40129846e-45F
+// RISCV32: #define __FLT_DIG__ 6
+// RISCV32: #define __FLT_EPSILON__ 1.19209290e-7F
+// RISCV32: #define __FLT_EVAL_METHOD__ 0
+// RISCV32: #define __FLT_HAS_DENORM__ 1
+// RISCV32: #define __FLT_HAS_INFINITY__ 1
+// RISCV32: #define __FLT_HAS_QUIET_NAN__ 1
+// RISCV32: #define __FLT_MANT_DIG__ 24
+// RISCV32: #define __FLT_MAX_10_EXP__ 38
+// RISCV32: #define __FLT_MAX_EXP__ 128
+// RISCV32: #define __FLT_MAX__ 3.40282347e+38F
+// RISCV32: #define __FLT_MIN_10_EXP__ (-37)
+// RISCV32: #define __FLT_MIN_EXP__ (-125)
+// RISCV32: #define __FLT_MIN__ 1.17549435e-38F
+// RISCV32: #define __FLT_RADIX__ 2
+// RISCV32: #define __GCC_ATOMIC_BOOL_LOCK_FREE 1
+//

[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

2017-12-13 Thread Alex Bradbury via Phabricator via cfe-commits 
asb updated this revision to Diff 126769.
asb edited the summary of this revision.
asb added a comment.

Update to add test cases based on the multilib Linux SDK produced by 
https://github.com/riscv/riscv-gnu-toolchain/.


https://reviews.llvm.org/D39963

Files:
  lib/Basic/CMakeLists.txt
  lib/Basic/Targets.cpp
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  lib/Driver/CMakeLists.txt
  lib/Driver/ToolChains/Arch/RISCV.cpp
  lib/Driver/ToolChains/Arch/RISCV.h
  lib/Driver/ToolChains/Clang.cpp
  lib/Driver/ToolChains/Clang.h
  lib/Driver/ToolChains/Gnu.cpp
  lib/Driver/ToolChains/Linux.cpp
  test/Driver/Inputs/multilib_riscv_linux_sdk/bin/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/include/.keep
  
test/Driver/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/crtbegin.o
  
test/Driver/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/lib32/ilp32/crtbegin.o
  
test/Driver/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/lib32/ilp32d/crtbegin.o
  
test/Driver/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/lib64/lp64/crtbegin.o
  
test/Driver/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/lib64/lp64d/crtbegin.o
  test/Driver/Inputs/multilib_riscv_linux_sdk/riscv64-unknown-linux-gnu/bin/ld
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib32/ilp32/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib32/ilp32d/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64d/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32d/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64/.keep
  test/Driver/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64d/.keep
  test/Driver/frame-pointer.c
  test/Driver/riscv-abi.c
  test/Driver/riscv-features.c
  test/Driver/riscv32-toolchain.c
  test/Driver/riscv64-toolchain.c
  test/Preprocessor/init.c

Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -10003,3 +10003,398 @@
 // ARM-DARWIN-BAREMETAL-64: #define __PTRDIFF_TYPE__ long int
 // ARM-DARWIN-BAREMETAL-64: #define __SIZE_TYPE__ long unsigned int
 
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=riscv32 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix=RISCV32 %s
+// RISCV32: #define _ILP32 1
+// RISCV32: #define __ATOMIC_ACQUIRE 2
+// RISCV32: #define __ATOMIC_ACQ_REL 4
+// RISCV32: #define __ATOMIC_CONSUME 1
+// RISCV32: #define __ATOMIC_RELAXED 0
+// RISCV32: #define __ATOMIC_RELEASE 3
+// RISCV32: #define __ATOMIC_SEQ_CST 5
+// RISCV32: #define __BIGGEST_ALIGNMENT__ 16
+// RISCV32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// RISCV32: #define __CHAR16_TYPE__ unsigned short
+// RISCV32: #define __CHAR32_TYPE__ unsigned int
+// RISCV32: #define __CHAR_BIT__ 8
+// RISCV32: #define __DBL_DECIMAL_DIG__ 17
+// RISCV32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// RISCV32: #define __DBL_DIG__ 15
+// RISCV32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// RISCV32: #define __DBL_HAS_DENORM__ 1
+// RISCV32: #define __DBL_HAS_INFINITY__ 1
+// RISCV32: #define __DBL_HAS_QUIET_NAN__ 1
+// RISCV32: #define __DBL_MANT_DIG__ 53
+// RISCV32: #define __DBL_MAX_10_EXP__ 308
+// RISCV32: #define __DBL_MAX_EXP__ 1024
+// RISCV32: #define __DBL_MAX__ 1.7976931348623157e+308
+// RISCV32: #define __DBL_MIN_10_EXP__ (-307)
+// RISCV32: #define __DBL_MIN_EXP__ (-1021)
+// RISCV32: #define __DBL_MIN__ 2.2250738585072014e-308
+// RISCV32: #define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__
+// RISCV32: #define __ELF__ 1
+// RISCV32: #define __FINITE_MATH_ONLY__ 0
+// RISCV32: #define __FLT_DECIMAL_DIG__ 9
+// RISCV32: #define __FLT_DENORM_MIN__ 1.40129846e-45F
+// RISCV32: #define __FLT_DIG__ 6
+// RISCV32: #define __FLT_EPSILON__ 1.19209290e-7F
+// RISCV32: #define __FLT_EVAL_METHOD__ 0
+// RISCV32: #define __FLT_HAS_DENORM__ 1
+// RISCV32: #define __FLT_HAS_INFINITY__ 1
+// RISCV32: #define __FLT_HAS_QUIET_NAN__ 1
+// RISCV32: #define __FLT_MANT_DIG__ 24
+// RISCV32: #define __FLT_MAX_10_EXP__ 38
+// RISCV32: #define __FLT_MAX_EXP__ 128
+// RISCV32: #define __FLT_MAX__ 3.40282347e+38F
+// RISCV32: #define __FLT_MIN_10_EXP__ (-37)
+// RISCV32: #define __FLT_MIN_EXP__ (-125)
+// RISCV32: #define __FLT_MIN__ 1.17549435e-38F
+// RISCV32: #define __FLT_RADIX__ 2
+// RISCV32: #define __GCC_ATOMIC_BOOL_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_CHAR_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_INT_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// RISCV32: #define

[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

2017-12-11 Thread Alex Bradbury via Phabricator via cfe-commits 
asb updated this revision to Diff 126404.
asb marked 3 inline comments as done.
asb retitled this revision from "[RISCV][RFC] Add initial RISC-V target and 
driver support" to "[RISCV] Add initial RISC-V target and driver support".
asb edited the summary of this revision.
asb added a comment.
Herald added a subscriber: sabuasal.

Patch updates:

- Address review comments
- (u)int64_type is `long int` on RV64 rather than `long long int`
- Remove driver for bare metal RV32 target (to be posted in a subsequent patch 
and maybe discussed on cfe-dev).

>From my perspective, the only deficiency in this patch is now the tests (which 
>I'll add to this review ASAP). Let me know if you see other remaining problems.


https://reviews.llvm.org/D39963

Files:
  lib/Basic/CMakeLists.txt
  lib/Basic/Targets.cpp
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  lib/Driver/CMakeLists.txt
  lib/Driver/ToolChains/Arch/RISCV.cpp
  lib/Driver/ToolChains/Arch/RISCV.h
  lib/Driver/ToolChains/Clang.cpp
  lib/Driver/ToolChains/Clang.h
  lib/Driver/ToolChains/Gnu.cpp
  lib/Driver/ToolChains/Linux.cpp
  test/Driver/frame-pointer.c
  test/Driver/riscv-abi.c
  test/Driver/riscv-features.c
  test/Driver/riscv32-toolchain.c
  test/Driver/riscv64-toolchain.c
  test/Preprocessor/init.c

Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -10003,3 +10003,398 @@
 // ARM-DARWIN-BAREMETAL-64: #define __PTRDIFF_TYPE__ long int
 // ARM-DARWIN-BAREMETAL-64: #define __SIZE_TYPE__ long unsigned int
 
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=riscv32 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix=RISCV32 %s
+// RISCV32: #define _ILP32 1
+// RISCV32: #define __ATOMIC_ACQUIRE 2
+// RISCV32: #define __ATOMIC_ACQ_REL 4
+// RISCV32: #define __ATOMIC_CONSUME 1
+// RISCV32: #define __ATOMIC_RELAXED 0
+// RISCV32: #define __ATOMIC_RELEASE 3
+// RISCV32: #define __ATOMIC_SEQ_CST 5
+// RISCV32: #define __BIGGEST_ALIGNMENT__ 16
+// RISCV32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// RISCV32: #define __CHAR16_TYPE__ unsigned short
+// RISCV32: #define __CHAR32_TYPE__ unsigned int
+// RISCV32: #define __CHAR_BIT__ 8
+// RISCV32: #define __DBL_DECIMAL_DIG__ 17
+// RISCV32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// RISCV32: #define __DBL_DIG__ 15
+// RISCV32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// RISCV32: #define __DBL_HAS_DENORM__ 1
+// RISCV32: #define __DBL_HAS_INFINITY__ 1
+// RISCV32: #define __DBL_HAS_QUIET_NAN__ 1
+// RISCV32: #define __DBL_MANT_DIG__ 53
+// RISCV32: #define __DBL_MAX_10_EXP__ 308
+// RISCV32: #define __DBL_MAX_EXP__ 1024
+// RISCV32: #define __DBL_MAX__ 1.7976931348623157e+308
+// RISCV32: #define __DBL_MIN_10_EXP__ (-307)
+// RISCV32: #define __DBL_MIN_EXP__ (-1021)
+// RISCV32: #define __DBL_MIN__ 2.2250738585072014e-308
+// RISCV32: #define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__
+// RISCV32: #define __ELF__ 1
+// RISCV32: #define __FINITE_MATH_ONLY__ 0
+// RISCV32: #define __FLT_DECIMAL_DIG__ 9
+// RISCV32: #define __FLT_DENORM_MIN__ 1.40129846e-45F
+// RISCV32: #define __FLT_DIG__ 6
+// RISCV32: #define __FLT_EPSILON__ 1.19209290e-7F
+// RISCV32: #define __FLT_EVAL_METHOD__ 0
+// RISCV32: #define __FLT_HAS_DENORM__ 1
+// RISCV32: #define __FLT_HAS_INFINITY__ 1
+// RISCV32: #define __FLT_HAS_QUIET_NAN__ 1
+// RISCV32: #define __FLT_MANT_DIG__ 24
+// RISCV32: #define __FLT_MAX_10_EXP__ 38
+// RISCV32: #define __FLT_MAX_EXP__ 128
+// RISCV32: #define __FLT_MAX__ 3.40282347e+38F
+// RISCV32: #define __FLT_MIN_10_EXP__ (-37)
+// RISCV32: #define __FLT_MIN_EXP__ (-125)
+// RISCV32: #define __FLT_MIN__ 1.17549435e-38F
+// RISCV32: #define __FLT_RADIX__ 2
+// RISCV32: #define __GCC_ATOMIC_BOOL_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_CHAR_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_INT_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_LONG_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_POINTER_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_SHORT_LOCK_FREE 1
+// RISCV32: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// RISCV32: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 1
+// RISCV32: #define __GNUC_MINOR__ {{.*}}
+// RISCV32: #define __GNUC_PATCHLEVEL__ {{.*}}
+// RISCV32: #define __GNUC_STDC_INLINE__ 1
+// RISCV32: #define __GNUC__ {{.*}}
+// RISCV32: #define __GXX_ABI_VERSION {{.*}}
+// RISCV32: #define __ILP32__ 1
+// RISCV32: #define __INT16_C_SUFFIX__
+// RISCV32: #define __INT16_MAX__ 32767
+// RISCV32: #define __INT16_TYPE__ short
+// RISCV32: #define __INT32_C_SUFFIX__
+// RISCV32: #define __INT32_MAX__ 2147483647
+// RISCV32: #define __INT32_TYPE__ int
+// RISCV32: #define __INT64_C_SUFFIX__ LL
+// RISCV32: #define __INT64_MAX__ 9223372036854775807LL
+// RISCV32: #define __INT64_TYPE__ long long int