[PATCH] D43911: [AMDGPU] Clean up old address space mapping and fix constant address space value
This revision was automatically updated to reflect the committed changes.
Closed by commit rL326725: [AMDGPU] Clean up old address space mapping and fix
constant address space value (authored by yaxunl, committed by ).
Herald added a subscriber: llvm-commits.
Changed prior to commit:
https://reviews.llvm.org/D43911?vs=136394=137031#toc
Repository:
rL LLVM
https://reviews.llvm.org/D43911
Files:
cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
cfe/trunk/lib/Basic/Targets/AMDGPU.h
cfe/trunk/test/CodeGenCXX/cxx0x-initializer-stdinitializerlist.cpp
Index: cfe/trunk/lib/Basic/Targets/AMDGPU.h
===
--- cfe/trunk/lib/Basic/Targets/AMDGPU.h
+++ cfe/trunk/lib/Basic/Targets/AMDGPU.h
@@ -28,24 +28,15 @@
static const Builtin::Info BuiltinInfo[];
static const char *const GCCRegNames[];
- struct LLVM_LIBRARY_VISIBILITY AddrSpace {
-unsigned Generic, Global, Local, Constant, Private;
-AddrSpace(bool IsGenericZero_ = false) {
- if (IsGenericZero_) {
-Generic = 0;
-Global = 1;
-Local = 3;
-Constant = 2;
-Private = 5;
- } else {
-Generic = 4;
-Global = 1;
-Local = 3;
-Constant = 2;
-Private = 0;
- }
-}
+ enum AddrSpace {
+Generic = 0,
+Global = 1,
+Local = 3,
+Constant = 4,
+Private = 5
};
+ static const LangASMap AMDGPUDefIsGenMap;
+ static const LangASMap AMDGPUDefIsPrivMap;
/// \brief GPU kinds supported by the AMDGPU target.
enum GPUKind : uint32_t {
@@ -178,15 +169,12 @@
GPUInfo parseGPUName(StringRef Name) const;
- const AddrSpace AS;
GPUInfo GPU;
static bool isAMDGCN(const llvm::Triple ) {
return TT.getArch() == llvm::Triple::amdgcn;
}
- static bool isGenericZero(const llvm::Triple ) { return true; }
-
public:
AMDGPUTargetInfo(const llvm::Triple , const TargetOptions );
@@ -197,7 +185,7 @@
uint64_t getPointerWidthV(unsigned AddrSpace) const override {
if (GPU.Kind <= GK_R600_LAST)
return 32;
-if (AddrSpace == AS.Private || AddrSpace == AS.Local)
+if (AddrSpace == Private || AddrSpace == Local)
return 32;
return 64;
}
@@ -374,11 +362,13 @@
}
llvm::Optional getConstantAddressSpace() const override {
-return getLangASFromTargetAS(AS.Constant);
+return getLangASFromTargetAS(Constant);
}
/// \returns Target specific vtbl ptr address space.
- unsigned getVtblPtrAddressSpace() const override { return AS.Constant; }
+ unsigned getVtblPtrAddressSpace() const override {
+return static_cast(Constant);
+ }
/// \returns If a target requires an address within a target specific address
/// space \p AddressSpace to be converted in order to be used, then return the
@@ -390,9 +380,9 @@
getDWARFAddressSpace(unsigned AddressSpace) const override {
const unsigned DWARF_Private = 1;
const unsigned DWARF_Local = 2;
-if (AddressSpace == AS.Private) {
+if (AddressSpace == Private) {
return DWARF_Private;
-} else if (AddressSpace == AS.Local) {
+} else if (AddressSpace == Local) {
return DWARF_Local;
} else {
return None;
Index: cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
===
--- cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
+++ cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
@@ -32,62 +32,33 @@
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
-static const char *const DataLayoutStringSIPrivateIsZero =
-"e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
-"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
-"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
-
-static const char *const DataLayoutStringSIGenericIsZero =
+static const char *const DataLayoutStringAMDGCN =
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
-static const LangASMap AMDGPUPrivIsZeroDefIsGenMap = {
-4, // Default
-1, // opencl_global
-3, // opencl_local
-4, // opencl_constant
-0, // opencl_private
-4, // opencl_generic
-1, // cuda_device
-4, // cuda_constant
-3 // cuda_shared
-};
-
-static const LangASMap AMDGPUGenIsZeroDefIsGenMap = {
-0, // Default
-1, // opencl_global
-3, // opencl_local
-4, // opencl_constant
-5, // opencl_private
-0, // opencl_generic
-1, // cuda_device
-4, // cuda_constant
-3 // cuda_shared
+const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = {
+Generic, // Default
+Global, // opencl_global
+Local,// opencl_local
+Constant, // opencl_constant
+Private, // opencl_private
+Generic, // opencl_generic
+Global, // cuda_device
+Constant, // cuda_constant
+Local
[PATCH] D43911: [AMDGPU] Clean up old address space mapping and fix constant address space value
yaxunl added a comment. Will make recommended changes when committing. https://reviews.llvm.org/D43911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43911: [AMDGPU] Clean up old address space mapping and fix constant address space value
t-tye accepted this revision. t-tye added a comment. This revision is now accepted and ready to land. LGTM except minor comment. Comment at: lib/Basic/Targets/AMDGPU.cpp:41-49 0, // Default 1, // opencl_global 3, // opencl_local 4, // opencl_constant 5, // opencl_private 0, // opencl_generic 1, // cuda_device Could the values be the AddrSpace enumerators? Comment at: lib/Basic/Targets/AMDGPU.cpp:53-61 5, // Default 1, // opencl_global 3, // opencl_local 4, // opencl_constant 5, // opencl_private 0, // opencl_generic 1, // cuda_device Could the values be the AddrSpace enumerators? Comment at: lib/Basic/Targets/AMDGPU.cpp:254 } - auto IsGenericZero = isGenericZero(Triple); resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn + ? DataLayoutStringAMDGCN To be consistent should this be: ``` !isAMDGCN(getTriple()) ``` https://reviews.llvm.org/D43911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43911: [AMDGPU] Clean up old address space mapping and fix constant address space value
b-sumner added a comment. Looks fine to me. https://reviews.llvm.org/D43911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43911: [AMDGPU] Clean up old address space mapping and fix constant address space value
yaxunl added a comment. Ping https://reviews.llvm.org/D43911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43911: [AMDGPU] Clean up old address space mapping and fix constant address space value
yaxunl created this revision.
yaxunl added reviewers: t-tye, b-sumner, arsenm.
Herald added subscribers: tpr, dstuttard, nhaehnle, wdng, kzhuravl.
https://reviews.llvm.org/D43911
Files:
lib/Basic/Targets/AMDGPU.cpp
lib/Basic/Targets/AMDGPU.h
test/CodeGenCXX/cxx0x-initializer-stdinitializerlist.cpp
Index: test/CodeGenCXX/cxx0x-initializer-stdinitializerlist.cpp
===
--- test/CodeGenCXX/cxx0x-initializer-stdinitializerlist.cpp
+++ test/CodeGenCXX/cxx0x-initializer-stdinitializerlist.cpp
@@ -78,17 +78,17 @@
// X86: @[[PARTLY_CONSTANT_SECOND:_ZGRN15partly_constant2ilE.*]] = internal global [2 x i32] zeroinitializer, align 4
// X86: @[[PARTLY_CONSTANT_THIRD:_ZGRN15partly_constant2ilE.*]] = internal constant [4 x i32] [i32 5, i32 6, i32 7, i32 8], align 4
// AMDGCN: @_ZN15partly_constant1kE = addrspace(1) global i32 0, align 4
-// AMDGCN: @_ZN15partly_constant2ilE = addrspace(2) global {{.*}} null, align 8
-// AMDGCN: @[[PARTLY_CONSTANT_OUTER:_ZGRN15partly_constant2ilE.*]] = internal addrspace(2) global {{.*}} zeroinitializer, align 8
-// AMDGCN: @[[PARTLY_CONSTANT_INNER:_ZGRN15partly_constant2ilE.*]] = internal addrspace(2) global [3 x {{.*}}] zeroinitializer, align 8
-// AMDGCN: @[[PARTLY_CONSTANT_FIRST:_ZGRN15partly_constant2ilE.*]] = internal addrspace(2) constant [3 x i32] [i32 1, i32 2, i32 3], align 4
-// AMDGCN: @[[PARTLY_CONSTANT_SECOND:_ZGRN15partly_constant2ilE.*]] = internal addrspace(2) global [2 x i32] zeroinitializer, align 4
-// AMDGCN: @[[PARTLY_CONSTANT_THIRD:_ZGRN15partly_constant2ilE.*]] = internal addrspace(2) constant [4 x i32] [i32 5, i32 6, i32 7, i32 8], align 4
+// AMDGCN: @_ZN15partly_constant2ilE = addrspace(4) global {{.*}} null, align 8
+// AMDGCN: @[[PARTLY_CONSTANT_OUTER:_ZGRN15partly_constant2ilE.*]] = internal addrspace(4) global {{.*}} zeroinitializer, align 8
+// AMDGCN: @[[PARTLY_CONSTANT_INNER:_ZGRN15partly_constant2ilE.*]] = internal addrspace(4) global [3 x {{.*}}] zeroinitializer, align 8
+// AMDGCN: @[[PARTLY_CONSTANT_FIRST:_ZGRN15partly_constant2ilE.*]] = internal addrspace(4) constant [3 x i32] [i32 1, i32 2, i32 3], align 4
+// AMDGCN: @[[PARTLY_CONSTANT_SECOND:_ZGRN15partly_constant2ilE.*]] = internal addrspace(4) global [2 x i32] zeroinitializer, align 4
+// AMDGCN: @[[PARTLY_CONSTANT_THIRD:_ZGRN15partly_constant2ilE.*]] = internal addrspace(4) constant [4 x i32] [i32 5, i32 6, i32 7, i32 8], align 4
// X86: @[[REFTMP1:.*]] = private constant [2 x i32] [i32 42, i32 43], align 4
// X86: @[[REFTMP2:.*]] = private constant [3 x %{{.*}}] [%{{.*}} { i32 1 }, %{{.*}} { i32 2 }, %{{.*}} { i32 3 }], align 4
-// AMDGCN: @[[REFTMP1:.*]] = private addrspace(2) constant [2 x i32] [i32 42, i32 43], align 4
-// AMDGCN: @[[REFTMP2:.*]] = private addrspace(2) constant [3 x %{{.*}}] [%{{.*}} { i32 1 }, %{{.*}} { i32 2 }, %{{.*}} { i32 3 }], align 4
+// AMDGCN: @[[REFTMP1:.*]] = private addrspace(4) constant [2 x i32] [i32 42, i32 43], align 4
+// AMDGCN: @[[REFTMP2:.*]] = private addrspace(4) constant [3 x %{{.*}}] [%{{.*}} { i32 1 }, %{{.*}} { i32 2 }, %{{.*}} { i32 3 }], align 4
// CHECK: appending global
@@ -518,7 +518,7 @@
// CHECK-LABEL: @_ZN9B197730102f1Ev
testcase a{{"", ENUM_CONSTANT}};
// X86: store %"struct.B19773010::pair"* getelementptr inbounds ([1 x %"struct.B19773010::pair"], [1 x %"struct.B19773010::pair"]* bitcast ([1 x { i8*, i32 }]* @.ref.tmp{{.*}} to [1 x %"struct.B19773010::pair"]*), i64 0, i64 0), %"struct.B19773010::pair"** %{{.*}}, align 8
-// AMDGCN: store %"struct.B19773010::pair"* getelementptr inbounds ([1 x %"struct.B19773010::pair"], [1 x %"struct.B19773010::pair"]* addrspacecast{{.*}} bitcast ([1 x { i8*, i32 }] addrspace(2)* @.ref.tmp{{.*}} to [1 x %"struct.B19773010::pair"] addrspace(2)*){{.*}}, i64 0, i64 0), %"struct.B19773010::pair"** %{{.*}}, align 8
+// AMDGCN: store %"struct.B19773010::pair"* getelementptr inbounds ([1 x %"struct.B19773010::pair"], [1 x %"struct.B19773010::pair"]* addrspacecast{{.*}} bitcast ([1 x { i8*, i32 }] addrspace(4)* @.ref.tmp{{.*}} to [1 x %"struct.B19773010::pair"] addrspace(4)*){{.*}}, i64 0, i64 0), %"struct.B19773010::pair"** %{{.*}}, align 8
}
void f2() {
// CHECK-LABEL: @_ZN9B197730102f2Ev
Index: lib/Basic/Targets/AMDGPU.h
===
--- lib/Basic/Targets/AMDGPU.h
+++ lib/Basic/Targets/AMDGPU.h
@@ -28,23 +28,12 @@
static const Builtin::Info BuiltinInfo[];
static const char *const GCCRegNames[];
- struct LLVM_LIBRARY_VISIBILITY AddrSpace {
-unsigned Generic, Global, Local, Constant, Private;
-AddrSpace(bool IsGenericZero_ = false) {
- if (IsGenericZero_) {
-Generic = 0;
-Global = 1;
-Local = 3;
-Constant = 2;
-Private = 5;
- } else {
-Generic = 4;
-Global = 1;
-Local = 3;
-Constant = 2;
-Private = 0;
- }
-}
+ enum AddrSpace {
