[PATCH] D59615: [AArch64] When creating SISD intrinsic calls widen scalar args into a zero vectors, not undef

2020-08-14 Thread Amara Emerson via Phabricator via cfe-commits
aemerson abandoned this revision. aemerson added a comment. Seems no one is enthusiastic about this change, so I'm going to drop it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59615/new/ https://reviews.llvm.org/D59615

[PATCH] D59615: [AArch64] When creating SISD intrinsic calls widen scalar args into a zero vectors, not undef

2020-08-11 Thread Eli Friedman via Phabricator via cfe-commits
efriedma added a comment. I see two issues here: 1. We're still generating the wrong instruction. 2. The intrinsic is marked readnone, so any code that depends on whether it sets saturation flags is likely broken anyway. Given the layers of wrongness here, this seems like a marginal

[PATCH] D59615: [AArch64] When creating SISD intrinsic calls widen scalar args into a zero vectors, not undef

2020-08-10 Thread Amara Emerson via Phabricator via cfe-commits
aemerson added a comment. Herald added a subscriber: danielkiss. Does anyone object to this? I'd like to get it off my review dashboard one way or the other. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59615/new/ https://reviews.llvm.org/D59615

[PATCH] D59615: [AArch64] When creating SISD intrinsic calls widen scalar args into a zero vectors, not undef

2019-03-27 Thread Amara Emerson via Phabricator via cfe-commits
aemerson added a comment. Ping. I've filed PR41260 for the code quality issue. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59615/new/ https://reviews.llvm.org/D59615 ___ cfe-commits mailing list

[PATCH] D59615: [AArch64] When creating SISD intrinsic calls widen scalar args into a zero vectors, not undef

2019-03-22 Thread Amara Emerson via Phabricator via cfe-commits
aemerson added a comment. In D59615#1439153 , @t.p.northover wrote: > Did you look into a scalar variant of the intrinsic call instead? These > instructions have non-vector variants (e.g. `sqadd s0, s0, s0`), and that's > actually why the intrinsics

[PATCH] D59615: [AArch64] When creating SISD intrinsic calls widen scalar args into a zero vectors, not undef

2019-03-22 Thread Tim Northover via Phabricator via cfe-commits
t.p.northover added a comment. Did you look into a scalar variant of the intrinsic call instead? These instructions have non-vector variants (e.g. `sqadd s0, s0, s0`), and that's actually why the intrinsics exist in the first place. It'd be a shame to always require this extra work.

[PATCH] D59615: [AArch64] When creating SISD intrinsic calls widen scalar args into a zero vectors, not undef

2019-03-20 Thread Amara Emerson via Phabricator via cfe-commits
aemerson created this revision. aemerson added reviewers: kristof.beyls, t.p.northover, olista01. aemerson added a project: clang. Herald added subscribers: arphaman, javed.absar. Some intrinsics like saturating operations may set flags, so if the scalar arg is inserted into an undef vector, the