[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added a comment. In D70401#4204511 , @recallmenot wrote: > Hi, I'm working on CH32V003 for rust and it uses RV32EC core. > I tried replacing my distros llvm and clang with a patched version of this > like this: > > git clone

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

recallmenot added a comment. Hi, I'm working on CH32V003 for rust and it uses RV32EC core. I tried replacing my distros llvm and clang with a patched version of this like this: git clone https://aur.archlinux.org/llvm-git.git cd llvm-git mkdir src cd src git clone

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added a comment. In D70401#3948829 , @StephenFan wrote: > In D70401#3873874 , @pcwang-thead > wrote: > >> In D70401#3873347 , @luojia wrote: >> >>> Hello! Any

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

StephenFan added a comment. In D70401#3873874 , @pcwang-thead wrote: > In D70401#3873347 , @luojia wrote: > >> Hello! Any further updates to this patch? It seems like all the inline >> comments have been

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead marked an inline comment as done. pcwang-thead added a comment. In D70401#3873347 , @luojia wrote: > Hello! Any further updates to this patch? It seems like all the inline > comments have been resolved. We have done some works in this patch

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

luojia added a comment. Hello! Any further updates to this patch? It seems like all the inline comments have been resolved. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead marked an inline comment as done. pcwang-thead added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:411 // implemented such that the stack will always be 16 byte aligned. unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) *

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

zixuan-wu added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:411 // implemented such that the stack will always be 16 byte aligned. unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

zixuan-wu added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:106 +for (size_t Reg = RISCV::X16; Reg <= RISCV::X31; Reg++) + markSuperRegs(Reserved, Reg); + I am wondering whether we need construct another new RegisterClass

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added a comment. Herald added a subscriber: StephenFan. In D70401#3391561 , @khchen wrote: > I found > https://github.com/llvm/llvm-test-suite/blob/main/SingleSource/UnitTests/2003-05-26-Shorts.c > result is mismatched with gcc's

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added a comment. In D70401#3395340 , @kito-cheng wrote: > Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, > so here is note from my site: > > RISC-V psABI doc still say "we don't guarantee the stability of

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

kito-cheng added a comment. Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, so here is note from my site: RISC-V psABI doc still say "we don't guarantee the stability of `ILP32E`", the reason is RV32E still not a ratified extension, but as psABI chair, what I can

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

kito-cheng added a comment. > If I understand correctly, E can't be combined with D in current > specification since E must use ILP32E calling convention. Calling convention and extensions are separated, calling convention are specify the how argument passing and the register convention, so

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

khchen added a comment. Herald added a subscriber: s. In D70401#3384758 , @pcwang-thead wrote: > In D70401#3250049 , @khchen wrote: > >> 1. please add a check here >>

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead commandeered this revision. pcwang-thead edited reviewers, added: zixuan-wu; removed: pcwang-thead. pcwang-thead added a comment. Herald added a subscriber: arichardson. Herald added a project: All. In D70401#3250049 , @khchen wrote: > 1.

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

khchen added a comment. In D70401#3325419 , @zixuan-wu wrote: > It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there > are no workable environment such as runtime and kernel for ilp32e in GNU > series tools. > And we can not run

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

zixuan-wu added a comment. Sorry for the wrong action of commandeer, @pcwang-thead will still be the author. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 ___

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

zixuan-wu added a comment. It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there are no workable environment such as runtime and kernel for ilp32e in GNU series tools. And we can not run llvm-test-suite in baremental environment(NOT linux but elf triple). So I have a

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

zixuan-wu commandeered this revision. zixuan-wu added a reviewer: pcwang-thead. zixuan-wu added a comment. In D70401#3250049 , @khchen wrote: > 2. Have you try to run llvm-test-suite with rv32e config on qemu? It's difficult to run llvm-test-suite in

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added inline comments. Comment at: llvm/lib/Support/TargetParser.cpp:339 +if (ISAInfo.hasExtension("d")) + return "ilp32d"; return "ilp32"; khchen wrote: > why do we need to change the order? IMO, when `e` is combined with `d`, `e`

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

khchen added a comment. 1. please add a check here and a clang cc1 test for it. 2. Have you try to run llvm-test-suite with rv32e config on qemu?

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added a comment. Herald added subscribers: alextsao1999, eopXD. Gentle ping. We are testing this patch and I'd like to get some nice advice. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added a comment. ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 ___ cfe-commits mailing list cfe-commits@lists.llvm.org