[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

lenary marked an inline comment as done. lenary added a comment. In D70401#3188138 , @zixuan-wu wrote: > In D70401#3175266 , @khchen wrote: > >>> Is it (D70401 ) good enough to

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

zixuan-wu added a subscriber: pcwang-thead. zixuan-wu added a comment. In D70401#3175266 , @khchen wrote: >> Is it (D70401 ) good enough to solve or >> complete rv32e issue? > > It need to > > 1. disallow ilp32e ABI with

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

khchen added a comment. > Is it (D70401 ) good enough to solve or > complete rv32e issue? It need to 1. disallow ilp32e ABI with D ISA extension.

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

zixuan-wu added a comment. In D70401#3172750 , @khchen wrote: > In D70401#3172457 , @zixuan-wu wrote: > >> Hi, all. Why is it not continued? > > Sorry, I have to work on other tasks so stop the rv32e implementation

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

khchen added a comment. In D70401#3172457 , @zixuan-wu wrote: > Hi, all. Why is it not continued? Sorry, I have to work on other tasks so stop the rv32e implementation work. Are you interest to finish it? I could share my patches to you. Repository:

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

zixuan-wu added a comment. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence. Hi, all. Why is it not continued? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

asb added a comment. In D70401#2733003 , @khchen wrote: > Hi, I would like to add ilp32e ABI support in llvm > Is there anyone working on this? > It seem the one thing missed is ilp32e ABI should disallow D ISA extension. > Is there anything else? Nobody

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

khchen added a comment. Herald added a subscriber: vkmr. Hi, I would like to add ilp32e ABI support in llvm Is there anyone working on this? It seem the one thing missed is ilp32e ABI should disallow D ISA extension. Is there anything else? Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

lenary marked 3 inline comments as done. lenary added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:104 + // so that we don't insert `fp` manipulation code into functions that do not + // require it. + const MachineFrameInfo = MF.getFrameInfo();

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

lenary added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1525 unsigned TwoXLenInBytes = (2 * XLen) / 8; if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { lenary

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

jrtc27 added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:10323 + bool EABI) + : DefaultABIInfo(CGT), XLen(XLen), FLen(FLen) { +if (EABI) I think it'd be better to have a `NumArgGPRs(EAABI ? 6 : 8)` here as having a

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

Jim added inline comments. Comment at: llvm/test/CodeGen/RISCV/calling-conv-ilp32e-double-bug.ll:2 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -target-abi ilp32e -mattr=+f -verify-machineinstrs < %s +; RUN: llc

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

lenary marked 3 inline comments as done. lenary added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1525 unsigned TwoXLenInBytes = (2 * XLen) / 8; if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) ==

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

shiva0217 added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1525 unsigned TwoXLenInBytes = (2 * XLen) / 8; if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

luismarques added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:36 +// The only physical register that isn't saved is x2 (SP), which is used by the +// processor when the interrupt happens. + Nitpick: "the interrupt happens" -> "an

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

lenary added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1525 unsigned TwoXLenInBytes = (2 * XLen) / 8; if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {