[PATCH] D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates

2020-01-17 Thread Kerry McLaughlin via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
kmclaughlin marked an inline comment as done.
Closed by commit rGfe3bb8ec9683: [AArch64][SVE] Add ImmArg property to 
intrinsics with immediates (authored by kmclaughlin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72612/new/

https://reviews.llvm.org/D72612

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td

Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -1646,12 +1646,12 @@
 let Inst{19-16} = Zm;
   }
 
-  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexH32b:$idx))),
-(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexH32b:$idx)>;
-  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexS32b:$idx))),
-(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexS32b:$idx)>;
-  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, (i32 VectorIndexD32b:$idx))),
-(!cast(NAME # _D) $Op1, $Op2, $Op3, VectorIndexD32b:$idx)>;
+  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexH32b_timm:$idx))),
+(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexH32b_timm:$idx)>;
+  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexS32b_timm:$idx))),
+(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexS32b_timm:$idx)>;
+  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, (i32 VectorIndexD32b_timm:$idx))),
+(!cast(NAME # _D) $Op1, $Op2, $Op3, VectorIndexD32b_timm:$idx)>;
 }
 
 
@@ -1694,12 +1694,12 @@
 let Inst{19-16} = Zm;
   }
 
-  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, (i32 VectorIndexH32b:$idx))),
-(!cast(NAME # _H) $Op1, $Op2, VectorIndexH32b:$idx)>;
-  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, (i32 VectorIndexS32b:$idx))),
-(!cast(NAME # _S) $Op1, $Op2, VectorIndexS32b:$idx)>;
-  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, (i32 VectorIndexD32b:$idx))),
-(!cast(NAME # _D) $Op1, $Op2, VectorIndexD32b:$idx)>;
+  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, (i32 VectorIndexH32b_timm:$idx))),
+(!cast(NAME # _H) $Op1, $Op2, VectorIndexH32b_timm:$idx)>;
+  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, (i32 VectorIndexS32b_timm:$idx))),
+(!cast(NAME # _S) $Op1, $Op2, VectorIndexS32b_timm:$idx)>;
+  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, (i32 VectorIndexD32b_timm:$idx))),
+(!cast(NAME # _D) $Op1, $Op2, VectorIndexD32b_timm:$idx)>;
 }
 
 //===--===//
@@ -1785,10 +1785,10 @@
 let Inst{19-16} = Zm;
   }
 
-  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexS32b:$idx), (i32 complexrotateop:$imm))),
-(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexS32b:$idx, complexrotateop:$imm)>;
-  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexD32b:$idx), (i32 complexrotateop:$imm))),
-(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexD32b:$idx, complexrotateop:$imm)>;
+  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexS32b_timm:$idx), (i32 complexrotateop:$imm))),
+(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexS32b_timm:$idx, complexrotateop:$imm)>;
+  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexD32b_timm:$idx), (i32 complexrotateop:$imm))),
+(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexD32b_timm:$idx, complexrotateop:$imm)>;
 }
 
 //===--===//
@@ -1949,7 +1949,7 @@
 multiclass sve2_fp_mla_long_by_indexed_elem opc, string asm,
 SDPatternOperator op> {
   def NAME : sve2_fp_mla_long_by_indexed_elem;
-  def : SVE_4_Op_Imm_Pat(NAME)>;
+  def : SVE_4_Op_Imm_Pat(NAME)>;
 }
 
 //===--===//
@@ -2479,23 +2479,23 @@
 
 multiclass sve_intx_dot_by_indexed_elem {
-  def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS32b> {
+  def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS32b_timm> {
 bits<2> iop;
 bits<3> Zm;
 let Inst{20-19} = iop;
 let Inst{18-16} = Zm;
   }
-  def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD32b> {
+  def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD32b_timm> {
 bits<1> iop;
 bits<4> Zm;
 let Inst{20} = iop;
 let Inst{19-16} = Zm;

[PATCH] D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates

2020-01-16 Thread Kerry McLaughlin via Phabricator via cfe-commits 
kmclaughlin marked an inline comment as done.
kmclaughlin added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:1108
+  def "" : AsmVectorIndexOpnd, PatLeaf<(ty imm), pred>;
+  def _timm : AsmVectorIndexOpnd, PatLeaf<(ty timm), pred>;
+}

efriedma wrote:
> Using ImmLeaf/TImmLeaf doesn't work here?
Thanks for the suggestion, it looks like I can use ImmLeaf & TImmLeaf here (and 
use //Imm// again instead of //N->getZExtValue()// in VectorIndex1, etc below)


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[PATCH] D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates

2020-01-16 Thread Kerry McLaughlin via Phabricator via cfe-commits 
kmclaughlin updated this revision to Diff 238445.
kmclaughlin added a comment.

- Replace PatLeaf with ImmLeaf & TImmLeaf in the VectorIndex multiclass


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72612/new/

https://reviews.llvm.org/D72612

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td

Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -1646,12 +1646,12 @@
 let Inst{19-16} = Zm;
   }
 
-  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexH32b:$idx))),
-(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexH32b:$idx)>;
-  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexS32b:$idx))),
-(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexS32b:$idx)>;
-  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, (i32 VectorIndexD32b:$idx))),
-(!cast(NAME # _D) $Op1, $Op2, $Op3, VectorIndexD32b:$idx)>;
+  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexH32b_timm:$idx))),
+(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexH32b_timm:$idx)>;
+  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexS32b_timm:$idx))),
+(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexS32b_timm:$idx)>;
+  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, (i32 VectorIndexD32b_timm:$idx))),
+(!cast(NAME # _D) $Op1, $Op2, $Op3, VectorIndexD32b_timm:$idx)>;
 }
 
 
@@ -1694,12 +1694,12 @@
 let Inst{19-16} = Zm;
   }
 
-  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, (i32 VectorIndexH32b:$idx))),
-(!cast(NAME # _H) $Op1, $Op2, VectorIndexH32b:$idx)>;
-  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, (i32 VectorIndexS32b:$idx))),
-(!cast(NAME # _S) $Op1, $Op2, VectorIndexS32b:$idx)>;
-  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, (i32 VectorIndexD32b:$idx))),
-(!cast(NAME # _D) $Op1, $Op2, VectorIndexD32b:$idx)>;
+  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, (i32 VectorIndexH32b_timm:$idx))),
+(!cast(NAME # _H) $Op1, $Op2, VectorIndexH32b_timm:$idx)>;
+  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, (i32 VectorIndexS32b_timm:$idx))),
+(!cast(NAME # _S) $Op1, $Op2, VectorIndexS32b_timm:$idx)>;
+  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, (i32 VectorIndexD32b_timm:$idx))),
+(!cast(NAME # _D) $Op1, $Op2, VectorIndexD32b_timm:$idx)>;
 }
 
 //===--===//
@@ -1785,10 +1785,10 @@
 let Inst{19-16} = Zm;
   }
 
-  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexS32b:$idx), (i32 complexrotateop:$imm))),
-(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexS32b:$idx, complexrotateop:$imm)>;
-  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexD32b:$idx), (i32 complexrotateop:$imm))),
-(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexD32b:$idx, complexrotateop:$imm)>;
+  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexS32b_timm:$idx), (i32 complexrotateop:$imm))),
+(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexS32b_timm:$idx, complexrotateop:$imm)>;
+  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexD32b_timm:$idx), (i32 complexrotateop:$imm))),
+(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexD32b_timm:$idx, complexrotateop:$imm)>;
 }
 
 //===--===//
@@ -1949,7 +1949,7 @@
 multiclass sve2_fp_mla_long_by_indexed_elem opc, string asm,
 SDPatternOperator op> {
   def NAME : sve2_fp_mla_long_by_indexed_elem;
-  def : SVE_4_Op_Imm_Pat(NAME)>;
+  def : SVE_4_Op_Imm_Pat(NAME)>;
 }
 
 //===--===//
@@ -2479,23 +2479,23 @@
 
 multiclass sve_intx_dot_by_indexed_elem {
-  def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS32b> {
+  def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS32b_timm> {
 bits<2> iop;
 bits<3> Zm;
 let Inst{20-19} = iop;
 let Inst{18-16} = Zm;
   }
-  def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD32b> {
+  def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD32b_timm> {
 bits<1> iop;
 bits<4> Zm;
 let Inst{20} = iop;
 let Inst{19-16} = Zm;
   }
 
-  def : Pat<(nxv4i32 (op nxv4i32:$Op1, nxv16i8:$Op2, nxv16i8:$Op3, (i32 VectorIndexS32b:$idx))),
-(!cast(NAME #

[PATCH] D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates

2020-01-15 Thread Eli Friedman via Phabricator via cfe-commits 
efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM with one question




Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:1108
+  def "" : AsmVectorIndexOpnd, PatLeaf<(ty imm), pred>;
+  def _timm : AsmVectorIndexOpnd, PatLeaf<(ty timm), pred>;
+}

Using ImmLeaf/TImmLeaf doesn't work here?


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[PATCH] D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates

2020-01-15 Thread Kerry McLaughlin via Phabricator via cfe-commits 
kmclaughlin updated this revision to Diff 238199.
kmclaughlin added a comment.

- Removed shiftimm patterns and reused tvecshiftR8, etc
- Removed complex patterns used by AsmVectorIndexOpnd and instead created a 
multiclass (VectorIndex) to create a PatLeaf with timm if "_timm" is appended


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72612/new/

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Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td

Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -1639,12 +1639,12 @@
 let Inst{19-16} = Zm;
   }
 
-  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexH32b:$idx))),
-(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexH32b:$idx)>;
-  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexS32b:$idx))),
-(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexS32b:$idx)>;
-  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, (i32 VectorIndexD32b:$idx))),
-(!cast(NAME # _D) $Op1, $Op2, $Op3, VectorIndexD32b:$idx)>;
+  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexH32b_timm:$idx))),
+(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexH32b_timm:$idx)>;
+  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexS32b_timm:$idx))),
+(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexS32b_timm:$idx)>;
+  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, (i32 VectorIndexD32b_timm:$idx))),
+(!cast(NAME # _D) $Op1, $Op2, $Op3, VectorIndexD32b_timm:$idx)>;
 }
 
 
@@ -1687,12 +1687,12 @@
 let Inst{19-16} = Zm;
   }
 
-  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, (i32 VectorIndexH32b:$idx))),
-(!cast(NAME # _H) $Op1, $Op2, VectorIndexH32b:$idx)>;
-  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, (i32 VectorIndexS32b:$idx))),
-(!cast(NAME # _S) $Op1, $Op2, VectorIndexS32b:$idx)>;
-  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, (i32 VectorIndexD32b:$idx))),
-(!cast(NAME # _D) $Op1, $Op2, VectorIndexD32b:$idx)>;
+  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, (i32 VectorIndexH32b_timm:$idx))),
+(!cast(NAME # _H) $Op1, $Op2, VectorIndexH32b_timm:$idx)>;
+  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, (i32 VectorIndexS32b_timm:$idx))),
+(!cast(NAME # _S) $Op1, $Op2, VectorIndexS32b_timm:$idx)>;
+  def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, (i32 VectorIndexD32b_timm:$idx))),
+(!cast(NAME # _D) $Op1, $Op2, VectorIndexD32b_timm:$idx)>;
 }
 
 //===--===//
@@ -1778,10 +1778,10 @@
 let Inst{19-16} = Zm;
   }
 
-  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexS32b:$idx), (i32 complexrotateop:$imm))),
-(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexS32b:$idx, complexrotateop:$imm)>;
-  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexD32b:$idx), (i32 complexrotateop:$imm))),
-(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexD32b:$idx, complexrotateop:$imm)>;
+  def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexS32b_timm:$idx), (i32 complexrotateop:$imm))),
+(!cast(NAME # _H) $Op1, $Op2, $Op3, VectorIndexS32b_timm:$idx, complexrotateop:$imm)>;
+  def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexD32b_timm:$idx), (i32 complexrotateop:$imm))),
+(!cast(NAME # _S) $Op1, $Op2, $Op3, VectorIndexD32b_timm:$idx, complexrotateop:$imm)>;
 }
 
 //===--===//
@@ -1942,7 +1942,7 @@
 multiclass sve2_fp_mla_long_by_indexed_elem opc, string asm,
 SDPatternOperator op> {
   def NAME : sve2_fp_mla_long_by_indexed_elem;
-  def : SVE_4_Op_Imm_Pat(NAME)>;
+  def : SVE_4_Op_Imm_Pat(NAME)>;
 }
 
 //===--===//
@@ -2472,23 +2472,23 @@
 
 multiclass sve_intx_dot_by_indexed_elem {
-  def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS32b> {
+  def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS32b_timm> {
 bits<2> iop;
 bits<3> Zm;
 let Inst{20-19} = iop;
 let Inst{18-16} = Zm;
   }
-  def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD32b> {
+  def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD32b_timm> {
 bits<1> iop;
 bits<4> Zm;
 let Inst{20} = iop;
 let

[PATCH] D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates

2020-01-13 Thread Eli Friedman via Phabricator via cfe-commits 
efriedma added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:1099
+class AsmVectorIndexOpnd
+: Operand, ComplexPattern", []> 
{
   let ParserMatchClass = mc;

sdesmalen wrote:
> @efriedma  @rengolin The idea here is to use a ComplexPattern to match either 
> a TargetConstant or a Constant (as at this point in selectiondag, it probably 
> no longer matters what kind of constant it is, as we want to match an 
> instruction). This avoids having to duplicate patternfragments for TImmLeaf 
> and ImmLeaf for all the operands deriving from AsmVectorIndexOpnd.
> 
> Any thoughts on this approach?
You should never need to duplicate a pattern.  If the pattern is matching an 
ImmArg intrinsic, it has to be a TargetConstant; otherwise, it has to be a 
Constant.  I would rather keep the corresponding pattern fragments strict, to 
avoid confusion about what we're expecting.  Also, looking to the future, 
ComplexPatterns are more complicated to port to GlobalISel.

If the concern is just that you'll have to define the pattern fragments 
multiple times, could you use a multiclass?


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[PATCH] D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates

2020-01-13 Thread Sander de Smalen via Phabricator via cfe-commits 
sdesmalen added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:1099
+class AsmVectorIndexOpnd
+: Operand, ComplexPattern", []> 
{
   let ParserMatchClass = mc;

@efriedma  @rengolin The idea here is to use a ComplexPattern to match either a 
TargetConstant or a Constant (as at this point in selectiondag, it probably no 
longer matters what kind of constant it is, as we want to match an 
instruction). This avoids having to duplicate patternfragments for TImmLeaf and 
ImmLeaf for all the operands deriving from AsmVectorIndexOpnd.

Any thoughts on this approach?



Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:4386
 
-  def : SVE_3_Op_Imm_Pat(NAME # _B)>;
-  def : SVE_3_Op_Imm_Pat(NAME # _H)>;
-  def : SVE_3_Op_Imm_Pat(NAME # _S)>;
-  def : SVE_3_Op_Imm_Pat(NAME # _D)>;
+  def : SVE_3_Op_Cpx_Imm_Pat(NAME # _B)>;
+  def : SVE_3_Op_Cpx_Imm_Pat(NAME # _H)>;

I think these can just as well use `tvecshiftR8`, `tvecshiftR16`, (etc) as 
those already exist.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72612/new/

https://reviews.llvm.org/D72612



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[PATCH] D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates

2020-01-13 Thread Kerry McLaughlin via Phabricator via cfe-commits 
kmclaughlin created this revision.
kmclaughlin added reviewers: efriedma, sdesmalen, andwar.
Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.

Several SVE intrinsics with immediate arguments (including those
added by D70253  & D70437 
) do not use the ImmArg property.
This patch adds ImmArg where required and changes
the appropriate patterns which match the immediates.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D72612

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td

Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -354,6 +354,12 @@
 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, (vt3 ImmTy:$Op3))),
   (inst $Op1, $Op2, ImmTy:$Op3)>;
 
+class SVE_3_Op_Cpx_Imm_Pat
+: Pat<(vtd (op vt1:$Op1, vt2:$Op2, (cpx ImmTy:$Op3))),
+  (inst $Op1, $Op2, ImmTy:$Op3)>;
+
 class SVE_4_Op_Imm_Pat
@@ -4377,10 +4383,10 @@
 let Inst{9-8} = imm{4-3};
   }
 
-  def : SVE_3_Op_Imm_Pat(NAME # _B)>;
-  def : SVE_3_Op_Imm_Pat(NAME # _H)>;
-  def : SVE_3_Op_Imm_Pat(NAME # _S)>;
-  def : SVE_3_Op_Imm_Pat(NAME # _D)>;
+  def : SVE_3_Op_Cpx_Imm_Pat(NAME # _B)>;
+  def : SVE_3_Op_Cpx_Imm_Pat(NAME # _H)>;
+  def : SVE_3_Op_Cpx_Imm_Pat(NAME # _S)>;
+  def : SVE_3_Op_Cpx_Imm_Pat(NAME # _D)>;
 }
 
 class sve_int_bin_pred_shift sz8_64, bit wide, bits<3> opc,
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5023,6 +5023,7 @@
 defm : Neon_INS_elt_pattern;
 
 
+let AddedComplexity = 1 in {
 // Floating point vector extractions are codegen'd as either a sequence of
 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
 // the lane number is anything other than zero.
@@ -5032,6 +5033,7 @@
   (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
   (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
+}
 
 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
   (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
Index: llvm/lib/Target/AArch64/AArch64InstrFormats.td
===
--- llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -683,6 +683,10 @@
   let ParserMatchClass = Imm0_63Operand;
 }
 
+def shiftimm8  : ComplexPattern",  []>;
+def shiftimm16 : ComplexPattern", []>;
+def shiftimm32 : ComplexPattern", []>;
+def shiftimm64 : ComplexPattern", []>;
 
 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
 // instructions for splatting repeating bit patterns across the immediate.
@@ -832,7 +836,7 @@
 }
 
 // imm32_0_7 predicate - True if the 32-bit immediate is in the range [0,7]
-def imm32_0_7 : Operand, ImmLeaf, TImmLeaf {
   let ParserMatchClass = Imm0_7Operand;
@@ -1091,8 +1095,8 @@
   let RenderMethod = "addVectorIndexOperands";
 }
 
-class AsmVectorIndexOpnd
-: Operand, ImmLeaf {
+class AsmVectorIndexOpnd
+: Operand, ComplexPattern", []> {
   let ParserMatchClass = mc;
   let PrintMethod = "printVectorIndex";
 }
@@ -1103,17 +1107,17 @@
 def VectorIndexSOperand : AsmVectorIndex<0, 3>;
 def VectorIndexDOperand : AsmVectorIndex<0, 1>;
 
-def VectorIndex1 : AsmVectorIndexOpnd;
-def VectorIndexB : AsmVectorIndexOpnd;
-def VectorIndexH : AsmVectorIndexOpnd;
-def VectorIndexS : AsmVectorIndexOpnd;
-def VectorIndexD : AsmVectorIndexOpnd;
+def VectorIndex1 : AsmVectorIndexOpnd;
+def VectorIndexB : AsmVectorIndexOpnd;
+def VectorIndexH : AsmVectorIndexOpnd;
+def VectorIndexS : AsmVectorIndexOpnd;
+def VectorIndexD : AsmVectorIndexOpnd;
 
-def VectorIndex132b : AsmVectorIndexOpnd;
-def VectorIndexB32b : AsmVectorIndexOpnd;
-def VectorIndexH32b : AsmVectorIndexOpnd;
-def VectorIndexS32b : AsmVectorIndexOpnd;
-def VectorIndexD32b : AsmVectorIndexOpnd;
+def VectorIndex132b : AsmVectorIndexOpnd;
+def VectorIndexB32b : AsmVectorIndexOpnd;
+def VectorIndexH32b : AsmVectorIndexOpnd;
+def VectorIndexS32b : AsmVectorIndexOpnd;
+def VectorIndexD32b : AsmVectorIndexOpnd;
 
 def SVEVectorIndexExtDupBOperand : AsmVectorIndex<0, 63, "SVE">;
 def SVEVectorIndexExtDupHOperand : AsmVectorIndex<0, 31, "SVE">;
@@ -1122,15 +1126,15 @@
 def SVEVectorIndexExtDupQOperand : AsmVectorIndex<0, 3, "SVE">;
 
 def sve_elm_idx_extdup_b
-  : AsmVectorIndexOpnd;
+  : AsmVectorIndexOpnd;
 def sve_elm_idx_extdup_h
-  : AsmVectorIndexOpnd;
+  : AsmVectorIndexOpnd;
 def sve_elm_idx_extdup_s
-