[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

2020-06-25 Thread Amy Kwan via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe0c02dc9800e: [PowerPC][Power10] Implement centrifuge, 
vector gather every nth bit, vector… (authored by amyk).

Changed prior to commit:
  https://reviews.llvm.org/D80970?vs=267775=273581#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80970/new/

https://reviews.llvm.org/D80970

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10.c
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
  llvm/test/MC/Disassembler/PowerPC/p10insts.txt
  llvm/test/MC/PowerPC/p10.s

Index: llvm/test/MC/PowerPC/p10.s
===
--- llvm/test/MC/PowerPC/p10.s
+++ llvm/test/MC/PowerPC/p10.s
@@ -15,6 +15,20 @@
 # CHECK-BE: pextd 1, 2, 4 # encoding: [0x7c,0x41,0x21,0x78]
 # CHECK-LE: pextd 1, 2, 4 # encoding: [0x78,0x21,0x41,0x7c]
 pextd 1, 2, 4
+# CHECK-BE: vcfuged 1, 2, 4   # encoding: [0x10,0x22,0x25,0x4d]
+# CHECK-LE: vcfuged 1, 2, 4   # encoding: [0x4d,0x25,0x22,0x10]
+vcfuged 1, 2, 4
+# CHECK-BE: cfuged 1, 2, 4# encoding: [0x7c,0x41,0x21,0xb8]
+# CHECK-LE: cfuged 1, 2, 4# encoding: [0xb8,0x21,0x41,0x7c]
+cfuged 1, 2, 4
+# CHECK-BE: vgnb 1, 2, 2  # encoding: [0x10,0x22,0x14,0xcc]
+# CHECK-LE: vgnb 1, 2, 2  # encoding: [0xcc,0x14,0x22,0x10]
+vgnb 1, 2, 2
+# CHECK-BE: xxeval 32, 1, 2, 3, 2 # encoding: [0x05,0x00,0x00,0x02,
+# CHECK-BE-SAME:   0x88,0x01,0x10,0xd1]
+# CHECK-LE: xxeval 32, 1, 2, 3, 2 # encoding: [0x02,0x00,0x00,0x05,
+# CHECK-LE-SAME:   0xd1,0x10,0x01,0x88]
+xxeval 32, 1, 2, 3, 2
 # CHECK-BE: vclzdm 1, 2, 3# encoding: [0x10,0x22,0x1f,0x84]
 # CHECK-LE: vclzdm 1, 2, 3# encoding: [0x84,0x1f,0x22,0x10]
 vclzdm 1, 2, 3
Index: llvm/test/MC/Disassembler/PowerPC/p10insts.txt
===
--- llvm/test/MC/Disassembler/PowerPC/p10insts.txt
+++ llvm/test/MC/Disassembler/PowerPC/p10insts.txt
@@ -13,6 +13,18 @@
 # CHECK: pextd 1, 2, 4
 0x7c 0x41 0x21 0x78
 
+# CHECK: vcfuged 1, 2, 4
+0x10 0x22 0x25 0x4d
+
+# CHECK: cfuged 1, 2, 4
+0x7c 0x41 0x21 0xb8
+
+# CHECK: vgnb 1, 2, 2
+0x10 0x22 0x14 0xcc
+
+# CHECK: xxeval 32, 1, 2, 3, 2
+0x05 0x00 0x00 0x02 0x88 0x01 0x10 0xd1
+
 # CHECK: vclzdm 1, 2, 3
 0x10 0x22 0x1f 0x84
 
Index: llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
===
--- llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
+++ llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
@@ -9,6 +9,10 @@
 declare <2 x i64> @llvm.ppc.altivec.vpextd(<2 x i64>, <2 x i64>)
 declare i64 @llvm.ppc.pdepd(i64, i64)
 declare i64 @llvm.ppc.pextd(i64, i64)
+declare <2 x i64> @llvm.ppc.altivec.vcfuged(<2 x i64>, <2 x i64>)
+declare i64 @llvm.ppc.cfuged(i64, i64)
+declare i64 @llvm.ppc.altivec.vgnb(<1 x i128>, i32)
+declare <2 x i64> @llvm.ppc.vsx.xxeval(<2 x i64>, <2 x i64>, <2 x i64>, i32)
 declare <2 x i64> @llvm.ppc.altivec.vclzdm(<2 x i64>, <2 x i64>)
 declare <2 x i64> @llvm.ppc.altivec.vctzdm(<2 x i64>, <2 x i64>)
 declare i64 @llvm.ppc.cntlzdm(i64, i64)
@@ -54,6 +58,66 @@
   ret i64 %tmp
 }
 
+define <2 x i64> @test_vcfuged(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vcfuged:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vcfuged v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %tmp = tail call <2 x i64> @llvm.ppc.altivec.vcfuged(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %tmp
+}
+
+define i64 @test_cfuged(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cfuged:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cfuged r3, r3, r4
+; CHECK-NEXT:blr
+entry:
+  %tmp = tail call i64 @llvm.ppc.cfuged(i64 %a, i64 %b)
+  ret i64 %tmp
+}
+
+define i64 @test_vgnb_1(<1 x i128> %a) {
+; CHECK-LABEL: test_vgnb_1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vgnb r3, v2, 2
+; CHECK-NEXT:blr
+entry:
+  %tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 2)
+  ret i64 %tmp
+}
+
+define i64 @test_vgnb_2(<1 x i128> %a) {
+; CHECK-LABEL: test_vgnb_2:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vgnb r3, v2, 7
+; CHECK-NEXT:blr
+entry:
+  %tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 7)
+  ret i64 %tmp
+}
+
+define i64 @test_vgnb_3(<1 x i128> %a) {
+; CHECK-LABEL: test_vgnb_3:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vgnb r3, v2, 5
+;

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

2020-06-25 Thread Amy Kwan via Phabricator via cfe-commits 
amyk added a comment.

Talked to Anil, and will address his nit comments on the commit and disregard 
the comment about the test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80970/new/

https://reviews.llvm.org/D80970



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

2020-06-15 Thread Lei Huang via Phabricator via cfe-commits 
lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80970/new/

https://reviews.llvm.org/D80970



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

2020-06-12 Thread Anil Mahmud via Phabricator via cfe-commits 
anil9 added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:305
 
+// P10 Vector Centrifuge
+BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "")

nit : // P10 Vector Centrifuge built-in.



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:308
+
+// P10 Vector Gather Every N-th Bit
+BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "")

similar as above.



Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:43
+  // CHECK-NEXT: ret i64
+  return vec_gnb(vui128a, 7);
+}

Try out some numbers which have different interpretation as signed/unsigned, if 
that matters that is.



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80970/new/

https://reviews.llvm.org/D80970



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

2020-06-10 Thread Amy Kwan via Phabricator via cfe-commits 
amyk added a comment.

Ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80970/new/

https://reviews.llvm.org/D80970



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

2020-06-01 Thread Amy Kwan via Phabricator via cfe-commits 
amyk created this revision.
amyk added reviewers: nemanjai, lei, stefanp, saghir, power-llvm-team.
amyk added a project: LLVM.
Herald added subscribers: shchenz, hiraditya.
Herald added a project: clang.

This patch implements builtins for the following prototypes:

  unsigned long long __builtin_cfuged (unsigned long long, unsigned long long);
  vector unsigned long long vec_cfuge (vector unsigned long long, vector 
unsigned long long);
  unsigned long long vec_gnb (vector unsigned __int128, const unsigned int);
  vector unsigned char vec_ternarylogic (vector unsigned char, vector unsigned 
char, vector unsigned char, const unsigned int);
  vector unsigned short vec_ternarylogic (vector unsigned short, vector 
unsigned short, vector unsigned short, const unsigned int);
  vector unsigned int vec_ternarylogic (vector unsigned int, vector unsigned 
int, vector unsigned int, const unsigned int);
  vector unsigned long long vec_ternarylogic (vector unsigned long long, vector 
unsigned long long, vector unsigned long long, const unsigned int);
  vector unsigned __int128 vec_ternarylogic (vector unsigned __int128, vector 
unsigned __int128, vector unsigned __int128, const unsigned int);

Depends on D80935 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80970

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10.c
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
  llvm/test/MC/Disassembler/PowerPC/p10insts.txt
  llvm/test/MC/PowerPC/p10.s

Index: llvm/test/MC/PowerPC/p10.s
===
--- llvm/test/MC/PowerPC/p10.s
+++ llvm/test/MC/PowerPC/p10.s
@@ -15,3 +15,18 @@
 # CHECK-BE: pextd 1, 2, 4 # encoding: [0x7c,0x41,0x21,0x78]
 # CHECK-LE: pextd 1, 2, 4 # encoding: [0x78,0x21,0x41,0x7c]
 pextd 1, 2, 4
+# CHECK-BE: vcfuged 1, 2, 4   # encoding: [0x10,0x22,0x25,0x4d]
+# CHECK-LE: vcfuged 1, 2, 4   # encoding: [0x4d,0x25,0x22,0x10]
+vcfuged 1, 2, 4
+# CHECK-BE: cfuged 1, 2, 4# encoding: [0x7c,0x41,0x21,0xb8]
+# CHECK-LE: cfuged 1, 2, 4# encoding: [0xb8,0x21,0x41,0x7c]
+cfuged 1, 2, 4
+# CHECK-BE: vgnb 1, 2, 2  # encoding: [0x10,0x22,0x14,0xcc]
+# CHECK-LE: vgnb 1, 2, 2  # encoding: [0xcc,0x14,0x22,0x10]
+vgnb 1, 2, 2
+# CHECK-BE: xxeval 32, 1, 2, 3, 2 # encoding: [0x05,0x00,0x00,0x02,
+# CHECK-BE-SAME:   0x88,0x01,0x10,0xd1]
+# CHECK-LE: xxeval 32, 1, 2, 3, 2 # encoding: [0x02,0x00,0x00,0x05,
+# CHECK-LE-SAME:   0xd1,0x10,0x01,0x88]
+xxeval 32, 1, 2, 3, 2
+
Index: llvm/test/MC/Disassembler/PowerPC/p10insts.txt
===
--- llvm/test/MC/Disassembler/PowerPC/p10insts.txt
+++ llvm/test/MC/Disassembler/PowerPC/p10insts.txt
@@ -12,3 +12,15 @@
 
 # CHECK: pextd 1, 2, 4
 0x7c 0x41 0x21 0x78
+
+# CHECK: vcfuged 1, 2, 4
+0x10 0x22 0x25 0x4d
+
+# CHECK: cfuged 1, 2, 4
+0x7c 0x41 0x21 0xb8
+
+# CHECK: vgnb 1, 2, 2
+0x10 0x22 0x14 0xcc
+
+# CHECK: xxeval 32, 1, 2, 3, 2
+0x05 0x00 0x00 0x02 0x88 0x01 0x10 0xd1
Index: llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
===
--- llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
+++ llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
@@ -9,6 +9,11 @@
 declare <2 x i64> @llvm.ppc.altivec.vpextd(<2 x i64>, <2 x i64>)
 declare i64 @llvm.ppc.pdepd(i64, i64)
 declare i64 @llvm.ppc.pextd(i64, i64)
+declare <2 x i64> @llvm.ppc.altivec.vcfuged(<2 x i64>, <2 x i64>)
+declare i64 @llvm.ppc.cfuged(i64, i64)
+declare i64 @llvm.ppc.altivec.vgnb(<1 x i128>, i32)
+declare <2 x i64> @llvm.ppc.vsx.xxeval(<2 x i64>, <2 x i64>, <2 x i64>, i32)
+
 
 define <2 x i64> @test_vpdepd(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vpdepd:
@@ -49,3 +54,63 @@
   %tmp = tail call i64 @llvm.ppc.pextd(i64 %a, i64 %b)
   ret i64 %tmp
 }
+
+define <2 x i64> @test_vcfuged(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vcfuged:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vcfuged v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %tmp = tail call <2 x i64> @llvm.ppc.altivec.vcfuged(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %tmp
+}
+
+define i64 @test_cfuged(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cfuged:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cfuged r3, r3, r4
+; CHECK-NEXT:blr
+entry:
+  %tmp = tail call i64 @llvm.ppc.cfuged(i64 %a, i64 %b)
+  ret i64 %tmp
+}
+
+define i64 @test_vgnb_1(<1 x