[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Albion Fung via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3136cbe29e74: [PowerPC]  Implement Vector Shift Builtins 
(authored by Conanap).

Changed prior to commit:
  https://reviews.llvm.org/D83338?vs=283980=285208#toc

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-shift.ll

Index: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These test cases demonstrate that the vector shift quadword instructions
+; introduced within Power10 are correctly exploited.
+
+define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vslq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vslq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shl = shl <1 x i128> %a, %rem
+  ret <1 x i128> %shl
+}
+
+define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsrq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsrq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shr = lshr <1 x i128> %a, %rem
+  ret <1 x i128> %shr
+}
+
+define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsraq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsraq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shr = ashr <1 x i128> %a, %rem
+  ret <1 x i128> %shr
+}
+
+define dso_local <1 x i128> @test_vec_vslq2(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vslq2:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vslq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %shl = shl <1 x i128> %a, %b
+  ret <1 x i128> %shl
+}
+
+define dso_local <1 x i128> @test_vec_vsrq2(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsrq2:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsrq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %shr = lshr <1 x i128> %a, %b
+  ret <1 x i128> %shr
+}
+
+define dso_local <1 x i128> @test_vec_vsraq2(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsraq2:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsraq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %shr = ashr <1 x i128> %a, %b
+  ret <1 x i128> %shr
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1288,6 +1288,18 @@
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
   def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
+  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
 }
 
 let AddedComplexity = 400, Predicates = [IsISA3_1] in {
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1128,6 +1128,9 @@
   if (Subtarget.has64BitSupport())
 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
 
+  if (Subtarget.isISA3_1())
+setOperationAction(ISD::SRA, MVT::v1i128, Legal);
+
   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
 
   if (!isPPC64) {
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- 

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Amy Kwan via Phabricator via cfe-commits]

amyk accepted this revision.
amyk added a comment.
This revision is now accepted and ready to land.

Thanks for addressing the comments. LGTM.




Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:10
+
+; These tests ensure that vector shift quadword builtins are correctly
+; exploited and selected for during codeGen.

nit: 
```
These test cases demonstrate that the vector shift quadword instructions 
introduced 
within Power10 are correctly exploited.
```


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Albion Fung via Phabricator via cfe-commits]

Conanap added inline comments.



Comment at: clang/lib/Headers/altivec.h:17243
+  // return (vector signed __int128)vec_sr((vector unsigned __int128)__a, __b);
+  return (vector signed __int128)(
+((vector unsigned __int128) __a) >>

amyk wrote:
> Could you please fix the indentation of the returns to make them all 
> consistent?
I ran clang-format this time, lmk if we should change this as it doesn't look 
like clang-format was too consistent with itself


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Albion Fung via Phabricator via cfe-commits]

Conanap updated this revision to Diff 283980.
Conanap marked 8 inline comments as done.
Conanap added a comment.

Added shl tests, formatting fixes


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Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-shift.ll

Index: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These tests ensure that vector shift quadword builtins are correctly
+; exploited and selected for during codeGen.
+
+define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vslq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vslq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shl = shl <1 x i128> %a, %rem
+  ret <1 x i128> %shl
+}
+
+define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsrq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsrq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shr = lshr <1 x i128> %a, %rem
+  ret <1 x i128> %shr
+}
+
+define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsraq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsraq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shr = ashr <1 x i128> %a, %rem
+  ret <1 x i128> %shr
+}
+
+define dso_local <1 x i128> @test_vec_vslq2(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vslq2:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vslq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %shl = shl <1 x i128> %a, %b
+  ret <1 x i128> %shl
+}
+
+define dso_local <1 x i128> @test_vec_vsrq2(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsrq2:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsrq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %shr = lshr <1 x i128> %a, %b
+  ret <1 x i128> %shr
+}
+
+define dso_local <1 x i128> @test_vec_vsraq2(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsraq2:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsraq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %shr = ashr <1 x i128> %a, %b
+  ret <1 x i128> %shr
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1176,6 +1176,19 @@
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
   def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
+
+  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
 }
 
 let AddedComplexity = 400, Predicates = [IsISA3_1] in {
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1110,6 +1110,9 @@
 }
   }
 
+  if (Subtarget.isISA3_1())
+setOperationAction(ISD::SRA, MVT::v1i128, Legal);
+
   if (Subtarget.has64BitSupport())
 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
 
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -17,6 +17,7 @@
 vector unsigned int vuia, vuib, vuic;
 vector signed long long vslla, vsllb;
 vector unsigned long long vulla, vullb, vullc;
+vector signed __int128 vi128a;
 vector unsigned __int128 

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Amy Kwan via Phabricator via cfe-commits]

amyk added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1144
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;

amyk wrote:
> I noticed that we have patterns for the PPCISD nodes, but I think no tests to 
> show these patterns?
My apologies, upon closer inspection I noticed that your tests are in fact the 
ones with the PPCISD nodes but you are missing the regular shl/srl/sra. Please 
add the tests for these, as well. 


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

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amyk added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1100
+
+if (Subtarget.isISA3_1()) {
+  setOperationAction(ISD::SRA, MVT::v1i128, Legal);

amyk wrote:
> No brackets are needed here.
> 
> Also, I think it might make sense to move this block into the previous 
> `hasP9Altivec` condition since in there it has:
> ```
>   setOperationAction(ISD::SHL, MVT::v1i128, Legal);
>   setOperationAction(ISD::SRL, MVT::v1i128, Legal);
> ```
Oops, I made that comment above since I thought you were putting the block 
inside a `hasP9Altivec` block. Sorry. 

Maybe you can move this condition right underneath the `hasP9Altivec` block 
that contains the `SHL/SRL` to be closer to those instructions. 



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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Amy Kwan via Phabricator via cfe-commits]

amyk added inline comments.



Comment at: clang/lib/Headers/altivec.h:17217
+
+/* vs[l | r | ra] */
+static __inline__ vector unsigned __int128 __ATTRS_o_ai

Add a space after this comment.



Comment at: clang/lib/Headers/altivec.h:17227
+vec_sl(vector signed __int128 __a, vector unsigned __int128 __b) {
+  // return (vector signed __int128)vec_sl((vector unsigned __int128)__a, __b);
+  return __a << (__b %

Please remove any commented code.



Comment at: clang/lib/Headers/altivec.h:17243
+  // return (vector signed __int128)vec_sr((vector unsigned __int128)__a, __b);
+  return (vector signed __int128)(
+((vector unsigned __int128) __a) >>

Could you please fix the indentation of the returns to make them all consistent?



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1100
+
+if (Subtarget.isISA3_1()) {
+  setOperationAction(ISD::SRA, MVT::v1i128, Legal);

No brackets are needed here.

Also, I think it might make sense to move this block into the previous 
`hasP9Altivec` condition since in there it has:
```
  setOperationAction(ISD::SHL, MVT::v1i128, Legal);
  setOperationAction(ISD::SRL, MVT::v1i128, Legal);
```



Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1141
+/* Vector shifts for ISA3_1 */
+let Predicates = [IsISA3_1] in {
+  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),

There is no need to make a new predicate block, you can put these anonymous 
patterns in the block above.



Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1144
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;

I noticed that we have patterns for the PPCISD nodes, but I think no tests to 
show these patterns?


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

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Conanap updated this revision to Diff 281783.
Conanap added a comment.

Replaced a forgotten test file.


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Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-shift.ll

Index: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These tests ensure that vector shift quadword builtins are correctly
+; exploited and selected for during codeGen.
+
+define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vslq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vslq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shl = shl <1 x i128> %a, %rem
+  ret <1 x i128> %shl
+}
+
+define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsrq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsrq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shr = lshr <1 x i128> %a, %rem
+  ret <1 x i128> %shr
+}
+
+define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsraq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsraq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shr = ashr <1 x i128> %a, %rem
+  ret <1 x i128> %shr
+}
+
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1137,6 +1137,22 @@
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
 }
 
+/* Vector shifts for ISA3_1 */
+let Predicates = [IsISA3_1] in {
+  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
+}
+
 let AddedComplexity = 400, Predicates = [IsISA3_1] in {
   def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$rS, 0)), xoaddr:$src),
 (STXVRBX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1096,6 +1096,10 @@
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
 }
+
+if (Subtarget.isISA3_1()) {
+  setOperationAction(ISD::SRA, MVT::v1i128, Legal);
+}
   }
 
   if (Subtarget.has64BitSupport())
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -17,6 +17,7 @@
 vector unsigned int vuia, vuib, vuic;
 vector signed long long vslla, vsllb;
 vector unsigned long long vulla, vullb, vullc;
++vector signed __int128 vi128a;
 vector unsigned __int128 vui128a, vui128b, vui128c;
 vector float vfa, vfb;
 vector double vda, vdb;
@@ -634,3 +635,45 @@
   // CHECK-NEXT: ret i32
   return vec_test_lsbb_all_zeros(vuca);
 }
+
+vector unsigned __int128 test_vec_slq_unsigned (void) {
+  // CHECK-LABEL: test_vec_slq_unsigned
+  // CHECK: shl <1 x i128> %{{.+}}, %{{.+}}
+  // CHECK: ret <1 x i128> %{{.+}}
+  return vec_sl(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_slq_signed (void) {
+  // CHECK-LABEL: test_vec_slq_signed
+  // CHECK: shl <1 x i128> %{{.+}}, %{{.+}}
+  // CHECK: ret <1 x i128>
+  return vec_sl(vi128a, vui128a);
+}
+
+vector unsigned __int128 test_vec_srq_unsigned (void) {
+  // CHECK-LABEL: 

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Albion Fung via Phabricator via cfe-commits]

Conanap updated this revision to Diff 281735.
Conanap added a comment.

Fixed formatting based on bot feedback.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83338/new/

https://reviews.llvm.org/D83338

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1137,6 +1137,22 @@
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
 }
 
+/* Vector shifts for ISA3_1 */
+let Predicates = [IsISA3_1] in {
+  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
+}
+
 let AddedComplexity = 400, Predicates = [IsISA3_1] in {
   def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$rS, 0)), xoaddr:$src),
 (STXVRBX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1096,6 +1096,10 @@
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
 }
+
+if (Subtarget.isISA3_1()) {
+  setOperationAction(ISD::SRA, MVT::v1i128, Legal);
+}
   }
 
   if (Subtarget.has64BitSupport())
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -17,6 +17,7 @@
 vector unsigned int vuia, vuib, vuic;
 vector signed long long vslla, vsllb;
 vector unsigned long long vulla, vullb, vullc;
++vector signed __int128 vi128a;
 vector unsigned __int128 vui128a, vui128b, vui128c;
 vector float vfa, vfb;
 vector double vda, vdb;
@@ -634,3 +635,45 @@
   // CHECK-NEXT: ret i32
   return vec_test_lsbb_all_zeros(vuca);
 }
+
+vector unsigned __int128 test_vec_slq_unsigned (void) {
+  // CHECK-LABEL: test_vec_slq_unsigned
+  // CHECK: shl <1 x i128> %{{.+}}, %{{.+}}
+  // CHECK: ret <1 x i128> %{{.+}}
+  return vec_sl(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_slq_signed (void) {
+  // CHECK-LABEL: test_vec_slq_signed
+  // CHECK: shl <1 x i128> %{{.+}}, %{{.+}}
+  // CHECK: ret <1 x i128>
+  return vec_sl(vi128a, vui128a);
+}
+
+vector unsigned __int128 test_vec_srq_unsigned (void) {
+  // CHECK-LABEL: test_vec_srq_unsigned
+  // CHECK: lshr <1 x i128> %{{.+}}, %{{.+}}
+  // CHECK: ret <1 x i128>
+  return vec_sr(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_srq_signed (void) {
+  // CHECK-LABEL: test_vec_srq_signed
+  // CHECK: lshr <1 x i128> %{{.+}}, %{{.+}}
+  // CHECK: ret <1 x i128>
+  return vec_sr(vi128a, vui128a);
+}
+
+vector unsigned __int128 test_vec_sraq_unsigned (void) {
+  // CHECK-LABEL: test_vec_sraq_unsigned
+  // CHECK: ashr <1 x i128> %{{.+}}, %{{.+}}
+  // CHECK: ret <1 x i128>
+  return vec_sra(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_sraq_signed (void) {
+  // CHECK-LABEL: test_vec_sraq_signed
+  // CHECK: ashr <1 x i128> %{{.+}}, %{{.+}}
+  // CHECK: ret <1 x i128>
+  return vec_sra(vi128a, vui128a);
+}
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -17213,6 +17213,56 @@
   return __builtin_vsx_xvtlsbb(__a, 0);
 }
 #endif /* __VSX__ */
+
+/* vs[l | r | ra] */
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sl(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+  return __a << (__b %
+ (vector unsigned __int128)(sizeof(unsigned __int128) *
+   __CHAR_BIT__));
+}
+
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_sl(vector signed __int128 __a, vector unsigned __int128 __b) {
+  // return (vector signed __int128)vec_sl((vector unsigned __int128)__a, __b);
+  return __a << (__b %
+ (vector unsigned __int128)(sizeof(unsigned __int128) *
+   __CHAR_BIT__));

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

Please address the auto generated clang-format issues for the added code in 
this patch.


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Albion Fung via Phabricator via cfe-commits]

Conanap updated this revision to Diff 280592.
Conanap removed a reviewer: power-llvm-team.
Conanap added a comment.
Herald added a subscriber: kbarton.

Converted the impelmentation to an open coded implementation and updated the 
test cases as appropriate.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83338/new/

https://reviews.llvm.org/D83338

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-shift.ll

Index: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These tests ensure that vector shift quadword builtins are correctly
+; exploited and selected for during codeGen.
+
+define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vslq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vslq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shl = shl <1 x i128> %a, %rem
+  ret <1 x i128> %shl
+}
+
+define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsrq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsrq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shr = lshr <1 x i128> %a, %rem
+  ret <1 x i128> %shr
+}
+
+define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsraq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsraq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %rem = urem <1 x i128> %b, 
+  %shr = ashr <1 x i128> %a, %rem
+  ret <1 x i128> %shr
+}
+
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1100,6 +1100,22 @@
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
 }
 
+/* Vector shifts for ISA3_1 */
+let Predicates = [IsISA3_1] in {
+  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
+  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
+}
+
 let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
  def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
 i32immNonAllOneNonZero:$A,
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1089,6 +1089,10 @@
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
 }
+
+if(Subtarget.isISA3_1()) {
+  setOperationAction(ISD::SRA, MVT::v1i128, Legal);
+}
   }
 
   if (Subtarget.hasQPX()) {
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -21,6 +21,7 @@
 vector unsigned int vuia, vuib, vuic;
 vector signed long long vslla, vsllb;
 vector unsigned long long vulla, vullb, vullc;
+vector signed __int128 vi128a;
 vector unsigned __int128 vui128a, vui128b, vui128c;
 vector float vfa, vfb;
 vector double vda, vdb;
@@ -593,3 +594,45 @@
   // CHECK-NEXT: ret i32
   return vec_test_lsbb_all_zeros(vuca);
 }
+
+vector unsigned __int128 test_vec_slq_unsigned (void) {
+  // CHECK-LABEL: test_vec_slq_unsigned
+  // CHECK: shl <1 x i128> %{{.+}}, %{{.+}}
+  // CHECK: ret <1 x i128> %{{.+}}
+  return vec_sl(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_slq_signed (void) {
+  // CHECK-LABEL: test_vec_slq_signed
+  // CHECK: shl <1 x i128> %{{.+}}, %{{.+}}
+  // CHECK: ret <1 x i128>
+ 

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Amy Kwan via Phabricator via cfe-commits]

amyk added a comment.

I realize it may be possible to open code these, as these functions already 
exist in altivec.h. Could you look into if this is the case?


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Albion Fung via Phabricator via cfe-commits]

Conanap updated this revision to Diff 279348.
Conanap marked 8 inline comments as done.
Conanap added a comment.

Fixed function names, test case clean up


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-shift.ll

Index: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These tests ensure that vector shift quadword builtins are correctly
+; exploited and selected for during codeGen.
+
+define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vslq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vslq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %slq = call <1 x i128> @llvm.ppc.altivec.vslq(<1 x i128> %a, <1 x i128> %b)
+  ret <1 x i128> %slq
+}
+
+define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsrq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsrq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %slq = call <1 x i128> @llvm.ppc.altivec.vsrq(<1 x i128> %a, <1 x i128> %b)
+  ret <1 x i128> %slq
+}
+
+define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {
+; CHECK-LABEL: test_vec_vsraq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsraq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %slq = call <1 x i128> @llvm.ppc.altivec.vsraq(<1 x i128> %a, <1 x i128> %b)
+  ret <1 x i128> %slq
+}
+
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vslq(<1 x i128>, <1 x i128>)
+
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vsrq(<1 x i128>, <1 x i128>)
+
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vsraq(<1 x i128>, <1 x i128>)
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1032,9 +1032,9 @@
 (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
 "vrlqmi $vD, $vA, $vB", IIC_VecFP, []>,
 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
-  def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
-  def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
-  def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
+  def VSLQ  : VX1_Int_Ty<261, "vslq", int_ppc_altivec_vslq, v1i128>;
+  def VSRAQ : VX1_Int_Ty<773, "vsraq", int_ppc_altivec_vsraq, v1i128>;
+  def VSRQ  : VX1_Int_Ty<517, "vsrq", int_ppc_altivec_vsrq, v1i128>;
   def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
   def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
   def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -797,6 +797,7 @@
 def int_ppc_altivec_vsrv  : PowerPC_Vec_BBB_Intrinsic<"vsrv">;
 def int_ppc_altivec_vslh  : PowerPC_Vec_HHH_Intrinsic<"vslh">;
 def int_ppc_altivec_vslw  : PowerPC_Vec_WWW_Intrinsic<"vslw">;
+def int_ppc_altivec_vslq  : PowerPC_Vec_QQQ_Intrinsic<"vslq">;
 
 // Right Shifts.
 def int_ppc_altivec_vsr   : PowerPC_Vec_WWW_Intrinsic<"vsr">;
@@ -805,9 +806,11 @@
 def int_ppc_altivec_vsrb  : PowerPC_Vec_BBB_Intrinsic<"vsrb">;
 def int_ppc_altivec_vsrh  : PowerPC_Vec_HHH_Intrinsic<"vsrh">;
 def int_ppc_altivec_vsrw  : PowerPC_Vec_WWW_Intrinsic<"vsrw">;
+def int_ppc_altivec_vsrq  : PowerPC_Vec_QQQ_Intrinsic<"vsrq">;
 def int_ppc_altivec_vsrab : PowerPC_Vec_BBB_Intrinsic<"vsrab">;
 def int_ppc_altivec_vsrah : PowerPC_Vec_HHH_Intrinsic<"vsrah">;
 def int_ppc_altivec_vsraw : PowerPC_Vec_WWW_Intrinsic<"vsraw">;
+def int_ppc_altivec_vsraq : PowerPC_Vec_QQQ_Intrinsic<"vsraq">;
 
 // Rotates.
 def int_ppc_altivec_vrlb  : PowerPC_Vec_BBB_Intrinsic<"vrlb">;
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -21,6 +21,7 @@
 vector unsigned int vuia, vuib, vuic;
 vector signed 

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Amy Kwan via Phabricator via cfe-commits]

amyk added a comment.

Please also change the function names.




Comment at: clang/lib/Headers/altivec.h:17151
+
+/* vs[l | r | raq] */
+static __inline__ vector unsigned __int128 __ATTRS_o_ai

Actually, sorry, I think this comment should be the following instead:
`/* vec_s[l | r | ra] */` since these functions are actually supposed to be 
`vec_sl`, `vec_sr`, `vec_sra`.



Comment at: clang/lib/Headers/altivec.h:17158
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_sl(vector signed __int128 __a, vector unsigned __int128 __b) {
+  return __builtin_altivec_vslq((vector unsigned __int128) __a, __b);

stefanp wrote:
> nit:
> Is this supposed to be `vec_slq`?
Actually `vec_sl` seems to be correct. However, that would mean the other 
functions need to be renamed as the functions are supposed to be: `vec_sl`, 
`vec_sr`, `vec_sra`. Albion, could you please rename these functions and also 
ensure your test uses the correct naming.


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Victor Huang via Phabricator via cfe-commits]

NeHuang added a comment.

Overall seems fine to me, but of course, please wait to hear from Amy. 
Just some nits for the test case.




Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:9
+; RUN:   FileCheck %s
+
+define dso_local <1 x i128> @test_vec_slq(<1 x i128> %a, <1 x i128> %b) #0 {

nit: please add a description for test purpose. 



Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:10
+
+define dso_local <1 x i128> @test_vec_slq(<1 x i128> %a, <1 x i128> %b) #0 {
+; CHECK-LABEL: test_vec_slq:

stefanp wrote:
> nit:
> If you are going to use `#0` you can probably define `attributes #0 = { 
> nounwind }` at the bottom of this file.
nit: The test name and CHECK-LABEL should use `test_vec_vslq`



Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:10
+
+define dso_local <1 x i128> @test_vec_slq(<1 x i128> %a, <1 x i128> %b) #0 {
+; CHECK-LABEL: test_vec_slq:

NeHuang wrote:
> stefanp wrote:
> > nit:
> > If you are going to use `#0` you can probably define `attributes #0 = { 
> > nounwind }` at the bottom of this file.
> nit: The test name and CHECK-LABEL should use `test_vec_vslq`
+1, if no specific attributes needed. please remove all the `#0` and `#1` 


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

Just a few nits for this patch.




Comment at: clang/lib/Headers/altivec.h:17158
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_sl(vector signed __int128 __a, vector unsigned __int128 __b) {
+  return __builtin_altivec_vslq((vector unsigned __int128) __a, __b);

nit:
Is this supposed to be `vec_slq`?



Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:10
+
+define dso_local <1 x i128> @test_vec_slq(<1 x i128> %a, <1 x i128> %b) #0 {
+; CHECK-LABEL: test_vec_slq:

nit:
If you are going to use `#0` you can probably define `attributes #0 = { 
nounwind }` at the bottom of this file.



Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:41
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vslq(<1 x i128>, <1 x i128>) #1
+

nit: 
You probably don't need the #1 as it is not defined anyway.


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Albion Fung via Phabricator via cfe-commits]

Conanap updated this revision to Diff 278235.
Conanap marked 7 inline comments as done.
Conanap added a comment.

Formatting fixes, fixed test case return type, updated builtins' signatures to 
correct signatures.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-shift.ll

Index: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+define dso_local <1 x i128> @test_vec_slq(<1 x i128> %a, <1 x i128> %b) #0 {
+; CHECK-LABEL: test_vec_slq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vslq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %slq = call <1 x i128> @llvm.ppc.altivec.vslq(<1 x i128> %a, <1 x i128> %b)
+  ret <1 x i128> %slq
+}
+
+define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) #0 {
+; CHECK-LABEL: test_vec_vsrq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsrq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %slq = call <1 x i128> @llvm.ppc.altivec.vsrq(<1 x i128> %a, <1 x i128> %b)
+  ret <1 x i128> %slq
+}
+
+define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) #0 {
+; CHECK-LABEL: test_vec_vsraq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsraq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %slq = call <1 x i128> @llvm.ppc.altivec.vsraq(<1 x i128> %a, <1 x i128> %b)
+  ret <1 x i128> %slq
+}
+
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vslq(<1 x i128>, <1 x i128>) #1
+
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vsrq(<1 x i128>, <1 x i128>) #1
+
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vsraq(<1 x i128>, <1 x i128>) #1
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1027,9 +1027,9 @@
 (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
 "vrlqmi $vD, $vA, $vB", IIC_VecFP, []>,
 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
-  def VSLQ   : VX1_VT5_VA5_VB5<261, "vslq", []>;
-  def VSRAQ  : VX1_VT5_VA5_VB5<773, "vsraq", []>;
-  def VSRQ   : VX1_VT5_VA5_VB5<517, "vsrq", []>;
+  def VSLQ  : VX1_Int_Ty<261, "vslq", int_ppc_altivec_vslq, v1i128>;
+  def VSRAQ : VX1_Int_Ty<773, "vsraq", int_ppc_altivec_vsraq, v1i128>;
+  def VSRQ  : VX1_Int_Ty<517, "vsrq", int_ppc_altivec_vsrq, v1i128>;
   def VRLQ   : VX1_VT5_VA5_VB5<5, "vrlq", []>;
 
   def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -797,6 +797,7 @@
 def int_ppc_altivec_vsrv  : PowerPC_Vec_BBB_Intrinsic<"vsrv">;
 def int_ppc_altivec_vslh  : PowerPC_Vec_HHH_Intrinsic<"vslh">;
 def int_ppc_altivec_vslw  : PowerPC_Vec_WWW_Intrinsic<"vslw">;
+def int_ppc_altivec_vslq  : PowerPC_Vec_QQQ_Intrinsic<"vslq">;
 
 // Right Shifts.
 def int_ppc_altivec_vsr   : PowerPC_Vec_WWW_Intrinsic<"vsr">;
@@ -805,9 +806,11 @@
 def int_ppc_altivec_vsrb  : PowerPC_Vec_BBB_Intrinsic<"vsrb">;
 def int_ppc_altivec_vsrh  : PowerPC_Vec_HHH_Intrinsic<"vsrh">;
 def int_ppc_altivec_vsrw  : PowerPC_Vec_WWW_Intrinsic<"vsrw">;
+def int_ppc_altivec_vsrq  : PowerPC_Vec_QQQ_Intrinsic<"vsrq">;
 def int_ppc_altivec_vsrab : PowerPC_Vec_BBB_Intrinsic<"vsrab">;
 def int_ppc_altivec_vsrah : PowerPC_Vec_HHH_Intrinsic<"vsrah">;
 def int_ppc_altivec_vsraw : PowerPC_Vec_WWW_Intrinsic<"vsraw">;
+def int_ppc_altivec_vsraq : PowerPC_Vec_QQQ_Intrinsic<"vsraq">;
 
 // Rotates.
 def int_ppc_altivec_vrlb  : PowerPC_Vec_BBB_Intrinsic<"vrlb">;
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -21,6 +21,7 @@
 vector unsigned int vuia, vuib, vuic;
 vector signed long long vslla, vsllb;
 vector unsigned long long vulla, vullb, vullc;
+vector signed __int128 

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Amy Kwan via Phabricator via cfe-commits]

amyk added inline comments.



Comment at: clang/lib/Headers/altivec.h:17153
+/* vs[l | r | raq] */
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_slq(vector unsigned __int128 __a, vector unsigned __int128 __b) {

I believe there are supposed to be `signed` and `unsigned` versions of the 
functions? It looks like you currently have all of them as `unsigned`. 


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Amy Kwan via Phabricator via cfe-commits]

amyk added inline comments.



Comment at: clang/lib/Headers/altivec.h:17151
+
+/* vector shifts for quadwords */
+/* vs[l | r | raq] */

I think we can remove `/* vector shifts for quadwords */`. 
Then, we can add a new line after `/* vs[l | r | raq] */` for consistency of 
the comments.



Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:593
+
+vector signed __int128 test_vec_slq_signed (void) {
+  // CHECK-LABEL: test_vec_slq_signed

`vector unsigned` you mean? For the return of this test and every other 
`unsigned` test case.



Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1030
 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
-  def VSLQ   : VX1_VT5_VA5_VB5<261, "vslq", []>;
-  def VSRAQ  : VX1_VT5_VA5_VB5<773, "vsraq", []>;
-  def VSRQ   : VX1_VT5_VA5_VB5<517, "vsrq", []>;
+  def VSLQ  : VX1_Int_Ty< 261, "vslq", int_ppc_altivec_vslq, v1i128>;
+  def VSRAQ : VX1_Int_Ty< 773, "vsraq", int_ppc_altivec_vsraq, v1i128>;

nit: remove extra space after `<`



Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1032
+  def VSRAQ : VX1_Int_Ty< 773, "vsraq", int_ppc_altivec_vsraq, v1i128>;
+  def VSRQ  : VX1_Int_Ty< 517, "vsrq" , int_ppc_altivec_vsrq, v1i128>;
   def VRLQ   : VX1_VT5_VA5_VB5<5, "vrlq", []>;

nit: remove after space before `,`



Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1039
   def XSCVSQQP  : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
+
 }

Unrelated space change?



Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:10
+
+@vui128a = dso_local global <1 x i128> zeroinitializer, align 16
+@vui128b = dso_local global <1 x i128> zeroinitializer, align 16

Can probably remove these globals as you are not using them in your test.


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Albion Fung via Phabricator via cfe-commits]

Conanap added a comment.

Also removed instr def as it will be part of D83516 
.


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Albion Fung via Phabricator via cfe-commits]

Conanap updated this revision to Diff 277896.
Conanap marked 3 inline comments as done.
Conanap added a comment.

Added tests, added extra comments.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-shift.ll

Index: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+@vui128a = dso_local global <1 x i128> zeroinitializer, align 16
+@vui128b = dso_local global <1 x i128> zeroinitializer, align 16
+
+define dso_local <1 x i128> @test_vec_slq(<1 x i128> %a, <1 x i128> %b) #0 {
+; CHECK-LABEL: test_vec_slq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vslq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %slq = call <1 x i128> @llvm.ppc.altivec.vslq(<1 x i128> %a, <1 x i128> %b)
+  ret <1 x i128> %slq
+}
+
+define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) #0 {
+; CHECK-LABEL: test_vec_vsrq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsrq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %slq = call <1 x i128> @llvm.ppc.altivec.vsrq(<1 x i128> %a, <1 x i128> %b)
+  ret <1 x i128> %slq
+}
+
+define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) #0 {
+; CHECK-LABEL: test_vec_vsraq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsraq v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %slq = call <1 x i128> @llvm.ppc.altivec.vsraq(<1 x i128> %a, <1 x i128> %b)
+  ret <1 x i128> %slq
+}
+
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vslq(<1 x i128>, <1 x i128>) #1
+
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vsrq(<1 x i128>, <1 x i128>) #1
+
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vsraq(<1 x i128>, <1 x i128>) #1
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1027,15 +1027,16 @@
 (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
 "vrlqmi $vD, $vA, $vB", IIC_VecFP, []>,
 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
-  def VSLQ   : VX1_VT5_VA5_VB5<261, "vslq", []>;
-  def VSRAQ  : VX1_VT5_VA5_VB5<773, "vsraq", []>;
-  def VSRQ   : VX1_VT5_VA5_VB5<517, "vsrq", []>;
+  def VSLQ  : VX1_Int_Ty< 261, "vslq", int_ppc_altivec_vslq, v1i128>;
+  def VSRAQ : VX1_Int_Ty< 773, "vsraq", int_ppc_altivec_vsraq, v1i128>;
+  def VSRQ  : VX1_Int_Ty< 517, "vsrq" , int_ppc_altivec_vsrq, v1i128>;
   def VRLQ   : VX1_VT5_VA5_VB5<5, "vrlq", []>;
 
   def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
   def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
   def XSCVUQQP  : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
   def XSCVSQQP  : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
+
 }
 
 // Anonymous Patterns //
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -797,6 +797,7 @@
 def int_ppc_altivec_vsrv  : PowerPC_Vec_BBB_Intrinsic<"vsrv">;
 def int_ppc_altivec_vslh  : PowerPC_Vec_HHH_Intrinsic<"vslh">;
 def int_ppc_altivec_vslw  : PowerPC_Vec_WWW_Intrinsic<"vslw">;
+def int_ppc_altivec_vslq  : PowerPC_Vec_QQQ_Intrinsic<"vslq">;
 
 // Right Shifts.
 def int_ppc_altivec_vsr   : PowerPC_Vec_WWW_Intrinsic<"vsr">;
@@ -805,9 +806,11 @@
 def int_ppc_altivec_vsrb  : PowerPC_Vec_BBB_Intrinsic<"vsrb">;
 def int_ppc_altivec_vsrh  : PowerPC_Vec_HHH_Intrinsic<"vsrh">;
 def int_ppc_altivec_vsrw  : PowerPC_Vec_WWW_Intrinsic<"vsrw">;
+def int_ppc_altivec_vsrq  : PowerPC_Vec_QQQ_Intrinsic<"vsrq">;
 def int_ppc_altivec_vsrab : PowerPC_Vec_BBB_Intrinsic<"vsrab">;
 def int_ppc_altivec_vsrah : PowerPC_Vec_HHH_Intrinsic<"vsrah">;
 def int_ppc_altivec_vsraw : PowerPC_Vec_WWW_Intrinsic<"vsraw">;
+def int_ppc_altivec_vsraq : PowerPC_Vec_QQQ_Intrinsic<"vsraq">;
 
 // Rotates.
 def int_ppc_altivec_vrlb  : PowerPC_Vec_BBB_Intrinsic<"vrlb">;
Index: 

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Amy Kwan via Phabricator via cfe-commits]

amyk requested changes to this revision.
amyk added a comment.
This revision now requires changes to proceed.

This will need to be rebased against your 2608 instruction definitions patch. 
But yes, I believe you are missing the clang and llc test case for this patch. 
Requesting changes due to missing tests.




Comment at: clang/lib/Headers/altivec.h:17099
+
+/* vector shifts for quadwords */
+static __inline__ vector unsigned __int128 __ATTRS_o_ai

`/* vs[l | r | raq] */` (with a new line after the comment)


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Baptiste Saleil via Phabricator via cfe-commits]

bsaleil added a comment.

Shouldn't we have test cases to test `vec_sl`, `vec_sr` and `vec_sra` ?




Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:800
 def int_ppc_altivec_vsrw  : PowerPC_Vec_WWW_Intrinsic<"vsrw">;
+def int_ppc_altivec_vsrq   : PowerPC_Vec_QQQ_Intrinsic<"vsrq">;
 def int_ppc_altivec_vsrab : PowerPC_Vec_BBB_Intrinsic<"vsrab">;

nit: indentation issue



Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:919
+
+  def VSLQ   : VX1_Int_Ty< 261, "vslq", int_ppc_altivec_vslq, v1i128>;
+  def VSRAQ  : VX1_Int_Ty< 773, "vsraq", int_ppc_altivec_vsraq, v1i128>;

nit: extra spaces before `:` here and in the next two lines


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83338/new/

https://reviews.llvm.org/D83338



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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Albion Fung via Phabricator via cfe-commits]

Conanap created this revision.
Conanap added reviewers: PowerPC, power-llvm-team, saghir, nemanjai, hfinkel.
Conanap added projects: LLVM, clang, PowerPC.

Implemented the following vector right and left shift builtins and its test 
cases:

  vector unsigned __int128 vec_sl(vector unsigned __int128 a, vector unsigned 
__int128 b)
  vector signed __int128 vec_sl(vector signed __int128 a, vector unsigned 
__int128 b)
  vector unsigned __int128 vec_sr(vector unsigned __int128 a, vector unsigned 
__int128 b)
  vector signed __int128 vec_sr(vector signed __int128 a, vector unsigned 
__int128 b)
  vector unsigned __int128 vec_sra(vector unsigned __int128 a, vector unsigned 
__int128 b)
  vector signed __int128 vec_sra(vector signed __int128 a, vector unsigned 
__int128 b)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83338

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
  llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

Index: llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
===
--- llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -405,3 +405,12 @@
 # CHECK-BE: vinsdrx 1, 2, 3   # encoding: [0x10,0x22,0x1b,0xcf]
 # CHECK-LE: vinsdrx 1, 2, 3   # encoding: [0xcf,0x1b,0x22,0x10]
 vinsdrx 1, 2, 3
+# CHECK-BE: vslq 2, 3, 4  # encoding: [0x10,0x43,0x21,0x05]
+# CHECK-LE: vslq 2, 3, 4  # encoding: [0x05,0x21,0x43,0x10]
+vslq 2, 3, 4
+# CHECK-BE: vsraq 2, 3, 4 # encoding: [0x10,0x43,0x23,0x05]
+# CHECK-LE: vsraq 2, 3, 4 # encoding: [0x05,0x23,0x43,0x10]
+vsraq 2, 3, 4
+# CHECK-BE: vsrq 2, 3, 4  # encoding: [0x10,0x43,0x22,0x05]
+# CHECK-LE: vsrq 2, 3, 4  # encoding: [0x05,0x22,0x43,0x10]
+vsrq 2, 3, 4
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
===
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -278,3 +278,12 @@
 
 # CHECK: vinsdrx 1, 2, 3
 0x10 0x22 0x1b 0xcf
+
+# CHECK: vsrq 2, 3, 4
+0x10 0x43 0x22 0x05
+
+# CHECK: vslq 2, 3, 4
+0x10 0x43 0x21 0x05
+
+# CHECK: vsraq 2, 3, 4
+0x10 0x43 0x23 0x05
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -915,6 +915,11 @@
  "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
  [(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
+
+  def VSLQ   : VX1_Int_Ty< 261, "vslq", int_ppc_altivec_vslq, v1i128>;
+  def VSRAQ  : VX1_Int_Ty< 773, "vsraq", int_ppc_altivec_vsraq, v1i128>;
+  def VSRQ   : VX1_Int_Ty< 517, "vsrq" , int_ppc_altivec_vsrq, v1i128>;
+
 }
 
 // Anonymous Patterns //
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -788,6 +788,7 @@
 def int_ppc_altivec_vsrv  : PowerPC_Vec_BBB_Intrinsic<"vsrv">;
 def int_ppc_altivec_vslh  : PowerPC_Vec_HHH_Intrinsic<"vslh">;
 def int_ppc_altivec_vslw  : PowerPC_Vec_WWW_Intrinsic<"vslw">;
+def int_ppc_altivec_vslq  : PowerPC_Vec_QQQ_Intrinsic<"vslq">;
 
 // Right Shifts.
 def int_ppc_altivec_vsr   : PowerPC_Vec_WWW_Intrinsic<"vsr">;
@@ -796,9 +797,11 @@
 def int_ppc_altivec_vsrb  : PowerPC_Vec_BBB_Intrinsic<"vsrb">;
 def int_ppc_altivec_vsrh  : PowerPC_Vec_HHH_Intrinsic<"vsrh">;
 def int_ppc_altivec_vsrw  : PowerPC_Vec_WWW_Intrinsic<"vsrw">;
+def int_ppc_altivec_vsrq   : PowerPC_Vec_QQQ_Intrinsic<"vsrq">;
 def int_ppc_altivec_vsrab : PowerPC_Vec_BBB_Intrinsic<"vsrab">;
 def int_ppc_altivec_vsrah : PowerPC_Vec_HHH_Intrinsic<"vsrah">;
 def int_ppc_altivec_vsraw : PowerPC_Vec_WWW_Intrinsic<"vsraw">;
+def int_ppc_altivec_vsraq : PowerPC_Vec_QQQ_Intrinsic<"vsraq">;
 
 // Rotates.
 def int_ppc_altivec_vrlb  : PowerPC_Vec_BBB_Intrinsic<"vrlb">;
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -17095,6 +17095,37 @@
   return __builtin_vsx_xxblendvd(__a, __b, __c);
 }
 #endif /* __VSX__ */
+
+/* vector shifts for quadwords */
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sl(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+  return