[PATCH] D88759: [RISCV] Add SiFive cores to the CPU option

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

In D88759#2313236 , @thakis wrote:

> This seems to break tests: http://45.33.8.238/linux/29545/step_7.txt
>
> Can you take a look and revert for now if it takes a while to fix?

I see it should already have been fixed in 
a48d480e1f7ebc5d5f93507fe1f519496621e259 
.


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  rG LLVM Github Monorepo

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[PATCH] D88759: [RISCV] Add SiFive cores to the CPU option

[Nico Weber via Phabricator via cfe-commits]

thakis added a comment.

This seems to break tests: http://45.33.8.238/linux/29545/step_7.txt

Can you take a look and revert for now if it takes a while to fix?


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[PATCH] D88759: [RISCV] Add SiFive cores to the CPU option

[Evandro Menezes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG5d6d8a2769b3: [RISCV] Add SiFive cores to the CPU option 
(authored by evandro).
Herald added subscribers: cfe-commits, jrtc27.
Herald added a project: clang.

Changed prior to commit:
  https://reviews.llvm.org/D88759?vs=295917=296290#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88759/new/

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Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td

Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -228,8 +228,8 @@
 def : ProcessorModel<"rocket-rv32", RocketModel, []>;
 def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
 
-def : ProcessorModel<"bullet-rv32", BulletModel, []>;
-def : ProcessorModel<"bullet-rv64", BulletModel, [Feature64Bit]>;
+def : ProcessorModel<"sifive-7-rv32", BulletModel, []>;
+def : ProcessorModel<"sifive-7-rv64", BulletModel, [Feature64Bit]>;
 
 def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
  FeatureStdExtA,
@@ -242,6 +242,18 @@
  FeatureStdExtD,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-e76", BulletModel, [FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtC]>;
+
+def : ProcessorModel<"sifive-u74", BulletModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC]>;
+
 //===--===//
 // Define the RISC-V target.
 //===--===//
Index: llvm/include/llvm/Support/RISCVTargetParser.def
===
--- llvm/include/llvm/Support/RISCVTargetParser.def
+++ llvm/include/llvm/Support/RISCVTargetParser.def
@@ -7,9 +7,11 @@
 PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
 PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
 PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
-PROC(BULLET_RV32, {"bullet-rv32"}, FK_NONE, {""})
-PROC(BULLET_RV64, {"bullet-rv64"}, FK_64BIT, {""})
+PROC(BULLET_RV32, {"sifive-7-rv32"}, FK_NONE, {""})
+PROC(BULLET_RV64, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
+PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
+PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
 
 #undef PROC
Index: clang/test/Misc/target-invalid-cpu-note.c
===
--- clang/test/Misc/target-invalid-cpu-note.c
+++ clang/test/Misc/target-invalid-cpu-note.c
@@ -191,8 +191,8 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, bullet-rv32, sifive-e31
+// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, bullet-rv64, sifive-u54
+// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-u54, sifive-u74
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -7,12 +7,12 @@
 // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
 // MCPU-ROCKET64: "-target-feature" "+64bit"
 
-// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=bullet-rv32 | FileCheck -check-prefix=MCPU-BULLET32 %s
-// MCPU-BULLET32: "-nostdsysteminc" "-target-cpu" "bullet-rv32"
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-7-rv32 | FileCheck -check-prefix=MCPU-SIFIVE7-32 %s
+// MCPU-SIFIVE7-32: "-nostdsysteminc" "-target-cpu" "sifive-7-rv32"
 
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=bullet-rv64 | FileCheck -check-prefix=MCPU-BULLET64 %s
-//