[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Krasimir Georgiev via Phabricator via cfe-commits]

krasimir added a comment.

> I just pushed 6cb42cd6669785f3b611106e1b6b38bbe65733a9 
>  to 
> hopefully fix this.

Thank you Craig! That fixed it.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

Never mind, I see you added a test for that case


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

Does a double with `r` for RV32 work with that fix? That's supposed to give the 
low half of the register. You might need to also deal with the register pair 
class?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D93298#3355088 , @craig.topper 
wrote:

> In D93298#3354313 , @krasimir wrote:
>
>> @achieveartificialintelligence thank you for looking into this, sorry for 
>> the late reply!
>>
>> It looks like the latest version addresses @nikic's IR reproducer with 
>> `-mtriple=riscv32`.
>>
>> There seems to be an error trying this out with `-mtriple=riscv64`:
>>
>>   % cat test.ll
>>   define float @test(float %x) {
>> %1 = tail call float asm sideeffect alignstack "mv a0, a0", 
>> "={x10},{x10}"(float 0.00e+00)
>> ret float 0.00e+00
>>   }
>>   % llc -mtriple=riscv32 -mattr=+d test.ll
>>   % llc -mtriple=riscv64 -mattr=+d test.ll
>>   error: couldn't allocate output register for constraint '{x10}'
>>
>> I'm not sure if this is intended to work `-mtriple=riscv64`, but judging by 
>> the newly added test `RUN: llc -mtriple=riscv64 ...` line it seems like it 
>> should?
>
> My patch was only partially correct. I'll fix it

I just pushed 6cb42cd6669785f3b611106e1b6b38bbe65733a9 
 to 
hopefully fix this.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D93298#3354313 , @krasimir wrote:

> @achieveartificialintelligence thank you for looking into this, sorry for the 
> late reply!
>
> It looks like the latest version addresses @nikic's IR reproducer with 
> `-mtriple=riscv32`.
>
> There seems to be an error trying this out with `-mtriple=riscv64`:
>
>   % cat test.ll
>   define float @test(float %x) {
> %1 = tail call float asm sideeffect alignstack "mv a0, a0", 
> "={x10},{x10}"(float 0.00e+00)
> ret float 0.00e+00
>   }
>   % llc -mtriple=riscv32 -mattr=+d test.ll
>   % llc -mtriple=riscv64 -mattr=+d test.ll
>   error: couldn't allocate output register for constraint '{x10}'
>
> I'm not sure if this is intended to work `-mtriple=riscv64`, but judging by 
> the newly added test `RUN: llc -mtriple=riscv64 ...` line it seems like it 
> should?

My patch was only partially correct. I'll fix it


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Krasimir Georgiev via Phabricator via cfe-commits]

krasimir added a comment.

@achieveartificialintelligence thank you for looking into this, sorry for the 
late reply!

It looks like the latest version addresses @nikic's IR reproducer with 
`-mtriple=riscv32`.

There seems to be an error trying this out with `-mtriple=riscv64`:

  % cat test.ll
  define float @test(float %x) {
%1 = tail call float asm sideeffect alignstack "mv a0, a0", 
"={x10},{x10}"(float 0.00e+00)
ret float 0.00e+00
  }
  % llc -mtriple=riscv32 -mattr=+d test.ll
  % llc -mtriple=riscv64 -mattr=+d test.ll
  error: couldn't allocate output register for constraint '{x10}'

I'm not sure if this is intended to work `-mtriple=riscv64`, but judging by the 
newly added test `RUN: llc -mtriple=riscv64 ...` line it seems like it should?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/test/CodeGen/RISCV/zfinx-types.ll:5
+; RUN:| FileCheck --check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfh -target-abi=ilp32f < %s \
+; RUN:| FileCheck --check-prefix=RV32IF %s

craig.topper wrote:
> I'm not sure the Zfh or D RUN lines are really doing anything. Especially the 
> Zfh.
> 
> The same bug did happen with double, D extension and RV64 so should probably 
> test that.
I see you added rv64, but didn't add a test case that uses double instead of 
float.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0e38b295435b: [RISCV] add the MC layer support of Zfinx 
extension (authored by achieveartificialintelligence).
Herald added a project: All.

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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfinx-types.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 411959.
achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.

Address @craig.topper's comment


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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfinx-types.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/test/CodeGen/RISCV/zfinx-types.ll:5
+; RUN:| FileCheck --check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfh -target-abi=ilp32f < %s \
+; RUN:| FileCheck --check-prefix=RV32IF %s

I'm not sure the Zfh or D RUN lines are really doing anything. Especially the 
Zfh.

The same bug did happen with double, D extension and RV64 so should probably 
test that.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence added a comment.

Are there any other errors now? @krasimir @nikic


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence updated this revision to Diff 411734.
achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.

Address @jrtc27's comments


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  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfinx-types.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10923-10924
 
-  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+  std::pair Res;
+  Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+




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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 411719.
achieveartificialintelligence added a comment.

Rebase


Repository:
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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfinx-types.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

Can you help test if this patch works fine now? @krasimir


Repository:
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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 411375.
achieveartificialintelligence added a comment.

Thanks for @craig.topper's patch!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfinx-types.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Here's a fix that I tested on the original repreoduce. It detects that we 
picked one of the new register classes and tries to redirect back to the normal 
GPR register class if the GPR register class has the same width. I also checked 
for MVT::Other to use the GPR class if there was no type.

  diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  index 3daf2d03de03..4984872139c5 100644
  --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  @@ -10893,7 +10893,28 @@ 
RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   }
 }
   
  -  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
  +  std::pair Res;
  +  Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
  +
  +  if (Res.second == ::GPRF32RegClass) {
  +if (!Subtarget.is64Bit() || VT == MVT::Other)
  +  return std::make_pair(Res.first, ::GPRRegClass);
  +return std::make_pair(0, nullptr);
  +  }
  +
  +  if (Res.second == ::GPRF64RegClass) {
  +if (Subtarget.is64Bit() || VT == MVT::Other)
  +  return std::make_pair(Res.first, ::GPRRegClass);
  +return std::make_pair(0, nullptr);
  +  }
  +
  +  if (Res.second == ::GPRF16RegClass) {
  +if (VT == MVT::Other)
  +  return std::make_pair(Res.first, ::GPRRegClass);
  +return std::make_pair(0, nullptr);
  +  }
  +
  +  return Res;
   }


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Krasimir Georgiev via Phabricator via cfe-commits]

krasimir added a comment.

In D93298#3342480 , 
@achieveartificialintelligence wrote:

> In D93298#3342452 , @krasimir wrote:
>
>> @achieveartificialintelligence any progress with the problematic IR? Have 
>> you been able to reproduce using nikic's reduced example?
>
> Sorry, I don't have a solution right now.

Could we revert this until then?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D93298#3342452 , @krasimir wrote:

> @achieveartificialintelligence any progress with the problematic IR? Have you 
> been able to reproduce using nikic's reduced example?

Sorry, I don't have a solution right now.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Krasimir Georgiev via Phabricator via cfe-commits]

krasimir added a comment.

@achieveartificialintelligence any progress with the problematic IR? Have you 
been able to reproduce using nikic's reduced example?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Nikita Popov via Phabricator via cfe-commits]

nikic added a comment.

Because I happened to also run into this, reduced IR for `-mtriple=riscv32 
-mattr=+d` is:

  define float @test(float %x) {
%1 = tail call float asm sideeffect alignstack "mv a0, a0", 
"={x10},{x10}"(float 0.00e+00)
ret float 0.00e+00
  }


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Dávid Bolvanský via Phabricator via cfe-commits]

xbolva00 added a comment.

In D93298#3332058 , @jrtc27 wrote:

> In D93298#3332038 , @xbolva00 wrote:
>
 It appears that this is causing an assertion segfault in a rustc test over 
 at our experimental rust + llvm@head bot:
>>
>> I dont think that patch author is required to debug this issue for 
>> "experimental rust + llvm@head" - downstream.
>>
 Since I don't have a rust environment
>>
>> There is no requirement, indeed. LLVM devs are not responsible to keep 
>> ""experimental rust + llvm@head" working.
>
> They're required to assist with fixing regressions that show when compiling 
> legitimate IR. An IR reproducer was given, so no Rust toolchain knowledge 
> should be needed, at that point it's the LLVM dev's responsibility, and if 
> they can't fix it in a timely manner then it should be backed out.

Then yeah, if IR is provided and is standard one, this is okay. Consider to add 
that IR as testcase for the fix.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

In D93298#3332038 , @xbolva00 wrote:

>>> It appears that this is causing an assertion segfault in a rustc test over 
>>> at our experimental rust + llvm@head bot:
>
> I dont think that patch author is required to debug this issue for 
> "experimental rust + llvm@head" - downstream.
>
>>> Since I don't have a rust environment
>
> There is no requirement, indeed. LLVM devs are not responsible to keep 
> ""experimental rust + llvm@head" working.

They're required to assist with fixing regressions that show when compiling 
legitimate IR. An IR reproducer was given, so no Rust toolchain knowledge 
should be needed, at that point it's the LLVM dev's responsibility, and if they 
can't fix it in a timely manner then it should be backed out.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Dávid Bolvanský via Phabricator via cfe-commits]

xbolva00 added a comment.

>> It appears that this is causing an assertion segfault in a rustc test over 
>> at our experimental rust + llvm@head bot:

I dont think that patch author is required to debug this issue for 
"experimental rust + llvm@head" - downstream.

>> Since I don't have a rust environment

There is no requirement, indeed. LLVM devs are not responsible to keep 
""experimental rust + llvm@head" working.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

In D93298#3332020 , 
@achieveartificialintelligence wrote:

> @krasimir Since I don't have a rust environment, can you help me to test if 
> D120130  works?

Hm, actually, looking at the log, it doesn't appear to be trying to use Zfinx? 
My guess is that putting a float in a GPR has broken as that's now legal but 
should only be legal for Zfinx?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

@krasimir Since I don't have a rust environment, can you help me to test if 
D120130  works?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

In D93298#3331641 , @krasimir wrote:

> It appears that this is causing an assertion segfault in a `rustc` test over 
> at our experimental rust + llvm@head bot:
> https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/builds/8430#167e6de5-2dd5-41c3-87d7-b6e3f3908371/262-706
> The test is 
> https://github.com/rust-lang/rust/blob/master/src/test/assembly/asm/riscv-types.rs.
>  These two lines appear to cause it (code compiles fine when removed):
>
> - `check_reg!(a0_f32 f32 "a0" "mv");` 
> https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L178
> - `check_reg!(a0_f64 f64 "a0" "mv");` 
> https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L192
>
> The assertion:
>
>   Impossible reg-to-reg copy
>   UNREACHABLE executed at 
> [...]/rust/src/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:350
>
> ...

This is just MC layer support. Inline assembly interacts with CodeGen; I assume 
the register classes/constraints still need updating to support Zfinx.




Comment at: llvm/test/MC/RISCV/rv32i-invalid.s:1
-# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
 

This is an unrelated change


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Krasimir Georgiev via Phabricator via cfe-commits]

krasimir added a comment.

It appears that this is causing an assertion segfault in a `rustc` test over at 
our experimental rust + llvm@head bot:
https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/builds/8430#167e6de5-2dd5-41c3-87d7-b6e3f3908371/262-706
The test is 
https://github.com/rust-lang/rust/blob/master/src/test/assembly/asm/riscv-types.rs.
 These two lines appear to cause it (code compiles fine when removed):

- `check_reg!(a0_f32 f32 "a0" "mv");` 
https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L178
- `check_reg!(a0_f64 f64 "a0" "mv");` 
https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L192

The assertion:

  Impossible reg-to-reg copy
  UNREACHABLE executed at 
[...]/rust/src/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:350

The IR for riscv-types.rs:

  ; ModuleID = 'riscv_types.4cedf4b7-cgu.0'
  source_filename = "riscv_types.4cedf4b7-cgu.0"
  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
  target triple = "riscv64"
  
  @extern_static = external dso_local global i8
  @alloc55 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"reg_i8" 
}>, align 1
  @alloc56 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] 
c"reg_i16" }>, align 1
  @alloc57 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] 
c"reg_i32" }>, align 1
  @alloc58 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] 
c"reg_f32" }>, align 1
  @alloc59 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] 
c"reg_i64" }>, align 1
  @alloc60 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] 
c"reg_f64" }>, align 1
  @alloc61 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] 
c"reg_ptr" }>, align 1
  @alloc62 = private unnamed_addr constant <{ [8 x i8] }> <{ [8 x i8] 
c"freg_f32" }>, align 1
  @alloc63 = private unnamed_addr constant <{ [8 x i8] }> <{ [8 x i8] 
c"freg_f64" }>, align 1
  @alloc64 = private unnamed_addr constant <{ [5 x i8] }> <{ [5 x i8] c"a0_i8" 
}>, align 1
  @alloc65 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_i16" 
}>, align 1
  @alloc66 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_i32" 
}>, align 1
  @alloc67 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_f32" 
}>, align 1
  @alloc68 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_i64" 
}>, align 1
  @alloc69 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_f64" 
}>, align 1
  @alloc70 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_ptr" 
}>, align 1
  @alloc71 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] 
c"fa0_f32" }>, align 1
  @alloc72 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] 
c"fa0_f64" }>, align 1
  
  ; Function Attrs: nounwind
  define dso_local void @sym_fn() unnamed_addr #0 {
  start:
tail call void asm sideeffect alignstack "call ${0:c}", 
"s,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(void ()* nonnull @extern_func) 
#1, !srcloc !1
ret void
  }
  
  ; Function Attrs: nounwind
  define dso_local void @sym_static() unnamed_addr #0 {
  start:
tail call void asm sideeffect alignstack "lb t0, ${0:c}", 
"s,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8* nonnull @extern_static) #1, 
!srcloc !2
ret void
  }
  
  ; Function Attrs: nounwind
  define dso_local i8 @reg_i8(i8 %x) unnamed_addr #0 {
  start:
tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 
1 bitcast (<{ [6 x i8] }>* @alloc55 to [0 x i8]*), i64 6) #1
%0 = tail call i8 asm sideeffect alignstack "mv ${0}, ${1}", 
"=,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8 %x) #1, !srcloc !3
ret i8 %0
  }
  
  ; Function Attrs: nounwind
  define dso_local i16 @reg_i16(i16 %x) unnamed_addr #0 {
  start:
tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 
1 bitcast (<{ [7 x i8] }>* @alloc56 to [0 x i8]*), i64 7) #1
%0 = tail call i16 asm sideeffect alignstack "mv ${0}, ${1}", 
"=,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i16 %x) #1, !srcloc !3
ret i16 %0
  }
  
  ; Function Attrs: nounwind
  define dso_local i32 @reg_i32(i32 %x) unnamed_addr #0 {
  start:
tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 
1 bitcast (<{ [7 x i8] }>* @alloc57 to [0 x i8]*), i64 7) #1
%0 = tail call i32 asm sideeffect alignstack "mv ${0}, ${1}", 
"=,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i32 %x) #1, !srcloc !3
ret i32 %0
  }
  
  ; Function Attrs: nounwind
  define dso_local float @reg_f32(float %x) unnamed_addr #0 {
  start:
tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 
1 bitcast (<{ [7 x i8] }>* @alloc58 to [0 x i8]*), i64 7) #1
%0 = tail call float asm sideeffect alignstack "mv ${0}, ${1}", 
"=,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(float %x) #1, !srcloc !3
ret float %0
  }
  
  ; Function 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

Thanks all!


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
achieveartificialintelligence marked an inline comment as done.
Closed by commit rG7798ecca9c3d: [RISCV] add the MC layer support of Zfinx 
extension (authored by achieveartificialintelligence).

Changed prior to commit:
  https://reviews.llvm.org/D93298?vs=407482=409617#toc

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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

In that case, LGTM (needs a rebase though). Thanks for your patience on this 
@achieveartificialintelligence.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D93298#3326230 , @asb wrote:

> I think all my comments have been addressed. @craig.topper - are you happy 
> your RegInfo question is addressed?

I'm happy.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

I think all my comments have been addressed. @craig.topper - are you happy your 
RegInfo question is addressed?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557
+
+let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add

Jim wrote:
> Is register pair only on RV32 for used as f64?
Yes.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557
+
+let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add

Is register pair only on RV32 for used as f64?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555
+def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+X10_PD, X12_PD, X14_PD, X16_PD,

craig.topper wrote:
> Jim wrote:
> > Is XLenRI correct for GPRPF64? RV32 has size 32.
> I'm not sure the RegInfos are correct for the other classes either. The 
> RegInfos override the register size, the spill size, and spill alignment. I 
> think those should all be based on the FP type.
> 
> So I don't think any of these should have a RegInfos.
Without `RegInfo`, it would cause `spill size` to be changed for a large number 
of other tests.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 407482.
achieveartificialintelligence marked 2 inline comments as done.
achieveartificialintelligence added a comment.

Address comments.


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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555
+def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+X10_PD, X12_PD, X14_PD, X16_PD,

Jim wrote:
> Is XLenRI correct for GPRPF64? RV32 has size 32.
I'm not sure the RegInfos are correct for the other classes either. The 
RegInfos override the register size, the spill size, and spill alignment. I 
think those should all be based on the FP type.

So I don't think any of these should have a RegInfos.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555
+def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+X10_PD, X12_PD, X14_PD, X16_PD,

Is XLenRI correct for GPRPF64? RV32 has size 32.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D93298#3296515 , @luismarques wrote:

> Assuming this will be merged soon, do you want to submit a backport request 
> for the 14.0 branch?

Yes.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

Assuming this will be merged soon, do you want to submit a backport request for 
the 14.0 branch?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 404910.
achieveartificialintelligence added a comment.

Separate the Zhinxmin and Zhinx extensions. Inspired by D118581 



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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 402739.
achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.

@asb Thank you very much! Could you please take a look at what needs to be 
modified now?


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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

Not an issue for this MC-layer patch, but I've created 
https://github.com/riscv/riscv-zfinx/issues/14 to point out what seems to be an 
incorrect statement about the status quo on the ABI for 32-bit floating point 
types on RV64 in the Zfinx spec.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.
Herald added a subscriber: pcwang-thead.

Thanks for your work on this. The way you've managed to use multiclasses to 
handle this with the 'ExtInfo' definitions takes a bit of unpicking to follow, 
but it does a really good job of keeping the instruction definitions largely 
unmodified. Nice!

I've got a few requests/questions on the test coverage:

- I'm not sure the inclusion of the load/store instructions in the z[d,f,h]inx 
test cases has much value, given those instructions are unmodified?
- Given that the set of F/D/Zfh instructions that _aren't_ supported under 
z[d,f,h]inx is relatively short, it's probably worth being exhaustive in the 
*-invalid.s test cases. It's only 8 instructions for Zfinx for instance.
- The *-invalid.s test cases should have coverage for using a floating point 
register with an operation that is supported by Z[d,f,h]inx
- The zdinx test cases don't include any coverage for when odd registers are 
used.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 401528.
achieveartificialintelligence added a comment.

Address @craig.topper's comments. Thanks!


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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: llvm/test/MC/RISCV/rvzfinx-aliases-valid.s

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:137
+
+def GPR : RegisterClass<"RISCV", [XLenVT], 32, GPRAllocationList> {
   let RegInfos = XLenRI;

Does putting this back the way it was and using "(add GPR)" in GPRF16, GPRF32, 
and GPRF64 work?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

Ping. Any other suggestions?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 400733.
achieveartificialintelligence added a comment.
Herald added subscribers: alextsao1999, eopXD.

rebase


Repository:
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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: llvm/test/MC/RISCV/rvzfinx-aliases-valid.s

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 400256.
achieveartificialintelligence added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: llvm/test/MC/RISCV/rvzfinx-aliases-valid.s

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 399527.
achieveartificialintelligence marked 3 inline comments as done.
achieveartificialintelligence added a comment.

Address @craig.topper's comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:687
   // TODO: This has been removed in later specs, which specify that D implies F
   if (HasD && !HasF)
 return createStringError(errc::invalid_argument,

Do we need the equivalent of this for Zfinx and Zdinx?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:228
 
+let Predicates = [HasStdExtZdinx] in {
+def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs, 
FPR64INX:$rs)>;

Don't we need IN32X aliases too?



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:552
+
+def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add
+(sequence "X%u", 10, 17),

Is possible to reference GPR here to avoid listing the allocation order again? 
Similar to how GPRNoX0 does (sub GPR, X0). Not sure if there is a way to be 
exactly another list.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 399270.
achieveartificialintelligence added a comment.

update


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: llvm/test/MC/RISCV/rvzfinx-aliases-valid.s

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence added a comment.

Ping. `Zfinx` has been ratified, could we spend some time on this patch?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence updated this revision to Diff 396373.
achieveartificialintelligence added a comment.

Update Part of Zfinx Codes


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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,49 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
Index: llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
@@ -0,0 +1,49 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN: | FileCheck 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:489
 
+let Predicates = [HasStdExtZdinx] in {
+def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX GPRF64Op:$rd, GPRF64Op:$rs, 
GPRF64Op:$rs)>;

Aren't these aliases only valid for RV64. You need IN32X aliases for RV32 right?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:69
 {"zfh", RISCVExtensionVersion{0, 1}},
+{"zfinx", RISCVExtensionVersion{1, 0}},
+{"zdinx", RISCVExtensionVersion{1, 0}},

Do we need to enforce that these can't be mixed with F, D, and Zfh?



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1718
+!getSTI().hasFeature(RISCV::FeatureStdExtF) &&
+!getSTI().hasFeature(RISCV::FeatureStdExtD) &&
+!getSTI().hasFeature(RISCV::FeatureStdExtZfh)));

D and Zfh imply F. Is it enough to just check F?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:77
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPFMAS_rrr_frm
-: RVInstR4Frm<0b00, opcode, (outs FPR32:$rd),
-  (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3),
+class FPFMAS_rrr_frm_single

Can we merge this with FPFMAD_rrr_frm_single and FPFMAH_rrr_frm_single by 
passing the 0b00/0b01/0b10 value from 
FPFMAS_rrr_frm/FPFMAD_rrr_frm/FPFMAH_rrr_frm?

This applies to most of the `_single` classes. We should share them if possible.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence added a comment.

Ping


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence marked 6 inline comments as done.
achieveartificialintelligence added inline comments.



Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:164
 
+static DecodeStatus DecodeGPRF16RegisterClass(MCInst , uint64_t RegNo,
+  uint64_t Address,

MaskRay wrote:
> Use `functionName`.
> 
> There is inconsistency in the code base but `functionName` is used much more 
> than `FunctionName`.
I fix this in D112520



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:539
 
+let RegAltNameIndices = [ABIRegAltName] in {
+  foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,

jrtc27 wrote:
> This needs to be coordinated with D95588; you both define GPR pairs for RV32 
> but in different ways. There needs to be only one.
After D95588 is accepted, we will reuse this.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Fangrui Song via Phabricator via cfe-commits]

MaskRay added inline comments.



Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:164
 
+static DecodeStatus DecodeGPRF16RegisterClass(MCInst , uint64_t RegNo,
+  uint64_t Address,

Use `functionName`.

There is inconsistency in the code base but `functionName` is used much more 
than `FunctionName`.



Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:186
+  if (RegNo >= 32 || RegNo & 1) {
+return MCDisassembler::Fail;
+  }

https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:175
+   string OpcodeStr> {
+let Predicates = [HasStdExtD, IsRV64] in
+def : FPUnaryOpDynFrmAlias_single;

The indentation is inconsistent. Also applies to code above.



Comment at: llvm/test/MC/RISCV/rv64zhinx-valid.s:3
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zhinx -M no-aliases -d -r - \

`llvm-mc` can use `%s` instead of `< %s`

I heard that not using `<` is a bit more convenient for some Windows users. 
(They do suffer from `llc` and `opt`'s prevailing `< %s`)



Comment at: llvm/test/MC/RISCV/rv64zhinx-valid.s:12
+# CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc4]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I 
Base Instruction Set
+fcvt.l.h a0, t0, dyn

`[[@LINE+1]]` is a deprecated form.
Use `[[#@LINE+1]]`. Applies to many places elsewhere.



Comment at: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s:46
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3{{[[:space:]]}}
+fmadd.h x10, x11, x12, x13

What is `{{[[:space:]]}}` used for?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence updated this revision to Diff 379272.
achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.

Add arch info


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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s

Index: llvm/test/MC/RISCV/rv32i-invalid.s
===
--- llvm/test/MC/RISCV/rv32i-invalid.s
+++ llvm/test/MC/RISCV/rv32i-invalid.s
@@ -173,9 +173,9 @@
 amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions)
 fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
 fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point)
-fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer)
 fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer)
 fadd.d a0, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer)
+fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer)
 
 # Using floating point registers when integer registers are expected
 addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -72,6 +72,18 @@
 .attribute arch, "rv32ifzfh"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
+.attribute arch, "rv32izfinx"
+# CHECK: attribute  5, "rv32i2p0_zfinx0p1"
+
+.attribute arch, "rv32izdinx"
+# CHECK: attribute  5, "rv32i2p0_zfinx0p1_zdinx0p1"
+
+.attribute arch, "rv32izhinx"
+# CHECK: attribute  5, "rv32i2p0_zfinx0p1_zhinx0p1"
+
+.attribute arch, "rv32izhinxmin"
+# CHECK: attribute  5, "rv32i2p0_zfinx0p1_zhinxmin0p1"
+
 .attribute arch, "rv32ivzvamo_zvlsseg"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -49,42 +49,42 @@
  AssemblerPredicate<(all_of FeatureStdExtZfh),
  "'Zfh' (Half-Precision Floating-Point)">;
 
-def FeatureExtZfinx
+def FeatureStdExtZfinx
 : SubtargetFeature<"experimental-zfinx", "HasStdExtZfinx", "true",
"'Zfinx' (Float in Integer)">;
 def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
-   AssemblerPredicate<(all_of FeatureExtZfinx),
+   AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
 
-def FeatureExtZdinx
+def FeatureStdExtZdinx
 : SubtargetFeature<"experimental-zdinx", "HasStdExtZdinx", "true",
"'Zdinx' (Double in Integer)",
-   [FeatureExtZfinx]>;
+   [FeatureStdExtZfinx]>;
 def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
-   AssemblerPredicate<(all_of FeatureExtZdinx),
+   AssemblerPredicate<(all_of FeatureStdExtZdinx),
"'Zdinx' (Double in Integer)">;
 
-def FeatureExtZhinx
+def FeatureStdExtZhinx
 : SubtargetFeature<"experimental-zhinx", "HasStdExtZhinx", "true",
"'Zhinx' (Half Float in Integer)",
-   [FeatureExtZfinx]>;
+   [FeatureStdExtZfinx]>;
 def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
-   AssemblerPredicate<(all_of FeatureExtZhinx),
+   AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
 
-def FeatureExtZhinxmin
+def FeatureStdExtZhinxmin
 : SubtargetFeature<"experimental-zhinxmin", "HasStdExtZhinxmin", "true",
"'Zhinxmin' (Half Float in Integer Minimal)",
-   [FeatureExtZfinx]>;
+   [FeatureStdExtZfinx]>;
 def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
-  AssemblerPredicate<(all_of FeatureExtZhinxmin),
+  AssemblerPredicate<(all_of 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D93298#3020917 , @frasercrmck wrote:

> In D93298#3014160 , @jrtc27 wrote:
>
>> The amount of duplication here really depresses me and is only going to get 
>> worse once codegen is added, but TableGen isn't able to have operands that 
>> use different register classes based on even HwMode, that I know of, and 
>> whilst you could make use of multi classes to generate both versions of the 
>> instructions you can't easily do that for patterns, so I don't know what the 
>> right answer is.
>
> Do we know if it's possible to teach TableGen how to do that? This extension 
> seems like a good reason to implement such a feature as the duplication 
> really is unfortunate.
>
> I thought that `MCOperandInfo` may be an issue but there's already dynamic 
> lookup there to support `isLookupPtrRegClass`.

@frasercrmck Thank you for your guidance. I don't quite understand what is the 
role of `isLookupPtrRegClass` here, or how to use `isLookupPtrRegClass`? Could 
you please give me more detailed instructions?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Fraser Cormack via Phabricator via cfe-commits]

frasercrmck added a comment.

In D93298#3014160 , @jrtc27 wrote:

> The amount of duplication here really depresses me and is only going to get 
> worse once codegen is added, but TableGen isn't able to have operands that 
> use different register classes based on even HwMode, that I know of, and 
> whilst you could make use of multi classes to generate both versions of the 
> instructions you can't easily do that for patterns, so I don't know what the 
> right answer is.

Do we know if it's possible to teach TableGen how to do that? This extension 
seems like a good reason to implement such a feature as the duplication really 
is unfortunate.

I thought that `MCOperandInfo` may be an issue but there's already dynamic 
lookup there to support `isLookupPtrRegClass`.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence updated this revision to Diff 374131.
achieveartificialintelligence added a comment.

Address @jrtc27 's comment.


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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZhinx.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,83 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3{{[[:space:]]}}
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7{{[[:space:]]}}
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3{{[[:space:]]}}
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6{{[[:space:]]}}
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2{{[[:space:]]}}
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5{{[[:space:]]}}
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7{{[[:space:]]}}
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5{{[[:space:]]}}
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6{{[[:space:]]}}

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:539
 
+let RegAltNameIndices = [ABIRegAltName] in {
+  foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,

This needs to be coordinated with D95588; you both define GPR pairs for RV32 
but in different ways. There needs to be only one.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

The amount of duplication here really depresses me and is only going to get 
worse once codegen is added, but TableGen isn't able to have operands that use 
different register classes based on even HwMode, that I know of, and whilst you 
could make use of multi classes to generate both versions of the instructions 
you can't easily do that for patterns, so I don't know what the right answer is.




Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td:193
+let Predicates = [HasStdExtZdinx, IsRV32] in {
+let DecoderNamespace = "RV32DZfinx" in {
+def FMADD_D_IN32X  : FPFMADINX_rrr_frm,

Old extension name


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

ping.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 373170.
achieveartificialintelligence added a comment.

fix CI error


Repository:
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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZhinx.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,83 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3{{[[:space:]]}}
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7{{[[:space:]]}}
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3{{[[:space:]]}}
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6{{[[:space:]]}}
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2{{[[:space:]]}}
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5{{[[:space:]]}}
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7{{[[:space:]]}}
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5{{[[:space:]]}}
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6{{[[:space:]]}}
+fcvt.wu.h a1, s6

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 372866.
achieveartificialintelligence added a comment.

Updating D93298 : [RISCV] add the MC layer 
support of Zfinx extension


Repository:
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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZhinx.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,83 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3{{[[:space:]]}}
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7{{[[:space:]]}}
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3{{[[:space:]]}}
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6{{[[:space:]]}}
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2{{[[:space:]]}}
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5{{[[:space:]]}}
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7{{[[:space:]]}}
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5{{[[:space:]]}}
+fcvt.w.h a0, s5
+# 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 372863.
achieveartificialintelligence added a comment.

support zfinx-1.0-rc


Repository:
  rG LLVM Github Monorepo

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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZhinx.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzfdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfhinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.s s1, s2, s2
+# CHECK-ALIAS: fabs.s s1, s2
+fabs.s s1, s2
+# CHECK-INST: fsgnjn.s s2, s3, s3
+# CHECK-ALIAS: fneg.s s2, s3
+fneg.s s2, s3
+
+# CHECK-INST: flt.s tp, s6, s5
+# CHECK-ALIAS: flt.s tp, s6, s5
+fgt.s x4, s5, s6
+# CHECK-INST: fle.s t2, s1, s0
+# CHECK-ALIAS: fle.s t2, s1, s0
+fge.s x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.s a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.s a0, a1, a2, a3{{[[:space:]]}}
+fmadd.s x10, x11, x12, x13
+# CHECK-INST: fmsub.s a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.s a4, a5, a6, a7{{[[:space:]]}}
+fmsub.s x14, x15, x16, x17
+# CHECK-INST: fnmsub.s s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.s s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.s x18, x19, x20, x21
+# CHECK-INST: fnmadd.s s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.s s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.s x22, x23, x24, x25
+# CHECK-INST: fadd.s s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.s s10, s11, t3{{[[:space:]]}}
+fadd.s x26, x27, x28
+# CHECK-INST: fsub.s t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.s t4, t5, t6{{[[:space:]]}}
+fsub.s x29, x30, x31
+# CHECK-INST: fmul.s s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.s s0, s1, s2{{[[:space:]]}}
+fmul.s s0, s1, s2
+# CHECK-INST: fdiv.s s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.s s3, s4, s5{{[[:space:]]}}
+fdiv.s s3, s4, s5
+# CHECK-INST: sqrt.s s6, s7, dyn
+# CHECK-ALIAS: sqrt.s s6, s7{{[[:space:]]}}
+fsqrt.s s6, s7
+# CHECK-INST: fcvt.w.s a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.s a0, s5{{[[:space:]]}}
+fcvt.w.s a0, s5
+# CHECK-INST: fcvt.wu.s a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.s a1, s6{{[[:space:]]}}
+fcvt.wu.s 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.

In D93298#2544775 , @asb wrote:

> In D93298#2544459 , @StephenFan 
> wrote:
>
>> According to  @jrtc27 's review that is 
>> "As for Zfinx itself, well, the idea is fine, but I really detest the way 
>> it's being done as an extension to F/D/Zfh. Running F code on an FZfh core 
>> _does not work_ so it is not an _extension_. Instead it should really be a 
>> set of separate extensions to I/E that conflict with F/D/Zfh, i.e. Zfinx, 
>> Zdinx and Zfhinx, but apparently asking code that complies with a ratified 
>> standard to change itself in order to not break when a new extension is 
>> introduced is a-ok in the RISC-V world.". 
>> We split the Zfinx into 3 separate extensions which is Zfinx, Zdinx, and 
>> Zfhinx.
>
> Ah I see. I interpreted jrtc27's comment as a general gripe about the spec 
> (which perhaps could be relayed to those working on the zfinx spec) rather as 
> a direction for changing this patch in particular. Anyway, it's a detail that 
> shouldn't affect an initial review. Thanks for clarifying.

Oh, I'm sorry. It seems that I misunderstood @jrtc27 's comment. I will merge 
the Zfinx, Zdinx, Zfhinx into Zfinx if this patch is ready for accepting.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

In D93298#2544775 , @asb wrote:

> In D93298#2544459 , @StephenFan 
> wrote:
>
>> According to  @jrtc27 's review that is 
>> "As for Zfinx itself, well, the idea is fine, but I really detest the way 
>> it's being done as an extension to F/D/Zfh. Running F code on an FZfh core 
>> _does not work_ so it is not an _extension_. Instead it should really be a 
>> set of separate extensions to I/E that conflict with F/D/Zfh, i.e. Zfinx, 
>> Zdinx and Zfhinx, but apparently asking code that complies with a ratified 
>> standard to change itself in order to not break when a new extension is 
>> introduced is a-ok in the RISC-V world.". 
>> We split the Zfinx into 3 separate extensions which is Zfinx, Zdinx, and 
>> Zfhinx.
>
> Ah I see. I interpreted jrtc27's comment as a general gripe about the spec 
> (which perhaps could be relayed to those working on the zfinx spec) rather as 
> a direction for changing this patch in particular. Anyway, it's a detail that 
> shouldn't affect an initial review. Thanks for clarifying.

Well, it was "I'm uneasy about accepting a patch adding an extension that is 
fundamentally flawed in its current form" (unlike some of the others where 
they're subject to change but don't _break_ anything).


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D93298#2544459 , @StephenFan wrote:

> According to  @jrtc27 's review that is 
> "As for Zfinx itself, well, the idea is fine, but I really detest the way 
> it's being done as an extension to F/D/Zfh. Running F code on an FZfh core 
> _does not work_ so it is not an _extension_. Instead it should really be a 
> set of separate extensions to I/E that conflict with F/D/Zfh, i.e. Zfinx, 
> Zdinx and Zfhinx, but apparently asking code that complies with a ratified 
> standard to change itself in order to not break when a new extension is 
> introduced is a-ok in the RISC-V world.". 
> We split the Zfinx into 3 separate extensions which is Zfinx, Zdinx, and 
> Zfhinx.

Ah I see. I interpreted jrtc27's comment as a general gripe about the spec 
(which perhaps could be relayed to those working on the zfinx spec) rather as a 
direction for changing this patch in particular. Anyway, it's a detail that 
shouldn't affect an initial review. Thanks for clarifying.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.

In D93298#253 , @asb wrote:

> I started reviewing this alongside the specification in 
> https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc. At the time 
> of writing, it seems to define "zfinx" but not "zfhinx" and "zfdinx" as seem 
> to be used in this patch. I think intent is that rv32ifd_zfinx is the 
> equivalent of "zfdinx" in this patch. Is there a reason to go for different 
> naming, or a different version of the spec I should be looking at?

According to  @jrtc27 's review that is 
"As for Zfinx itself, well, the idea is fine, but I really detest the way it's 
being done as an extension to F/D/Zfh. Running F code on an FZfh core _does not 
work_ so it is not an _extension_. Instead it should really be a set of 
separate extensions to I/E that conflict with F/D/Zfh, i.e. Zfinx, Zdinx and 
Zfhinx, but apparently asking code that complies with a ratified standard to 
change itself in order to not break when a new extension is introduced is a-ok 
in the RISC-V world.". 
We split the Zfinx into 3 separate extensions which is Zfinx, Zdinx, and Zfhinx.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

I started reviewing this alongside the specification in 
https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc. At the time 
of writing, it seems to define "zfinx" but not "zfhinx" and "zfdinx" as seem to 
be used in this patch. I think intent is that rv32ifd_zfinx is the equivalent 
of "zfdinx" in this patch. Is there a reason to go for different naming, or a 
different version of the spec I should be looking at?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.
Herald added a subscriber: vkmr.

Ping


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 314879.
achieveartificialintelligence marked 5 inline comments as done.
achieveartificialintelligence added a comment.

Thanks for suggestions. We updated the code again.


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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfdinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfhinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zfdinx-invalid.s
  llvm/test/MC/RISCV/rv32zfdinx-valid.s
  llvm/test/MC/RISCV/rv32zfhinx-invalid.s
  llvm/test/MC/RISCV/rv32zfhinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv64zfdinx-invalid.s
  llvm/test/MC/RISCV/rv64zfdinx-valid.s
  llvm/test/MC/RISCV/rv64zfhinx-invalid.s
  llvm/test/MC/RISCV/rv64zfhinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rvzfdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfhinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.s s1, s2, s2
+# CHECK-ALIAS: fabs.s s1, s2
+fabs.s s1, s2
+# CHECK-INST: fsgnjn.s s2, s3, s3
+# CHECK-ALIAS: fneg.s s2, s3
+fneg.s s2, s3
+
+# CHECK-INST: flt.s tp, s6, s5
+# CHECK-ALIAS: flt.s tp, s6, s5
+fgt.s x4, s5, s6
+# CHECK-INST: fle.s t2, s1, s0
+# CHECK-ALIAS: fle.s t2, s1, s0
+fge.s x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.s a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.s a0, a1, a2, a3{{[[:space:]]}}
+fmadd.s x10, x11, x12, x13
+# CHECK-INST: fmsub.s a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.s a4, a5, a6, a7{{[[:space:]]}}
+fmsub.s x14, x15, x16, x17
+# CHECK-INST: fnmsub.s s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.s s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.s x18, x19, x20, x21
+# CHECK-INST: fnmadd.s s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.s s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.s x22, x23, x24, x25
+# CHECK-INST: fadd.s s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.s s10, s11, t3{{[[:space:]]}}
+fadd.s x26, x27, x28
+# CHECK-INST: fsub.s t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.s t4, t5, t6{{[[:space:]]}}
+fsub.s x29, x30, x31
+# CHECK-INST: fmul.s s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.s s0, s1, s2{{[[:space:]]}}
+fmul.s s0, s1, s2
+# CHECK-INST: fdiv.s s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.s s3, s4, s5{{[[:space:]]}}
+fdiv.s s3, s4, s5
+# CHECK-INST: sqrt.s s6, s7, dyn
+# CHECK-ALIAS: sqrt.s s6, s7{{[[:space:]]}}
+fsqrt.s s6, s7
+# CHECK-INST: fcvt.w.s a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.s a0, s5{{[[:space:]]}}
+fcvt.w.s a0, s5
+# CHECK-INST: fcvt.wu.s a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.s a1, s6{{[[:space:]]}}
+fcvt.wu.s a1, s6
+# CHECK-INST: fcvt.s.w t6, a4, dyn
+# CHECK-ALIAS: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:943
+static MCRegister convertGPRToGPRPD(MCRegister Reg) {
+  assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && !((Reg - RISCV::X0) & 1) &&
+ "Invalid register");

Use "% 2  == 0" since the next line uses "/ 2"


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[luxufan via Phabricator via cfe-commits]

StephenFan added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1663
 
+OperandMatchResultTy RISCVAsmParser::parseGPRasFPR(OperandVector ) {
+  switch (getLexer().getKind()) {

StephenFan wrote:
> jrtc27 wrote:
> > Why can't you just use parseRegister?
> use the default parseRegister will make the test cases in other files fail. 
> For example:
> 
> ```
> fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for 
> instruction
> ```
> this is the test case in rv64d-invalid.s. If uses the default parseRegister. 
> the invalid operand is in column 14 (ft3 operand) instead of 10 (a3 operand).
> Why can't you just use parseRegister?

use the default parseRegister will make the test cases in other files fail. For 
example:

```
fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
```
this is the test case in rv64d-invalid.s. If uses the default parseRegister. 
the invalid operand is in column 14 (ft3 operand) instead of 10 (a3 operand).



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:59
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPUnaryOpINX_r funct7, bits<3> funct3, RegisterOperand rdty,
+RegisterOperand rs1ty, string opcodestr>

StephenFan wrote:
> jrtc27 wrote:
> > Don't duplicate all these, they're identical to the normal floating point 
> > versions.
> Because of normal floating point version only support RegisterClass, but we 
> use the RegisterOperand, so we change this. Or if there is more convenient 
> way to resolve this?
> Because of normal floating point version only support RegisterClass, but we 
> use the RegisterOperand, so we change this. Or if there is more convenient 
> way to resolve this?

Because of normal floating point version only support RegisterClass, but we use 
the RegisterOperand, so we change this. Or if there is more convenient way to 
resolve this?



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:468
+   Reg.AltNames> {
+  let SubRegIndices = [sub_32, sub_32_hi];
+}

StephenFan wrote:
> jrtc27 wrote:
> > Does this hard-coding of 32 cause issues on RV64?
> I don't known if it will cause issues on RV64. But the zfinx spec specifies 
> that register pairs are only used in RV32
> Does this hard-coding of 32 cause issues on RV64?

I don't known if it will cause issues on RV64. But the zfinx spec specifies 
that register pairs are only used in RV32


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[luxufan via Phabricator via cfe-commits]

StephenFan added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1663
 
+OperandMatchResultTy RISCVAsmParser::parseGPRasFPR(OperandVector ) {
+  switch (getLexer().getKind()) {

jrtc27 wrote:
> Why can't you just use parseRegister?
use the default parseRegister will make the test cases in other files fail. For 
example:

```
fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
```
this is the test case in rv64d-invalid.s. If uses the default parseRegister. 
the invalid operand is in column 14 (ft3 operand) instead of 10 (a3 operand).



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:59
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPUnaryOpINX_r funct7, bits<3> funct3, RegisterOperand rdty,
+RegisterOperand rs1ty, string opcodestr>

jrtc27 wrote:
> Don't duplicate all these, they're identical to the normal floating point 
> versions.
Because of normal floating point version only support RegisterClass, but we use 
the RegisterOperand, so we change this. Or if there is more convenient way to 
resolve this?



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:468
+   Reg.AltNames> {
+  let SubRegIndices = [sub_32, sub_32_hi];
+}

jrtc27 wrote:
> Does this hard-coding of 32 cause issues on RV64?
I don't known if it will cause issues on RV64. But the zfinx spec specifies 
that register pairs are only used in RV32


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence added a comment.

In D93298#2477105 , @jrtc27 wrote:

> Your tests look like copies of the F/D/Zfh tests with not all the comments 
> updated and instances of tests that just don't make sense for Zfinx. I only 
> skimmed them and picked up a few issues, I haven't gone through them 
> thoroughly, please do that yourself.

Thanks for your advices. We will solve the issues you have mentioned above.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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jrtc27 added a comment.

Your tests look like copies of the F/D/Zfh tests with not all the comments 
updated and instances of tests that just don't make sense for Zfinx. I only 
skimmed them and picked up a few issues, I haven't gone through them 
thoroughly, please do that yourself.




Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:341
 
+  bool isGPRasFPR() const { return isGPR() && IsGPRasFPR; }
+

as -> As everywhere



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:975-977
+  // As the parser couldn't differentiate an GPRH, GPRF, GPRD, GPRPD from an
+  // GPR, coerce the register from GPR to these if necessary.
+  if (IsRegGPR && Kind == MCK_GPRPD && !isRV64()) {

Comment doesn't match what you do, and it's "a GPR" not "an GPR". Are there 
tests that demonstrate all these potentially-problematic cases as working?



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1663
 
+OperandMatchResultTy RISCVAsmParser::parseGPRasFPR(OperandVector ) {
+  switch (getLexer().getKind()) {

Why can't you just use parseRegister?



Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:403
+!STI.getFeatureBits()[RISCV::Feature64Bit]) {
+  LLVM_DEBUG(dbgs() << "Trying RV32DZfinx table (Double in Integer and"
+  "rv32)\n");

RV32Zfdinx?



Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:414-416
+STI.getFeatureBits()[RISCV::FeatureExtZfhinx] ||
+(STI.getFeatureBits()[RISCV::FeatureExtZdinx] &&
+ STI.getFeatureBits()[RISCV::Feature64Bit])) {

Don't all these imply Zfinx? Should just need to check if Zfinx.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:20
+
+def GPRasFPR : AsmOperandClass {
+  let Name = "GPRasFPR";

I don't see why the default `parseRegister` doesn't work, then you can ditch 
all these `AsmOperandClass`es.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:35
+
+def GPRHOp : RegisterOperand {
+  let ParserMatchClass = GPRasFPR;

I don't like that all these exist, but not sure if there's a nice way to avoid 
them? If not, please use 16/32/64 suffixes like for FPRs rather than 
H/D/nothing, it gets confusing otherwise.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:59
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPUnaryOpINX_r funct7, bits<3> funct3, RegisterOperand rdty,
+RegisterOperand rs1ty, string opcodestr>

Don't duplicate all these, they're identical to the normal floating point 
versions.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:71
+
+// RV32/64 and zfh extension
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in

Zfh



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:119
+
+// RV64 D extension
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in

Zfd



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:177
+
+// instructions in zfh extension
+let Predicates = [HasStdExtZfhinx] in {

Instruction in Zfhinx extension



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:177
+
+// instructions in zfh extension
+let Predicates = [HasStdExtZfhinx] in {

jrtc27 wrote:
> Instruction in Zfhinx extension
It'd be nicer if the file were split up into multiple separate files the same 
way as we do for F/D/Zfh rather than having a single big file with everything.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:275
+
+// instructions in F extension and rv64
+let Predicates = [HasStdExtZfhinx, IsRV64] in {

Instructions in Zfhinx extension on RV64 / Instructions in RV64Zfhinx



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:316
+
+// instructions in F extension, no matter rv32 or rv64
+let Predicates = [HasStdExtZfinx] in {

Instructions in Zfinx extension



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:415
+
+// instructions that in F extention and rv64
+let Predicates = [HasStdExtZfinx, IsRV64] in {

etc, I won't keep repeating myself



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:113
[i32,  i64]>;
+def ZfinxLenVT : ValueTypeByHwMode<[RV32, RV64],
+   [f32, f64]>;

This doesn't seem to be used.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:468
+   Reg.AltNames> {
+  let SubRegIndices = [sub_32, sub_32_hi];
+}

Does this hard-coding of 32 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.

In D93298#2457925 , @kito-cheng wrote:

> Do you have implement register pair for rv32ifd_zfinx? I didn't saw the 
> related implementation, but I could be wrong since I am not LLVM expert, in 
> case you have implemented, you need a test case for that.

We have solved this now.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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StephenFan added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:983
+  }
+
   return Match_InvalidOperand;

It seems like that this function is not useful.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence updated this revision to Diff 314349.
achieveartificialintelligence marked 2 inline comments as done.
achieveartificialintelligence added a comment.

Including Zfinx, zdinx. Zfhinx.


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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfhinx-invalid.s
  llvm/test/MC/RISCV/rv32zfhinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfhinx-invalid.s
  llvm/test/MC/RISCV/rv64zfhinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfhinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.s s1, s2, s2
+# CHECK-ALIAS: fabs.s s1, s2
+fabs.s s1, s2
+# CHECK-INST: fsgnjn.s s2, s3, s3
+# CHECK-ALIAS: fneg.s s2, s3
+fneg.s s2, s3
+
+# CHECK-INST: flt.s tp, s6, s5
+# CHECK-ALIAS: flt.s tp, s6, s5
+fgt.s x4, s5, s6
+# CHECK-INST: fle.s t2, s1, s0
+# CHECK-ALIAS: fle.s t2, s1, s0
+fge.s x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.s a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.s a0, a1, a2, a3{{[[:space:]]}}
+fmadd.s x10, x11, x12, x13
+# CHECK-INST: fmsub.s a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.s a4, a5, a6, a7{{[[:space:]]}}
+fmsub.s x14, x15, x16, x17
+# CHECK-INST: fnmsub.s s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.s s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.s x18, x19, x20, x21
+# CHECK-INST: fnmadd.s s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.s s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.s x22, x23, x24, x25
+# CHECK-INST: fadd.s s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.s s10, s11, t3{{[[:space:]]}}
+fadd.s x26, x27, x28
+# CHECK-INST: fsub.s t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.s t4, t5, t6{{[[:space:]]}}
+fsub.s x29, x30, x31
+# CHECK-INST: fmul.s s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.s s0, s1, s2{{[[:space:]]}}
+fmul.s s0, s1, s2
+# CHECK-INST: fdiv.s s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.s s3, s4, s5{{[[:space:]]}}
+fdiv.s s3, s4, s5
+# CHECK-INST: sqrt.s s6, s7, dyn
+# CHECK-ALIAS: sqrt.s s6, s7{{[[:space:]]}}
+fsqrt.s s6, s7
+# CHECK-INST: fcvt.w.s a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.s a0, s5{{[[:space:]]}}
+fcvt.w.s a0, s5
+# CHECK-INST: fcvt.wu.s a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.s a1, s6{{[[:space:]]}}
+fcvt.wu.s a1, s6
+# CHECK-INST: fcvt.s.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.s.w t6, a4{{[[:space:]]}}
+fcvt.s.w t6, a4
+# CHECK-INST: fcvt.s.wu s0, a5, 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[luxufan via Phabricator via cfe-commits]

StephenFan added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:102
+: InstAlias;
+

use GPR as instruction operand may cause the codegen part of zfinx report 
errors. Because the GPR has data type i32 or i64, However, the zfinx will deal 
with the data type f64 or f32.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Sunny via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

Thanks. I've updated it.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Sunny via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 312444.

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Files:
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32d-invalid.s
  llvm/test/MC/RISCV/rv32zfh-invalid.s
  llvm/test/MC/RISCV/rvzfinx-valid.s

Index: llvm/test/MC/RISCV/rvzfinx-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzfinx-valid.s
@@ -0,0 +1,333 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zfinx %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zfinx %s \
+# RUN:| llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zfinx %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmadd.h a0, a1, a2, a3
+# CHECK-INST: fmadd.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 6c 
+
+fmsub.h a0, a1, a2, a3
+# CHECK-INST: fmsub.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 6c 
+
+fnmsub.h a0, a1, a2, a3
+# CHECK-INST: fnmsub.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 6c 
+
+fnmadd.h a0, a1, a2, a3
+# CHECK-INST: fnmadd.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x4f,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4f f5 c5 6c 
+
+fadd.h a0, a1, a2
+# CHECK-INST: fadd.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x04]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 04 
+
+fsub.h a0, a1, a2
+# CHECK-INST: fsub.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x0c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 0c 
+
+fmul.h a0, a1, a2
+# CHECK-INST: fmul.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x14]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 14 
+
+fdiv.h a0, a1, a2
+# CHECK-INST: fdiv.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x1c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 1c 
+
+fsqrt.h a0, a1
+# CHECK-INST: fsqrt.h a0, a1
+# CHECK-ENCODING: [0x53,0xf5,0x05,0x5c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 05 5c 
+
+fsgnj.h a0, a1, a2
+# CHECK-INST: fsgnj.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 24 
+
+fsgnjn.h a0, a1, a2
+# CHECK-INST: fsgnjn.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 24 
+
+fsgnjx.h a0, a1, a2
+# CHECK-INST: fsgnjx.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 24 
+
+fmin.h a0, a1, a2
+# CHECK-INST: fmin.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x2c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 2c 
+
+fmax.h a0, a1, a2
+# CHECK-INST: fmax.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x2c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 2c 
+
+feq.h a0, a1, a2
+# CHECK-INST: feq.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 a4 
+
+flt.h a0, a1, a2
+# CHECK-INST: flt.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 a4 
+
+fle.h a0, a1, a2
+# CHECK-INST: fle.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 a4 
+
+fclass.h a0, a1
+# CHECK-INST: fclass.h a0, a1
+# CHECK-ENCODING: [0x53,0x95,0x05,0xe4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 05 e4 
+
+fmadd.s a0, a1, a2, a3
+# CHECK-INST: fmadd.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 68 
+
+fmsub.s a0, a1, a2, a3
+# CHECK-INST: fmsub.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 68 
+
+fnmsub.s a0, a1, a2, a3
+# CHECK-INST: fnmsub.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 68 
+
+fnmadd.s a0, a1, a2, a3
+# CHECK-INST: fnmadd.s a0, a1, 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Sunny via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 312395.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32d-invalid.s
  llvm/test/MC/RISCV/rv32zfh-invalid.s
  llvm/test/MC/RISCV/rvzfinx-valid.s

Index: llvm/test/MC/RISCV/rvzfinx-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzfinx-valid.s
@@ -0,0 +1,333 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zfinx %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zfinx %s \
+# RUN:| llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zfinx %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmadd.h a0, a1, a2, a3
+# CHECK-INST: fmadd.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 6c 
+
+fmsub.h a0, a1, a2, a3
+# CHECK-INST: fmsub.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 6c 
+
+fnmsub.h a0, a1, a2, a3
+# CHECK-INST: fnmsub.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 6c 
+
+fnmadd.h a0, a1, a2, a3
+# CHECK-INST: fnmadd.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x4f,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4f f5 c5 6c 
+
+fadd.h a0, a1, a2
+# CHECK-INST: fadd.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x04]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 04 
+
+fsub.h a0, a1, a2
+# CHECK-INST: fsub.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x0c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 0c 
+
+fmul.h a0, a1, a2
+# CHECK-INST: fmul.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x14]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 14 
+
+fdiv.h a0, a1, a2
+# CHECK-INST: fdiv.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x1c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 1c 
+
+fsqrt.h a0, a1
+# CHECK-INST: fsqrt.h a0, a1
+# CHECK-ENCODING: [0x53,0xf5,0x05,0x5c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 05 5c 
+
+fsgnj.h a0, a1, a2
+# CHECK-INST: fsgnj.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 24 
+
+fsgnjn.h a0, a1, a2
+# CHECK-INST: fsgnjn.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 24 
+
+fsgnjx.h a0, a1, a2
+# CHECK-INST: fsgnjx.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 24 
+
+fmin.h a0, a1, a2
+# CHECK-INST: fmin.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x2c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 2c 
+
+fmax.h a0, a1, a2
+# CHECK-INST: fmax.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x2c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 2c 
+
+feq.h a0, a1, a2
+# CHECK-INST: feq.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 a4 
+
+flt.h a0, a1, a2
+# CHECK-INST: flt.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 a4 
+
+fle.h a0, a1, a2
+# CHECK-INST: fle.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 a4 
+
+fclass.h a0, a1
+# CHECK-INST: fclass.h a0, a1
+# CHECK-ENCODING: [0x53,0x95,0x05,0xe4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 05 e4 
+
+fmadd.s a0, a1, a2, a3
+# CHECK-INST: fmadd.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 68 
+
+fmsub.s a0, a1, a2, a3
+# CHECK-INST: fmsub.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 68 
+
+fnmsub.s a0, a1, a2, a3
+# CHECK-INST: fnmsub.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 68 
+
+fnmadd.s a0, a1, 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Do you have implement register pair for rv32ifd_zfinx? I didn't saw the related 
implementation, but I could be wrong since I am not LLVM expert, in case you 
have implemented, you need a test case for that.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.h:40
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false), HasD(false),
-HasC(false), HasB(false), HasV(false), HasZfh(false) {
 LongDoubleWidth = 128;

We really should just initialize these to false at their declarations so you 
don't have to change the constructor initializer list every time one is added.. 
I might submit a patch for that.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

Firstly, please generate your diffs with full context (-U with a 
sufficiently-large number). Secondly, can we avoid having to do a bunch of 
duplication with some clever use of multiclasses for F/D/Zfh and pseudos? 
Though maybe it's small enough that the duplication is easier to reason about 
than an obfuscated abstracted version.

Also, do you not need more predicates? You can't just assume all of F, D and 
Zfh exist.

As for Zfinx itself, well, the idea is fine, but I really detest the way it's 
being done as an extension to F/D/Zfh. Running F code on an FZfh core _does not 
work_ so it is not an _extension_. Instead it should really be a set of 
separate extensions to I/E that conflict with F/D/Zfh, i.e. Zfinx, Zdinx and 
Zfhinx, but apparently asking code that complies with a ratified standard to 
change itself in order to not break when a new extension is introduced is a-ok 
in the RISC-V world.




Comment at: llvm/test/MC/RISCV/rv32zfh-invalid.s:33
-# Integer registers where FP regs are expected
-fadd.h a2, a1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-

These need to stay, but presumably instead as errors about Zfinx not being 
enabled?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Sunny via Phabricator via cfe-commits]

achieveartificialintelligence created this revision.
achieveartificialintelligence added reviewers: HsiangKai, rkruppe, kito-cheng, 
craig.topper, jrtc27, luismarques.
Herald added subscribers: frasercrmck, NickHung, evandro, apazos, 
sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
achieveartificialintelligence requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93298

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32d-invalid.s
  llvm/test/MC/RISCV/rv32zfh-invalid.s
  llvm/test/MC/RISCV/rvzfinx-valid.s

Index: llvm/test/MC/RISCV/rvzfinx-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzfinx-valid.s
@@ -0,0 +1,333 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zfinx %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zfinx %s \
+# RUN:| llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zfinx %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmadd.h a0, a1, a2, a3
+# CHECK-INST: fmadd.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 6c 
+
+fmsub.h a0, a1, a2, a3
+# CHECK-INST: fmsub.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 6c 
+
+fnmsub.h a0, a1, a2, a3
+# CHECK-INST: fnmsub.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 6c 
+
+fnmadd.h a0, a1, a2, a3
+# CHECK-INST: fnmadd.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x4f,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4f f5 c5 6c 
+
+fadd.h a0, a1, a2
+# CHECK-INST: fadd.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x04]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 04 
+
+fsub.h a0, a1, a2
+# CHECK-INST: fsub.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x0c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 0c 
+
+fmul.h a0, a1, a2
+# CHECK-INST: fmul.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x14]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 14 
+
+fdiv.h a0, a1, a2
+# CHECK-INST: fdiv.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x1c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 1c 
+
+fsqrt.h a0, a1
+# CHECK-INST: fsqrt.h a0, a1
+# CHECK-ENCODING: [0x53,0xf5,0x05,0x5c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 05 5c 
+
+fsgnj.h a0, a1, a2
+# CHECK-INST: fsgnj.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 24 
+
+fsgnjn.h a0, a1, a2
+# CHECK-INST: fsgnjn.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 24 
+
+fsgnjx.h a0, a1, a2
+# CHECK-INST: fsgnjx.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 24 
+
+fmin.h a0, a1, a2
+# CHECK-INST: fmin.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x2c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 2c 
+
+fmax.h a0, a1, a2
+# CHECK-INST: fmax.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x2c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 2c 
+
+feq.h a0, a1, a2
+# CHECK-INST: feq.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 a4 
+
+flt.h a0, a1, a2
+# CHECK-INST: flt.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 a4 
+
+fle.h a0, a1, a2
+# CHECK-INST: fle.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 a4 
+
+fclass.h a0, a1
+# CHECK-INST: fclass.h a0, a1
+# CHECK-ENCODING: [0x53,0x95,0x05,0xe4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 05 e4 
+