[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

sunshaoce added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:599 + Sched<[]>; +def UKSTSA32 : RVPBinary<0b1110001, 0b011, "ukstsa32">, + Sched<[]>; `0b011` should be `0b010`.

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

sunshaoce added a comment. In D95588#3641900 , @Jim wrote: > In D95588#3622052 , @sunshaoce wrote: > >> Hello @Jim! We are developing the P extension, are you still maintaining >> this patch? Or would you mind

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. In D95588#3622052 , @sunshaoce wrote: > Hello @Jim! We are developing the P extension, are you still maintaining this > patch? Or would you mind co-development together? Yes, I am still on developing the P extension. But it seems

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

sunshaoce added a comment. Hello @Jim! We are developing the P extension, are you still maintaining this patch? Or would you mind co-development together? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim marked an inline comment as done. Jim added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll:4360 ; LMULMAX1-RV64-NEXT:vid.v v10 +; LMULMAX1-RV64-NEXT:vadd.vi v11, v10, 2 +; LMULMAX1-RV64-NEXT:lui a2, %hi(.LCPI132_2)

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim marked 2 inline comments as done. Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:909 + +// kmar64 has a aliased instruction kmada32 belong to zpn sub-extension on RV64. +let DecoderNamespace = "RISCV32Zpsfoperand_", Jim

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

jrtc27 added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:219 +def GPR32Pairs : RegisterTuples<[gpr32_pair_lo, gpr32_pair_hi], +[(add X0, X2, X4, X6, + X8, X10, X12, X14,

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim marked 7 inline comments as done. Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:909 + +// kmar64 has a aliased instruction kmada32 belong to zpn sub-extension on RV64. +let DecoderNamespace = "RISCV32Zpsfoperand_", jrtc27

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

jrtc27 added inline comments. Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:442 + +if (STI.getFeatureBits()[RISCV::FeatureExtZpsfoperand] && +!STI.getFeatureBits()[RISCV::Feature64Bit]) { Jim wrote: > jrtc27 wrote: > > The

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. In D95588#3003090 , @Jim wrote: > Any feedback? I think this patch is good enough to be accepted. Ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Any feedback? I think this patch is good enough to be accepted. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Hi, @jrtc27 About the concern the invalid combination RV32 + zprvsfextra on riscv attribute, I upload a patch D108189 based on @kito-cheng 's patch D105168 to forbid emitting rv32+zprvsfextra arch

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim marked an inline comment as done. Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:186-188 + [FeatureExtZpsfoperand, +FeatureExtZpn, +FeatureExtZprvsfextra]>; jrtc27

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

jrtc27 added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:186-188 + [FeatureExtZpsfoperand, +FeatureExtZpn, +FeatureExtZprvsfextra]>; Jim wrote: > jrtc27 wrote: > > These aren't

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Hi @jrtc27, any further feedback? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Kindly ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

jrtc27 added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69 +def sub_lo : SubRegIndex<32>; +def sub_hi : SubRegIndex<32, 32>; Jim wrote: > jrtc27 wrote: > > Jim wrote: > > > Jim wrote: > > > > luismarques wrote: > > > > > jrtc27

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. @jrtc27 Any more feedback? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim marked 8 inline comments as done. Jim added inline comments. Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:442 + +if (STI.getFeatureBits()[RISCV::FeatureExtZpsfoperand] && +!STI.getFeatureBits()[RISCV::Feature64Bit]) {

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. In D95588#2898470 , @jrtc27 wrote: > Oh, technically none of the clang changes belong in this patch. Those are for > the Clang driver and preprocessor, not the MC layer which is purely llvm. I move the clang changes to D95589

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

jrtc27 added a comment. Oh, technically none of the clang changes belong in this patch. Those are for the Clang driver and preprocessor, not the MC layer which is purely llvm. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

jrtc27 added a comment. I can't help but feel the assembly syntax for the register pair instructions shouldn't include both registers (perhaps in curly braces). The implicit use of the other register when reading the source is rather ugly, and particularly hard to remember when the RV64

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

craig.topper added a comment. I think this looks good to me. @luismarques or @jrtc27 any further feedback? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69 +def sub_lo : SubRegIndex<32>; +def sub_hi : SubRegIndex<32, 32>; Jim wrote: > luismarques wrote: > > jrtc27 wrote: > > > This assumes RV32, and is not clear it applies to

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69 +def sub_lo : SubRegIndex<32>; +def sub_hi : SubRegIndex<32, 32>; luismarques wrote: > jrtc27 wrote: > > This assumes RV32, and is not clear it applies to register pairs >

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

luismarques added a comment. This patch is nearly there! Just address the remaining review comments and it LGTM. BTW, please mark all addressed inline comments as done. I think a few were missed, and it's helpful for a large patch like this. Comment at:

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:599 + Sched<[]>; +def SMBB32 : RVPBinary<0b100, 0b010, "smbb32">, + Sched<[]>; It looks like the 0.9.3 spec lists this as an alias of

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Any comments? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:950 + assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid register"); + if ((Reg - RISCV::X0) % 2 || Reg == RISCV::X0) +return false; I think this can

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Any comments? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org