[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-22 Thread David Spickett via Phabricator via cfe-commits 
DavidSpickett added inline comments.



Comment at: clang/test/CodeGen/aarch64-neon-range-checks.c:31
   vsm3tt2bq_u32(a, b, c, 0);
+
+void test_range_check_xar(uint64x2_t a, uint64x2_t b) {

I added a "}" here. Please run ninja check-clang and/or check-llvm before you 
update patches.


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[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-22 Thread David Spickett via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2c25efcbd322: [AArch64] Adding SHA3 Intrinsics support 
(authored by rsanthir.quic, committed by DavidSpickett).

Changed prior to commit:
  https://reviews.llvm.org/D96381?vs=324711=325416#toc

Repository:
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Files:
  clang/include/clang/Basic/arm_neon.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-range-checks.c
  clang/test/CodeGen/aarch64-neon-sha3.c
  clang/utils/TableGen/NeonEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/neon-sha3.ll

Index: llvm/test/CodeGen/AArch64/neon-sha3.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/neon-sha3.ll
@@ -0,0 +1,246 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc %s -mtriple=aarch64 -mattr=+v8.3a,+sha3 -o - | FileCheck %s
+
+define <2 x i64> @test_vsha512h(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512h:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512h q0, q1, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512h.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512h(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512h.i
+}
+
+define <2 x i64> @test_vsha512h2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512h2:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512h2 q0, q1, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512h2.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512h2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512h2.i
+}
+
+define <2 x i64> @test_vsha512su0(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vsha512su0:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512su0 v0.2d, v1.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512su0.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512su0(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %vsha512su0.i
+}
+
+define <2 x i64> @test_vsha512su1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512su1:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512su1 v0.2d, v1.2d, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512su1.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512su1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512su1.i
+}
+
+define <2 x i64> @test_vrax1(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vrax1:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:rax1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:ret
+entry:
+  %vrax1.i = tail call <2 x i64> @llvm.aarch64.crypto.rax1(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %vrax1.i
+}
+
+define <2 x i64> @test_vxar(<2 x i64> %a,  <2 x i64> %b) {
+; CHECK-LABEL: test_vxar:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:xar v0.2d, v0.2d, v1.2d, #1
+; CHECK-NEXT:ret
+entry:
+  %vxar.i = tail call  <2 x i64> @llvm.aarch64.crypto.xar(<2 x i64> %a, <2 x i64> %b, i64 1)
+  ret <2 x i64> %vxar.i
+}
+
+define <16 x i8> @test_bcax_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_bcax_8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:bcax v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %vbcax_8.i = tail call <16 x i8> @llvm.aarch64.crypto.bcaxu.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %vbcax_8.i
+}
+
+define <16 x i8> @test_eor3_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_eor3_8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:eor3 v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %veor3_8.i = tail call <16 x i8> @llvm.aarch64.crypto.eor3u.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %veor3_8.i
+}
+
+define <16 x i8> @test_bcax_s8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_bcax_s8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:bcax v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %vbcax_8.i = tail call <16 x i8> @llvm.aarch64.crypto.bcaxs.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %vbcax_8.i
+}
+
+define <16 x i8> @test_eor3_s8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_eor3_s8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:eor3 v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %veor3_8.i = tail call <16 x i8> @llvm.aarch64.crypto.eor3s.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %veor3_8.i
+}
+
+define <8 x i16> @test_bcax_16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_bcax_16:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:bcax v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %vbcax_16.i = tail

[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-19 Thread Ryan Santhirarajan via Phabricator via cfe-commits 
rsanthir.quic added a comment.

Thank you for reviewing this @DavidSpickett ! If you get a chance could you 
commit this for me? I do not have commit access yet.


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[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-19 Thread David Spickett via Phabricator via cfe-commits 
DavidSpickett accepted this revision.
DavidSpickett added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-18 Thread Ryan Santhirarajan via Phabricator via cfe-commits 
rsanthir.quic added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:928
+
+class SHA512H_pattern
+  : Pat<(v2i64 (OpNode (v2i64 V128:$Vd), (v2i64 V128:$Vn), (v2i64 V128:$Vm))),

DavidSpickett wrote:
> This is unused.
a good catch thank you!


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[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-18 Thread Ryan Santhirarajan via Phabricator via cfe-commits 
rsanthir.quic updated this revision to Diff 324711.
rsanthir.quic marked 3 inline comments as done.
rsanthir.quic added a comment.

Minor corrections and removed unused code, also added complete testing


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Files:
  clang/include/clang/Basic/arm_neon.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-range-checks.c
  clang/test/CodeGen/aarch64-neon-sha3.c
  clang/utils/TableGen/NeonEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/neon-sha3.ll

Index: llvm/test/CodeGen/AArch64/neon-sha3.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/neon-sha3.ll
@@ -0,0 +1,246 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc %s -mtriple=aarch64 -mattr=+v8.3a,+sha3 -o - | FileCheck %s
+
+define <2 x i64> @test_vsha512h(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512h:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512h q0, q1, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512h.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512h(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512h.i
+}
+
+define <2 x i64> @test_vsha512h2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512h2:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512h2 q0, q1, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512h2.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512h2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512h2.i
+}
+
+define <2 x i64> @test_vsha512su0(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vsha512su0:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512su0 v0.2d, v1.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512su0.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512su0(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %vsha512su0.i
+}
+
+define <2 x i64> @test_vsha512su1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512su1:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512su1 v0.2d, v1.2d, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512su1.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512su1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512su1.i
+}
+
+define <2 x i64> @test_vrax1(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vrax1:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:rax1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:ret
+entry:
+  %vrax1.i = tail call <2 x i64> @llvm.aarch64.crypto.rax1(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %vrax1.i
+}
+
+define <2 x i64> @test_vxar(<2 x i64> %a,  <2 x i64> %b) {
+; CHECK-LABEL: test_vxar:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:xar v0.2d, v0.2d, v1.2d, #1
+; CHECK-NEXT:ret
+entry:
+  %vxar.i = tail call  <2 x i64> @llvm.aarch64.crypto.xar(<2 x i64> %a, <2 x i64> %b, i64 1)
+  ret <2 x i64> %vxar.i
+}
+
+define <16 x i8> @test_bcax_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_bcax_8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:bcax v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %vbcax_8.i = tail call <16 x i8> @llvm.aarch64.crypto.bcaxu.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %vbcax_8.i
+}
+
+define <16 x i8> @test_eor3_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_eor3_8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:eor3 v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %veor3_8.i = tail call <16 x i8> @llvm.aarch64.crypto.eor3u.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %veor3_8.i
+}
+
+define <16 x i8> @test_bcax_s8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_bcax_s8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:bcax v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %vbcax_8.i = tail call <16 x i8> @llvm.aarch64.crypto.bcaxs.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %vbcax_8.i
+}
+
+define <16 x i8> @test_eor3_s8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_eor3_s8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:eor3 v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %veor3_8.i = tail call <16 x i8> @llvm.aarch64.crypto.eor3s.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %veor3_8.i
+}
+
+define <8 x i16> @test_bcax_16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_bcax_16:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:bcax v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %vbcax_16.i = tail call <8 x i16> @llvm.aarch64.crypto.bcaxu.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c)
+  ret <8 x i16> %vbcax_16.i
+}

[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-18 Thread David Spickett via Phabricator via cfe-commits 
DavidSpickett added a comment.

The approach for xar looks fine to me, matches how we handled vcvt_n_* 
(https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vcvt_n_).




Comment at: clang/include/clang/Basic/arm_neon.td:1139
+def BCAX : SInst<"vbcax", "", "QUcQUsQUiQUlQsQcQiQl">;
+def EOR3 : SInst<"veor3", "", "QUcQUsQUiQUlQsQcQiQl">;
+def RAX1 : SInst<"vrax1", "...", "QUl">;

Put the second set in c-s-i-l order like the first.



Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:928
+
+class SHA512H_pattern
+  : Pat<(v2i64 (OpNode (v2i64 V128:$Vd), (v2i64 V128:$Vn), (v2i64 V128:$Vm))),

This is unused.



Comment at: llvm/test/CodeGen/AArch64/neon-sha3.ll:105
+declare <4 x i32> @llvm.aarch64.crypto.eor3s.v4i32(<4 x i32>, <4 x i32>, <4 x 
i32>)
+declare <2 x i64> @llvm.aarch64.crypto.eor3s.v2i64(<2 x i64>, <2 x i64>, <2 x 
i64>)
+

I'm not sure you need to declare variants you aren't using but in any case you 
should test the missing ones e.g. crypto.eor3u.v8i16.
Maybe there's an argument that it isn't very useful to test them all like this 
but the other files follow this pattern so might as well.


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[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-17 Thread Ryan Santhirarajan via Phabricator via cfe-commits 
rsanthir.quic updated this revision to Diff 324347.
rsanthir.quic added a comment.

Removed extra whitespace


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Files:
  clang/include/clang/Basic/arm_neon.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-range-checks.c
  clang/test/CodeGen/aarch64-neon-sha3.c
  clang/utils/TableGen/NeonEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/neon-sha3.ll

Index: llvm/test/CodeGen/AArch64/neon-sha3.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/neon-sha3.ll
@@ -0,0 +1,106 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc %s -mtriple=aarch64 -mattr=+v8.3a,+sha3 -o - | FileCheck %s
+
+define <2 x i64> @test_vsha512h(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512h:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512h q0, q1, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512h.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512h(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512h.i
+}
+
+define <2 x i64> @test_vsha512h2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512h2:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512h2 q0, q1, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512h2.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512h2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512h2.i
+}
+
+define <2 x i64> @test_vsha512su0(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vsha512su0:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512su0 v0.2d, v1.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512su0.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512su0(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %vsha512su0.i
+}
+
+define <2 x i64> @test_vsha512su1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512su1:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512su1 v0.2d, v1.2d, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512su1.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512su1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512su1.i
+}
+
+define <2 x i64> @test_vrax1(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vrax1:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:rax1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:ret
+entry:
+  %vrax1.i = tail call <2 x i64> @llvm.aarch64.crypto.rax1(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %vrax1.i
+}
+
+define <2 x i64> @test_vxar(<2 x i64> %a,  <2 x i64> %b) {
+; CHECK-LABEL: test_vxar:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:xar v0.2d, v0.2d, v1.2d, #1
+; CHECK-NEXT:ret
+entry:
+  %vxar.i = tail call  <2 x i64> @llvm.aarch64.crypto.xar(<2 x i64> %a, <2 x i64> %b, i64 1)
+  ret <2 x i64> %vxar.i
+}
+
+define <16 x i8> @test_bcax_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_bcax_8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:bcax v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %vbcax_8.i = tail call <16 x i8> @llvm.aarch64.crypto.bcaxu.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %vbcax_8.i
+}
+
+define <16 x i8> @test_eor3_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_eor3_8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:eor3 v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %veor3_8.i = tail call <16 x i8> @llvm.aarch64.crypto.eor3u.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %veor3_8.i
+}
+
+declare <2 x i64> @llvm.aarch64.crypto.sha512h(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.sha512h2(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.sha512su0(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.sha512su1(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.rax1(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.xar(<2 x i64>, <2 x i64>, i64 immarg)
+declare <16 x i8> @llvm.aarch64.crypto.bcaxu.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.aarch64.crypto.bcaxu.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.aarch64.crypto.bcaxu.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.aarch64.crypto.bcaxu.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <16 x i8> @llvm.aarch64.crypto.bcaxs.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.aarch64.crypto.bcaxs.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.aarch64.crypto.bcaxs.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.aarch64.crypto.bcaxs.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <16 x i8> @llvm.aarch64.crypto.eor3u.v16i8(<16 x

[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-17 Thread David Spickett via Phabricator via cfe-commits 
DavidSpickett added a comment.

One nit for now, I'll take a proper look tomorrow. Thanks for your work on 
these!




Comment at: clang/test/CodeGen/aarch64-neon-sha3.c:26
+void test_vsha512su0(uint64x2_t w0_1, uint64x2_t w2_) {
+
+  uint64x2_t result = vsha512su0q_u64(w0_1, w2_);

Nit: remove empty lines in this and the following


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[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-16 Thread Ana Pazos via Phabricator via cfe-commits 
apazos added a comment.

This looks like a straightforward implementation. The only caveat is that the 
XAR immediate does not represent a lane, and hence the need for a custom 
immediate range check. Looks sensible to me.
@labrinea   and others at ARM, do have any other comment before this is merged?


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[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-10 Thread Ryan Santhirarajan via Phabricator via cfe-commits 
rsanthir.quic updated this revision to Diff 322713.
rsanthir.quic added a comment.

alphabetized check in NeonEmitter


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Files:
  clang/include/clang/Basic/arm_neon.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-range-checks.c
  clang/test/CodeGen/aarch64-neon-sha3.c
  clang/utils/TableGen/NeonEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/neon-sha3.ll

Index: llvm/test/CodeGen/AArch64/neon-sha3.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/neon-sha3.ll
@@ -0,0 +1,105 @@
+; RUN: llc %s -mtriple=aarch64 -mattr=+v8.3a,+sha3 -o - | FileCheck %s
+
+define <2 x i64> @test_vsha512h(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512h:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512h q0, q1, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512h.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512h(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512h.i
+}
+
+define <2 x i64> @test_vsha512h2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512h2:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512h2 q0, q1, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512h2.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512h2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512h2.i
+}
+
+define <2 x i64> @test_vsha512su0(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vsha512su0:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512su0 v0.2d, v1.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512su0.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512su0(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %vsha512su0.i
+}
+
+define <2 x i64> @test_vsha512su1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512su1:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512su1 v0.2d, v1.2d, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512su1.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512su1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512su1.i
+}
+
+define <2 x i64> @test_vrax1(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vrax1:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:rax1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:ret
+entry:
+  %vrax1.i = tail call <2 x i64> @llvm.aarch64.crypto.rax1(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %vrax1.i
+}
+
+define <2 x i64> @test_vxar(<2 x i64> %a,  <2 x i64> %b) {
+; CHECK-LABEL: test_vxar:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:xar v0.2d, v0.2d, v1.2d, #1
+; CHECK-NEXT:ret
+entry:
+  %vxar.i = tail call  <2 x i64> @llvm.aarch64.crypto.xar(<2 x i64> %a, <2 x i64> %b, i64 1)
+  ret <2 x i64> %vxar.i
+}
+
+define <16 x i8> @test_bcax_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_bcax_8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:bcax v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %vbcax_8.i = tail call <16 x i8> @llvm.aarch64.crypto.bcaxu.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %vbcax_8.i
+}
+
+define <16 x i8> @test_eor3_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_eor3_8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:eor3 v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %veor3_8.i = tail call <16 x i8> @llvm.aarch64.crypto.eor3u.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %veor3_8.i
+}
+
+declare <2 x i64> @llvm.aarch64.crypto.sha512h(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.sha512h2(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.sha512su0(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.sha512su1(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.rax1(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.xar(<2 x i64>, <2 x i64>, i64 immarg)
+declare <16 x i8> @llvm.aarch64.crypto.bcaxu.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.aarch64.crypto.bcaxu.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.aarch64.crypto.bcaxu.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.aarch64.crypto.bcaxu.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <16 x i8> @llvm.aarch64.crypto.bcaxs.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.aarch64.crypto.bcaxs.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.aarch64.crypto.bcaxs.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.aarch64.crypto.bcaxs.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <16 x i8> @llvm.aarch64.crypto.eor3u.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <8 x i16>

[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-10 Thread Ana Pazos via Phabricator via cfe-commits 
apazos added inline comments.



Comment at: clang/utils/TableGen/NeonEmitter.cpp:2118
 Record *R = Def->getRecord();
-if (R->getValueAsBit("isVCVT_N")) {
+if (R->getValueAsBit("isVXAR")) {
+  //VXAR takes an immediate in the range [0, 63]

Consider alphabetizing the check. move isVXAR check after isVCT_N


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[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-09 Thread Ryan Santhirarajan via Phabricator via cfe-commits 
rsanthir.quic added a comment.

This is the second of three patches to address the following:
https://bugs.llvm.org/show_bug.cgi?id=47828


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[PATCH] D96381: [AArch64] Adding SHA3 Intrinsics support

2021-02-09 Thread Ryan Santhirarajan via Phabricator via cfe-commits 
rsanthir.quic created this revision.
rsanthir.quic added reviewers: apazos, t.p.northover, labrinea, pbarrio.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
rsanthir.quic requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

  This patch adds the following SHA3 Intrinsics:
  vsha512hq_u64,
  vsha512h2q_u64,
  vsha512su0q_u64,
  vsha512su1q_u64
  veor3q_u8
  veor3q_u16
  veor3q_u32
  veor3q_u64
  veor3q_s8
  veor3q_s16
  veor3q_s32
  veor3q_s64
  vrax1q_u64
  vxarq_u64
  vbcaxq_u8
  vbcaxq_u16
  vbcaxq_u32
  vbcaxq_u64
  vbcaxq_s8
  vbcaxq_s16
  vbcaxq_s32
  vbcaxq_s64
  
  Note need to include +sha3 and +crypto when building from the front-end


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96381

Files:
  clang/include/clang/Basic/arm_neon.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-range-checks.c
  clang/test/CodeGen/aarch64-neon-sha3.c
  clang/utils/TableGen/NeonEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/neon-sha3.ll

Index: llvm/test/CodeGen/AArch64/neon-sha3.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/neon-sha3.ll
@@ -0,0 +1,105 @@
+; RUN: llc %s -mtriple=aarch64 -mattr=+v8.3a,+sha3 -o - | FileCheck %s
+
+define <2 x i64> @test_vsha512h(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512h:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512h q0, q1, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512h.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512h(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512h.i
+}
+
+define <2 x i64> @test_vsha512h2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512h2:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512h2 q0, q1, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512h2.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512h2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512h2.i
+}
+
+define <2 x i64> @test_vsha512su0(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vsha512su0:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512su0 v0.2d, v1.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512su0.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512su0(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %vsha512su0.i
+}
+
+define <2 x i64> @test_vsha512su1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vsha512su1:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:sha512su1 v0.2d, v1.2d, v2.2d
+; CHECK-NEXT:ret
+entry:
+  %vsha512su1.i = tail call <2 x i64> @llvm.aarch64.crypto.sha512su1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+  ret <2 x i64> %vsha512su1.i
+}
+
+define <2 x i64> @test_vrax1(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vrax1:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:rax1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:ret
+entry:
+  %vrax1.i = tail call <2 x i64> @llvm.aarch64.crypto.rax1(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %vrax1.i
+}
+
+define <2 x i64> @test_vxar(<2 x i64> %a,  <2 x i64> %b) {
+; CHECK-LABEL: test_vxar:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:xar v0.2d, v0.2d, v1.2d, #1
+; CHECK-NEXT:ret
+entry:
+  %vxar.i = tail call  <2 x i64> @llvm.aarch64.crypto.xar(<2 x i64> %a, <2 x i64> %b, i64 1)
+  ret <2 x i64> %vxar.i
+}
+
+define <16 x i8> @test_bcax_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_bcax_8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:bcax v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %vbcax_8.i = tail call <16 x i8> @llvm.aarch64.crypto.bcaxu.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %vbcax_8.i
+}
+
+define <16 x i8> @test_eor3_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_eor3_8:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:eor3 v0.16b, v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:ret
+entry:
+  %veor3_8.i = tail call <16 x i8> @llvm.aarch64.crypto.eor3u.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+  ret <16 x i8> %veor3_8.i
+}
+
+declare <2 x i64> @llvm.aarch64.crypto.sha512h(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.sha512h2(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.sha512su0(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.sha512su1(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.rax1(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.aarch64.crypto.xar(<2 x i64>, <2 x i64>, i64 immarg)
+declare <16 x i8> @llvm.aarch64.crypto.bcaxu.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <8 x i16>