subject:"\[PATCH\] D97125\: Stop traping on sNaN in __builtin

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-03-15 Thread Thomas Preud'homme via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf60b35340fd7: Stop traping on sNaN in __builtin_isinf 
(authored by thopre).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97125/new/

https://reviews.llvm.org/D97125

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/X86/strictfp_builtins.c
  clang/test/CodeGen/aarch64-strictfp-builtins.c
  clang/test/CodeGen/builtin_float_strictfp.c
  clang/test/CodeGen/strictfp_builtins.c

Index: clang/test/CodeGen/strictfp_builtins.c
===
--- clang/test/CodeGen/strictfp_builtins.c
+++ clang/test/CodeGen/strictfp_builtins.c
@@ -55,23 +55,114 @@
   return;
 }
 
-// CHECK-LABEL: @test_isinf(
+// CHECK-LABEL: @test_fp16_isinf(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[D_ADDR:%.*]] = alloca double, align 8
-// CHECK-NEXT:store double [[D:%.*]], double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP1:%.*]] = call double @llvm.fabs.f64(double [[TMP0]]) [[ATTR5]]
-// CHECK-NEXT:[[CMPINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double 0x7FF0, metadata !"oeq", metadata !"fpexcept.strict") [[ATTR4]]
-// CHECK-NEXT:[[TMP2:%.*]] = zext i1 [[CMPINF]] to i32
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.2, i64 0, i64 0), i32 [[TMP2]]) [[ATTR4]]
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca half, align 2
+// CHECK-NEXT:store half [[H:%.*]], half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast half [[TMP0]] to i16
+// CHECK-NEXT:[[SHL1:%.*]] = shl i16 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i16 [[SHL1]], -2048
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:2]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
-void test_isinf(double d) {
+void test_fp16_isinf(__fp16 h) {
+  P(isinf, (h));
+
+  return;
+}
+
+// CHECK-LABEL: @test_float_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:store float [[F:%.*]], float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast float [[TMP0]] to i32
+// CHECK-NEXT:[[SHL1:%.*]] = shl i32 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i32 [[SHL1]], -16777216
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_float_isinf(float f) {
+  P(isinf, (f));
+
+  return;
+}
+
+// CHECK-LABEL: @test_double_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT:store double [[D:%.*]], double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast double [[TMP0]] to i64
+// CHECK-NEXT:[[SHL1:%.*]] = shl i64 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i64 [[SHL1]], -9007199254740992
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_double_isinf(double d) {
   P(isinf, (d));
 
   return;
 }
 
+// CHECK-LABEL: @test_fp16_isfinite(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca half, align 2
+// CHECK-NEXT:store half [[H:%.*]], half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast half [[TMP0]] to i16
+// CHECK-NEXT:[[SHL1:%.*]] = shl i16 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp ult i16 [[SHL1]], -2048
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_fp16_isfinite(__fp16 h) {
+  P(isfinite, (h));
+
+  return;
+}
+
+// CHECK-LABEL: @test_float_isfinite(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:store float [[F:%.*]], float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast float [[TMP0]] to i32
+// CHECK-NEXT:[[SHL1:%.*]] = shl i32 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp ult i32 [[SHL1]], -16777216
+// CHECK-NEXT:[[RES:%.*]] =

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-03-15 Thread Thomas Preud'homme via Phabricator via cfe-commits

thopre added a comment.

In D97125#2603832 , @thopre wrote:

> Requesting review since the logic has changed. This time I've also tested 
> isfinite against glibc's result. All looks good.

Ping?


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[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-03-04 Thread Thomas Preud'homme via Phabricator via cfe-commits

thopre requested review of this revision.
thopre added a comment.

Requesting review since the logic has changed. This time I've also tested 
isfinite against glibc's result. All looks good.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97125/new/

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[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-03-04 Thread Thomas Preud'homme via Phabricator via cfe-commits

thopre updated this revision to Diff 328171.
thopre added a comment.

Add isfinite testcases


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97125/new/

https://reviews.llvm.org/D97125

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/X86/strictfp_builtins.c
  clang/test/CodeGen/aarch64-strictfp-builtins.c
  clang/test/CodeGen/builtin_float_strictfp.c
  clang/test/CodeGen/strictfp_builtins.c

Index: clang/test/CodeGen/strictfp_builtins.c
===
--- clang/test/CodeGen/strictfp_builtins.c
+++ clang/test/CodeGen/strictfp_builtins.c
@@ -55,23 +55,114 @@
   return;
 }
 
-// CHECK-LABEL: @test_isinf(
+// CHECK-LABEL: @test_fp16_isinf(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[D_ADDR:%.*]] = alloca double, align 8
-// CHECK-NEXT:store double [[D:%.*]], double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP1:%.*]] = call double @llvm.fabs.f64(double [[TMP0]]) [[ATTR5]]
-// CHECK-NEXT:[[CMPINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double 0x7FF0, metadata !"oeq", metadata !"fpexcept.strict") [[ATTR4]]
-// CHECK-NEXT:[[TMP2:%.*]] = zext i1 [[CMPINF]] to i32
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.2, i64 0, i64 0), i32 [[TMP2]]) [[ATTR4]]
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca half, align 2
+// CHECK-NEXT:store half [[H:%.*]], half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast half [[TMP0]] to i16
+// CHECK-NEXT:[[SHL1:%.*]] = shl i16 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i16 [[SHL1]], -2048
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:2]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
-void test_isinf(double d) {
+void test_fp16_isinf(__fp16 h) {
+  P(isinf, (h));
+
+  return;
+}
+
+// CHECK-LABEL: @test_float_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:store float [[F:%.*]], float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast float [[TMP0]] to i32
+// CHECK-NEXT:[[SHL1:%.*]] = shl i32 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i32 [[SHL1]], -16777216
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_float_isinf(float f) {
+  P(isinf, (f));
+
+  return;
+}
+
+// CHECK-LABEL: @test_double_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT:store double [[D:%.*]], double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast double [[TMP0]] to i64
+// CHECK-NEXT:[[SHL1:%.*]] = shl i64 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i64 [[SHL1]], -9007199254740992
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_double_isinf(double d) {
   P(isinf, (d));
 
   return;
 }
 
+// CHECK-LABEL: @test_fp16_isfinite(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca half, align 2
+// CHECK-NEXT:store half [[H:%.*]], half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast half [[TMP0]] to i16
+// CHECK-NEXT:[[SHL1:%.*]] = shl i16 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp ult i16 [[SHL1]], -2048
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_fp16_isfinite(__fp16 h) {
+  P(isfinite, (h));
+
+  return;
+}
+
+// CHECK-LABEL: @test_float_isfinite(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:store float [[F:%.*]], float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast float [[TMP0]] to i32
+// CHECK-NEXT:[[SHL1:%.*]] = shl i32 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp ult i32 [[SHL1]], -16777216
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-03-04 Thread Thomas Preud'homme via Phabricator via cfe-commits

thopre updated this revision to Diff 328170.
thopre added a comment.

Fix isfinite logic


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97125/new/

https://reviews.llvm.org/D97125

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/X86/strictfp_builtins.c
  clang/test/CodeGen/aarch64-strictfp-builtins.c
  clang/test/CodeGen/builtin_float_strictfp.c
  clang/test/CodeGen/strictfp_builtins.c

Index: clang/test/CodeGen/strictfp_builtins.c
===
--- clang/test/CodeGen/strictfp_builtins.c
+++ clang/test/CodeGen/strictfp_builtins.c
@@ -55,18 +55,55 @@
   return;
 }
 
-// CHECK-LABEL: @test_isinf(
+// CHECK-LABEL: @test_fp16_isinf(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[D_ADDR:%.*]] = alloca double, align 8
-// CHECK-NEXT:store double [[D:%.*]], double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP1:%.*]] = call double @llvm.fabs.f64(double [[TMP0]]) [[ATTR5]]
-// CHECK-NEXT:[[CMPINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double 0x7FF0, metadata !"oeq", metadata !"fpexcept.strict") [[ATTR4]]
-// CHECK-NEXT:[[TMP2:%.*]] = zext i1 [[CMPINF]] to i32
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.2, i64 0, i64 0), i32 [[TMP2]]) [[ATTR4]]
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca half, align 2
+// CHECK-NEXT:store half [[H:%.*]], half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast half [[TMP0]] to i16
+// CHECK-NEXT:[[SHL1:%.*]] = shl i16 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i16 [[SHL1]], -2048
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:2]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_fp16_isinf(__fp16 h) {
+  P(isinf, (h));
+
+  return;
+}
+
+// CHECK-LABEL: @test_float_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:store float [[F:%.*]], float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast float [[TMP0]] to i32
+// CHECK-NEXT:[[SHL1:%.*]] = shl i32 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i32 [[SHL1]], -16777216
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_float_isinf(float f) {
+  P(isinf, (f));
+
+  return;
+}
+
+// CHECK-LABEL: @test_double_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT:store double [[D:%.*]], double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast double [[TMP0]] to i64
+// CHECK-NEXT:[[SHL1:%.*]] = shl i64 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i64 [[SHL1]], -9007199254740992
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
-void test_isinf(double d) {
+void test_double_isinf(double d) {
   P(isinf, (d));
 
   return;
@@ -83,7 +120,7 @@
 // CHECK-NEXT:[[TMP3:%.*]] = icmp slt i64 [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = select i1 [[TMP3]], i32 -1, i32 1
 // CHECK-NEXT:[[TMP5:%.*]] = select i1 [[ISINF]], i32 [[TMP4]], i32 0
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.3, i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]]
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
 void test_isinf_sign(double d) {
@@ -102,7 +139,7 @@
 // CHECK-NEXT:[[TMP1:%.*]] = sub i16 [[#%u,0x7C00]], [[ABS]]
 // CHECK-NEXT:[[ISNAN:%.*]] = lshr i16 [[TMP1]], 15
 // CHECK-NEXT:[[RES:%.*]] = zext i16 [[ISNAN]] to i32
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.4, i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
 void test_fp16_isnan(__fp16 h) {
@@ -120,7 +157,7 @@
 // CHECK-NEXT:[[ABS:%.*]] = and i32 [[BITCAST]], [[#%u,0x7FFF]]
 // CHECK-NEXT:[[TMP1:%.*]] = sub i32 [[#%u,0x7F80]], [[ABS]]
 // CHECK-NEXT:[[ISNAN:%.*]] = lshr i32 [[TMP1]], 31
-//

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-03-02 Thread Thomas Preud'homme via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1b6eb56aa0ea: Stop traping on sNaN in __builtin_isinf 
(authored by thopre).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97125/new/

https://reviews.llvm.org/D97125

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/X86/strictfp_builtins.c
  clang/test/CodeGen/aarch64-strictfp-builtins.c
  clang/test/CodeGen/builtin_float_strictfp.c
  clang/test/CodeGen/strictfp_builtins.c

Index: clang/test/CodeGen/strictfp_builtins.c
===
--- clang/test/CodeGen/strictfp_builtins.c
+++ clang/test/CodeGen/strictfp_builtins.c
@@ -1,5 +1,5 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 %s -emit-llvm -ffp-exception-behavior=maytrap -o - -triple x86_64-unknown-unknown | FileCheck %s
+// RUN: %clang_cc1 %s -emit-llvm -ffp-exception-behavior=maytrap -fallow-half-arguments-and-returns -o - -triple x86_64-unknown-unknown | FileCheck %s
 
 // Test that the constrained intrinsics are picking up the exception
 // metadata from the AST instead of the global default from the command line.
@@ -55,18 +55,55 @@
   return;
 }
 
-// CHECK-LABEL: @test_isinf(
+// CHECK-LABEL: @test_fp16_isinf(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[D_ADDR:%.*]] = alloca double, align 8
-// CHECK-NEXT:store double [[D:%.*]], double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP1:%.*]] = call double @llvm.fabs.f64(double [[TMP0]]) [[ATTR5]]
-// CHECK-NEXT:[[CMPINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double 0x7FF0, metadata !"oeq", metadata !"fpexcept.strict") [[ATTR4]]
-// CHECK-NEXT:[[TMP2:%.*]] = zext i1 [[CMPINF]] to i32
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.2, i64 0, i64 0), i32 [[TMP2]]) [[ATTR4]]
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca half, align 2
+// CHECK-NEXT:store half [[H:%.*]], half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast half [[TMP0]] to i16
+// CHECK-NEXT:[[SHL1:%.*]] = shl i16 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i16 [[SHL1]], -2048
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:2]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_fp16_isinf(__fp16 h) {
+  P(isinf, (h));
+
+  return;
+}
+
+// CHECK-LABEL: @test_float_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:store float [[F:%.*]], float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast float [[TMP0]] to i32
+// CHECK-NEXT:[[SHL1:%.*]] = shl i32 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i32 [[SHL1]], -16777216
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_float_isinf(float f) {
+  P(isinf, (f));
+
+  return;
+}
+
+// CHECK-LABEL: @test_double_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT:store double [[D:%.*]], double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast double [[TMP0]] to i64
+// CHECK-NEXT:[[SHL1:%.*]] = shl i64 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i64 [[SHL1]], -9007199254740992
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
-void test_isinf(double d) {
+void test_double_isinf(double d) {
   P(isinf, (d));
 
   return;
@@ -83,7 +120,7 @@
 // CHECK-NEXT:[[TMP3:%.*]] = icmp slt i64 [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = select i1 [[TMP3]], i32 -1, i32 1
 // CHECK-NEXT:[[TMP5:%.*]] = select i1 [[ISINF]], i32 [[TMP4]], i32 0
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.3, i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]]
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
 void test_isinf_sign(double d) {
@@ -101,7 +138,7 @@
 // CHECK-NEXT:[[ABS:%.*]] = and i32 [[BITCAST]], [[#%u,0x7FFF]]
 // CHECK-NEXT:

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-03-02 Thread Thomas Preud'homme via Phabricator via cfe-commits

thopre added a comment.

Ping?




Comment at: clang/test/CodeGen/builtin_float_strictfp.c:21
+  // NOFP16-NEXT:  [[IHALF:%.*]]  = load i16, i16* [[LDADDR]], align 2
+  // NOFP16-NEXT:  [[CONV:%.*]]   = call float @llvm.convert.from.fp16.f32(i16 
[[IHALF]])
+  // NOFP16-NEXT:  [[IFLOAT:%.*]] = bitcast float [[CONV]] to i32

thopre wrote:
> Am I right to think that clang should not use llvm.convert here since it's a 
> constrained operation? Any idea why that happens?
Nvm, that's for when fp16 is not supported. I'm guessing this ought to not 
throw an exception.


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[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-02-23 Thread Thomas Preud'homme via Phabricator via cfe-commits

thopre added inline comments.



Comment at: clang/test/CodeGen/builtin_float_strictfp.c:21
+  // NOFP16-NEXT:  [[IHALF:%.*]]  = load i16, i16* [[LDADDR]], align 2
+  // NOFP16-NEXT:  [[CONV:%.*]]   = call float @llvm.convert.from.fp16.f32(i16 
[[IHALF]])
+  // NOFP16-NEXT:  [[IFLOAT:%.*]] = bitcast float [[CONV]] to i32

Am I right to think that clang should not use llvm.convert here since it's a 
constrained operation? Any idea why that happens?


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[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-02-23 Thread Thomas Preud'homme via Phabricator via cfe-commits

thopre updated this revision to Diff 325718.
thopre added a comment.

- Add half testcase
- Fixup existing testcase


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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/X86/strictfp_builtins.c
  clang/test/CodeGen/aarch64-strictfp-builtins.c
  clang/test/CodeGen/builtin_float_strictfp.c
  clang/test/CodeGen/strictfp_builtins.c

Index: clang/test/CodeGen/strictfp_builtins.c
===
--- clang/test/CodeGen/strictfp_builtins.c
+++ clang/test/CodeGen/strictfp_builtins.c
@@ -1,5 +1,5 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 %s -emit-llvm -ffp-exception-behavior=maytrap -o - -triple x86_64-unknown-unknown | FileCheck %s
+// RUN: %clang_cc1 %s -emit-llvm -ffp-exception-behavior=maytrap -fallow-half-arguments-and-returns -o - -triple x86_64-unknown-unknown | FileCheck %s
 
 // Test that the constrained intrinsics are picking up the exception
 // metadata from the AST instead of the global default from the command line.
@@ -55,18 +55,55 @@
   return;
 }
 
-// CHECK-LABEL: @test_isinf(
+// CHECK-LABEL: @test_fp16_isinf(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[D_ADDR:%.*]] = alloca double, align 8
-// CHECK-NEXT:store double [[D:%.*]], double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP1:%.*]] = call double @llvm.fabs.f64(double [[TMP0]]) [[ATTR5]]
-// CHECK-NEXT:[[CMPINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double 0x7FF0, metadata !"oeq", metadata !"fpexcept.strict") [[ATTR4]]
-// CHECK-NEXT:[[TMP2:%.*]] = zext i1 [[CMPINF]] to i32
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.2, i64 0, i64 0), i32 [[TMP2]]) [[ATTR4]]
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca half, align 2
+// CHECK-NEXT:store half [[H:%.*]], half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, half* [[LD_ADDR]], align 2
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast half [[TMP0]] to i16
+// CHECK-NEXT:[[SHL1:%.*]] = shl i16 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i16 [[SHL1]], -2048
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:2]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_fp16_isinf(__fp16 h) {
+  P(isinf, (h));
+
+  return;
+}
+
+// CHECK-LABEL: @test_float_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:store float [[F:%.*]], float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast float [[TMP0]] to i32
+// CHECK-NEXT:[[SHL1:%.*]] = shl i32 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i32 [[SHL1]], -16777216
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_float_isinf(float f) {
+  P(isinf, (f));
+
+  return;
+}
+
+// CHECK-LABEL: @test_double_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT:store double [[D:%.*]], double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast double [[TMP0]] to i64
+// CHECK-NEXT:[[SHL1:%.*]] = shl i64 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i64 [[SHL1]], -9007199254740992
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
-void test_isinf(double d) {
+void test_double_isinf(double d) {
   P(isinf, (d));
 
   return;
@@ -83,7 +120,7 @@
 // CHECK-NEXT:[[TMP3:%.*]] = icmp slt i64 [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = select i1 [[TMP3]], i32 -1, i32 1
 // CHECK-NEXT:[[TMP5:%.*]] = select i1 [[ISINF]], i32 [[TMP4]], i32 0
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.3, i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]]
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
 void test_isinf_sign(double d) {
@@ -101,7 +138,7 @@
 // CHECK-NEXT:[[ABS:%.*]] = and i32 [[BITCAST]], [[#%u,0x7FFF]]
 // CHECK-NEXT:[[TMP1:%.*]] = sub i32 [[#%u,0x7F80]], [[ABS]]
 // CHECK-NEXT:[[ISNAN:%.*]] = lshr i32 [[TMP1]], 31
-//

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-02-22 Thread Jonas Paulsson via Phabricator via cfe-commits

jonpa added a comment.

In D97125#2578853 , @kpn wrote:

> System/Z's TEST DATA CLASS instruction covers most (all?) of the possible FP 
> value states. You might want to subscribe, or add as a reviewer, jonpa just 
> to make sure everyone stays in sync.

Thanks for keeping me updated on this - I see that you have already included 
the testFPKind() hook, so I will add these opcodes to SystemZ once this is 
committed...


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[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-02-22 Thread Thomas Preud'homme via Phabricator via cfe-commits

thopre added a comment.

I think we should also add tests for half


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[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-02-22 Thread Kevin P. Neal via Phabricator via cfe-commits

kpn added a comment.

System/Z's TEST DATA CLASS instruction covers most (all?) of the possible FP 
value states. You might want to subscribe, or add as a reviewer, jonpa just to 
make sure everyone stays in sync.


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[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

2021-02-20 Thread Thomas Preud'homme via Phabricator via cfe-commits

thopre created this revision.
thopre added reviewers: kpn, efriedma, mibintc, sepavloff, rjmccall.
Herald added a subscriber: pengfei.
thopre requested review of this revision.
Herald added a project: clang.

__builtin_isinf currently generates a floating-point compare operation
which triggers a trap when faced with a signaling NaN in StrictFP mode.
This commit uses integer operations instead to not generate any trap in
such a case.


Repository:
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https://reviews.llvm.org/D97125

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/X86/strictfp_builtins.c
  clang/test/CodeGen/aarch64-strictfp-builtins.c
  clang/test/CodeGen/strictfp_builtins.c

Index: clang/test/CodeGen/strictfp_builtins.c
===
--- clang/test/CodeGen/strictfp_builtins.c
+++ clang/test/CodeGen/strictfp_builtins.c
@@ -55,18 +55,37 @@
   return;
 }
 
-// CHECK-LABEL: @test_isinf(
+// CHECK-LABEL: @test_float_isinf(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[D_ADDR:%.*]] = alloca double, align 8
-// CHECK-NEXT:store double [[D:%.*]], double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
-// CHECK-NEXT:[[TMP1:%.*]] = call double @llvm.fabs.f64(double [[TMP0]]) [[ATTR5]]
-// CHECK-NEXT:[[CMPINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double 0x7FF0, metadata !"oeq", metadata !"fpexcept.strict") [[ATTR4]]
-// CHECK-NEXT:[[TMP2:%.*]] = zext i1 [[CMPINF]] to i32
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.2, i64 0, i64 0), i32 [[TMP2]]) [[ATTR4]]
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:store float [[F:%.*]], float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* [[LD_ADDR]], align 4
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast float [[TMP0]] to i32
+// CHECK-NEXT:[[SHL1:%.*]] = shl i32 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i32 [[SHL1]], -16777216
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.2, i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void test_float_isinf(float f) {
+  P(isinf, (f));
+
+  return;
+}
+
+// CHECK-LABEL: @test_double_isinf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LD_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT:store double [[D:%.*]], double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[LD_ADDR]], align 8
+// CHECK-NEXT:[[BITCAST:%.*]] = bitcast double [[TMP0]] to i64
+// CHECK-NEXT:[[SHL1:%.*]] = shl i64 [[BITCAST]], 1
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq i64 [[SHL1]], -9007199254740992
+// CHECK-NEXT:[[RES:%.*]] = zext i1 [[CMP]] to i32
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.3, i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
-void test_isinf(double d) {
+void test_double_isinf(double d) {
   P(isinf, (d));
 
   return;
@@ -83,7 +102,7 @@
 // CHECK-NEXT:[[TMP3:%.*]] = icmp slt i64 [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = select i1 [[TMP3]], i32 -1, i32 1
 // CHECK-NEXT:[[TMP5:%.*]] = select i1 [[ISINF]], i32 [[TMP4]], i32 0
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.3, i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]]
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.4, i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
 void test_isinf_sign(double d) {
@@ -101,7 +120,7 @@
 // CHECK-NEXT:[[ABS:%.*]] = and i32 [[BITCAST]], [[#%u,0x7FFF]]
 // CHECK-NEXT:[[TMP1:%.*]] = sub i32 [[#%u,0x7F80]], [[ABS]]
 // CHECK-NEXT:[[ISNAN:%.*]] = lshr i32 [[TMP1]], 31
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.4, i64 0, i64 0), i32 [[ISNAN]]) [[ATTR4]]
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.5, i64 0, i64 0), i32 [[ISNAN]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
 void test_float_isnan(float f) {
@@ -120,7 +139,7 @@
 // CHECK-NEXT:[[TMP1:%.*]] = sub i64 [[#%u,0x7FF0]], [[ABS]]
 // CHECK-NEXT:[[ISNAN:%.*]] = lshr i64 [[TMP1]], 63
 // CHECK-NEXT:[[RES:%.*]] = trunc i64 [[ISNAN]] to i32
-// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.5, i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
+// CHECK-NEXT:call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.6, i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
 // CHECK-NEXT:ret void
 //
 void test_double_isnan(double d) {
@@ -141,7 +160,7 @@
 // CHECK-NEXT:[[AND:%.*]] = and i1 [[ISEQ]], [[ISINF]]
 // CHECK-NEXT:[[AND1:%.*]] = and i1 [[AND]], [[ISNORMAL]]
 // CHECK-NEXT:[[TMP2:%.*]] = zext i1 [[AND1]] to i32
-// CHECK-NEXT:call void @p(i8*

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

[PATCH] D97125: Stop traping on sNaN in __builtin_isinf

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