koute wrote:
As a third-party bystander I just want to say, thank you to everyone involved!
And especially @wangpc-pp, a huge thank you for pushing this through!
https://github.com/llvm/llvm-project/pull/76777
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wangpc-pp wrote:
It's not easy to push this forward and thanks a lot!
I'll merge this soon. If there are some issues (hope not ), follow-up patches
will fix them.
https://github.com/llvm/llvm-project/pull/76777
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https://github.com/nemanjai approved this pull request.
My comments have been addressed, so this LGTM. I'll of course defer to @asb and
@topperc for final approval.
https://github.com/llvm/llvm-project/pull/76777
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@@ -985,9 +1003,10 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction ,
};
for (auto Reg : CSRegs)
- SavedRegs.set(Reg);
+ if (Reg < RISCV::X16 || !Subtarget.isRVE())
nemanjai wrote:
Sounds good. Maybe just a little comment
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/76777
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@@ -386,6 +393,11 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector ,
if (llvm::is_contained(Features, "+experimental"))
HasExperimental = true;
+ if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) {
+Diags.Report(diag::err_invalid_feature_combination)
+
@@ -386,6 +393,11 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector ,
if (llvm::is_contained(Features, "+experimental"))
HasExperimental = true;
+ if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) {
+Diags.Report(diag::err_invalid_feature_combination)
+
@@ -83,13 +88,14 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction
*MF) const {
}
BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction ) const {
+ const RISCVSubtarget = MF.getSubtarget();
wangpc-pp wrote:
This should be a
@@ -17,6 +17,13 @@ def HasStdExtZicsr :
Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
+def FeatureStdExtI
+: SubtargetFeature<"i", "HasStdExtI",
@@ -179,6 +180,11 @@ Assembly Support
Supported
Fully supported by the compiler. This includes everything in Assembly
Support, along with - if relevant - C language intrinsics for the instructions
and pattern matching by the compiler to recognize idiomatic patterns which
@@ -17,6 +17,13 @@ def HasStdExtZicsr :
Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
+def FeatureStdExtI
+: SubtargetFeature<"i", "HasStdExtI",
@@ -83,13 +88,14 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction
*MF) const {
}
BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction ) const {
+ const RISCVSubtarget = MF.getSubtarget();
nemanjai wrote:
Why was this added? Or
https://github.com/nemanjai commented:
It is not my intent to hold up approval of this patch. In addition to the minor
comments I added, I plan to do some local testing but even if the testing
reveals issues, they can be fixed on subsequent commits.
asb wrote:
The RISCVUsage change looks good to me, and it's fantastic that @nemanjai might
be able to help push this forward further.
I think all the review comments were addressed, so I'd be happy to merge if
@topperc is happy his comments were resolved. Though also fine to wait longer
if
koute wrote:
> As for your diffs, it seems that you only handle the
> `__riscv_save/restore_[2|1|0]`, which is incomplete. And the code is not
> different with non-rve cases?
Yes, I mostly copy-pasted the existing code and removed all of the code dealing
with registers not available on
wangpc-pp wrote:
> Side note: shouldn't we also update `compiler-rt/lib/builtins/riscv/{save,
> restore}.S`? E.g. with something like this:
> [...]
> (I don't remember why exactly since I did it a long time ago, but for some
> reason I do have this patch in my LLVM fork, so it probably was
koute wrote:
Side note: shouldn't we also update `compiler-rt/lib/builtins/riscv/{save,
restore}.S`? E.g. with something like this:
```patch
diff --git a/compiler-rt/lib/builtins/riscv/restore.S
b/compiler-rt/lib/builtins/riscv/restore.S
index 73f64a920d66..2e185ecae3f7 100644
---
athei wrote:
> What was the last bit of discussion on the phabricator review? I can no
> longer access it.
It was basically just waiting for final approval. The agreement was that it is
good enough to be merged in as experimental even with unfinalized ABI.
I really hope we can get this in
@@ -109,6 +115,11 @@ BitVector RISCVRegisterInfo::getReservedRegs(const
MachineFunction ) const {
// beginning with 'x0' for instructions that take register pairs.
markSuperRegs(Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0);
+ // There are only 16 GPRs for RVE.
+ if
@@ -285,13 +286,16 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList
,
// 3. Choose a default based on `-mabi=`
//
// ilp32e -> rv32e
+ // lp64e -> rv64e
// ilp32 | ilp32f | ilp32d -> rv32imafdc
// lp64 | lp64f | lp64d -> rv64imafdc
if (const Arg *A =
@@ -0,0 +1,2556 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=ILP32E-FPELIM %s
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e
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