Author: David Blaikie Date: 2021-06-28T22:57:21-07:00 New Revision: e1b8fde1cbfc031d67d9b316f1b4ac3ab9c8801f
URL: https://github.com/llvm/llvm-project/commit/e1b8fde1cbfc031d67d9b316f1b4ac3ab9c8801f DIFF: https://github.com/llvm/llvm-project/commit/e1b8fde1cbfc031d67d9b316f1b4ac3ab9c8801f.diff LOG: Revert "[Clang] Add option to handle behaviour of vector bool/vector pixel." This reverts commit c3fe847f9d90de5a6a76fd1d5f5823ab4719accc. Tests fail in non-asserts builds because they assume named IR, by the looks of it (testing for the "entry" label, for instance). I don't know enough about the update_cc_test_checks.py stuff to know how to manually fix these tests, so reverting for now. Added: Modified: clang/include/clang/Basic/DiagnosticSemaKinds.td clang/include/clang/Basic/LangOptions.def clang/include/clang/Basic/LangOptions.h clang/include/clang/Driver/Options.td clang/lib/Driver/ToolChains/Clang.cpp clang/lib/Sema/SemaExpr.cpp Removed: clang/test/CodeGen/vector-compat-pixel-bool-ternary.c clang/test/CodeGen/vector-compat-pixel-bool.c clang/test/CodeGen/vector-compat-ternary.c clang/test/CodeGen/vector-compat.c ################################################################################ diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 70a22fd2506a..b5b8bc6aa3c5 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -7441,12 +7441,6 @@ def warn_deprecated_volatile_structured_binding : Warning< "volatile qualifier in structured binding declaration is deprecated">, InGroup<DeprecatedVolatile>; -def warn_deprecated_altivec_src_compat : Warning< - "Current handling of vector bool and vector pixel types in this context are " - "deprecated. The default behaviour will soon change to that implied by the " - "'-altivec-compat=xl' option">, - InGroup<DiagGroup<"deprecated-altivec-src-compat">>; - def err_catch_incomplete_ptr : Error< "cannot catch pointer to incomplete type %0">; def err_catch_incomplete_ref : Error< diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index 465bad8d7d11..b6d9160f89a0 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -126,8 +126,6 @@ LANGOPT(WritableStrings , 1, 0, "writable string support") LANGOPT(ConstStrings , 1, 0, "const-qualified string support") ENUM_LANGOPT(LaxVectorConversions, LaxVectorConversionKind, 2, LaxVectorConversionKind::All, "lax vector conversions") -ENUM_LANGOPT(AltivecSrcCompat, AltivecSrcCompatKind, 2, - AltivecSrcCompatKind::Default, "Altivec source compatibility") LANGOPT(ConvergentFunctions, 1, 1, "Assume convergent functions") LANGOPT(AltiVec , 1, 0, "AltiVec-style vector initializers") LANGOPT(ZVector , 1, 0, "System z vector extensions") diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h index d04ce52a550e..d618daf3d23c 100644 --- a/clang/include/clang/Basic/LangOptions.h +++ b/clang/include/clang/Basic/LangOptions.h @@ -244,18 +244,6 @@ class LangOptions : public LangOptionsBase { All, }; - enum class AltivecSrcCompatKind { - // All vector compares produce scalars except vector pixel and vector bool. - // The types vector pixel and vector bool return vector results. - Mixed, - // All vector compares produce vector results as in GCC. - GCC, - // All vector compares produce scalars as in XL. - XL, - // Default clang behaviour. - Default = Mixed, - }; - enum class SignReturnAddressScopeKind { /// No signing for any function. None, diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index f1455f546199..0122afd2eead 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -3823,18 +3823,6 @@ def u : JoinedOrSeparate<["-"], "u">, Group<u_Group>; def v : Flag<["-"], "v">, Flags<[CC1Option, CoreOption]>, HelpText<"Show commands to run and use verbose output">, MarshallingInfoFlag<HeaderSearchOpts<"Verbose">>; -def altivec_src_compat : Joined<["-"], "faltivec-src-compat=">, - Flags<[CC1Option]>, Group<f_Group>, - HelpText<"Source-level compatibility for Altivec vectors (for PowerPC " - "targets). This includes results of vector comparison (scalar for " - "'xl', vector for 'gcc') as well as behavior when initializing with " - "a scalar (splatting for 'xl', element zero only for 'gcc'). For " - "'mixed', the compatibility is as 'gcc' for 'vector bool/vector " - "pixel' and as 'xl' for other types. Current default is 'mixed'.">, - Values<"mixed,gcc,xl">, - NormalizedValuesScope<"LangOptions::AltivecSrcCompatKind">, - NormalizedValues<["Mixed", "GCC", "XL"]>, - MarshallingInfoEnum<LangOpts<"AltivecSrcCompat">, "Mixed">; def verify_debug_info : Flag<["--"], "verify-debug-info">, Flags<[NoXarchOption]>, HelpText<"Verify the binary representation of debug output">; def weak_l : Joined<["-"], "weak-l">, Flags<[LinkerInput]>; diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index c265e1c4e53c..a3f0ec577379 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -5816,7 +5816,6 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, (Args.hasArg(options::OPT_mkernel) && types::isCXX(InputType))) CmdArgs.push_back("-fapple-kext"); - Args.AddLastArg(CmdArgs, options::OPT_altivec_src_compat); Args.AddLastArg(CmdArgs, options::OPT_flax_vector_conversions_EQ); Args.AddLastArg(CmdArgs, options::OPT_fobjc_sender_dependent_dispatch); Args.AddLastArg(CmdArgs, options::OPT_fdiagnostics_print_source_range_info); diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 6031dff67335..728d7b61d4a8 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -12224,30 +12224,11 @@ QualType Sema::CheckVectorCompareOperands(ExprResult &LHS, ExprResult &RHS, QualType LHSType = LHS.get()->getType(); - // Determine the return type of a vector compare. By default clang will return - // a scalar for all vector compares except vector bool and vector pixel. - // With the gcc compiler we will always return a vector type and with the xl - // compiler we will always return a scalar type. This switch allows choosing - // which behavior is prefered. - if (getLangOpts().AltiVec) { - switch (getLangOpts().getAltivecSrcCompat()) { - case LangOptions::AltivecSrcCompatKind::Mixed: - // If AltiVec, the comparison results in a numeric type, i.e. - // bool for C++, int for C - if (vType->castAs<VectorType>()->getVectorKind() == - VectorType::AltiVecVector) - return Context.getLogicalOperationType(); - else - Diag(Loc, diag::warn_deprecated_altivec_src_compat); - break; - case LangOptions::AltivecSrcCompatKind::GCC: - // For GCC we always return the vector type. - break; - case LangOptions::AltivecSrcCompatKind::XL: - return Context.getLogicalOperationType(); - break; - } - } + // If AltiVec, the comparison results in a numeric type, i.e. + // bool for C++, int for C + if (getLangOpts().AltiVec && + vType->castAs<VectorType>()->getVectorKind() == VectorType::AltiVecVector) + return Context.getLogicalOperationType(); // For non-floating point types, check for self-comparisons of the form // x == x, x != x, x < x, etc. These always evaluate to a constant, and diff --git a/clang/test/CodeGen/vector-compat-pixel-bool-ternary.c b/clang/test/CodeGen/vector-compat-pixel-bool-ternary.c deleted file mode 100644 index 20da80960212..000000000000 --- a/clang/test/CodeGen/vector-compat-pixel-bool-ternary.c +++ /dev/null @@ -1,104 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR -// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1| FileCheck %s --check-prefix=ERROR -// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s -// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s -// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s - -// CHECK-LABEL: @bi8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequb.p(i32 2, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(16 * sizeof(char)))) char' (vector of 16 'char' values) where arithmetic or pointer type is required -int bi8(vector bool char a, vector bool char b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @bi16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required -int bi16(vector bool short a, vector bool short b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @bi32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequw.p(i32 2, <4 x i32> [[TMP0]], <4 x i32> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required -int bi32(vector bool int a, vector bool int b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @bi64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x i64>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x i64>, align 16 -// CHECK-NEXT: store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> [[TMP0]], <2 x i64> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(2 * sizeof(long long)))) long long' (vector of 2 'long long' values) where arithmetic or pointer type is required -int bi64(vector bool long long a, vector bool long long b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @VecPixel( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required -int VecPixel(vector pixel a, vector pixel b) { - return a == b ? 3 : 7; -} diff --git a/clang/test/CodeGen/vector-compat-pixel-bool.c b/clang/test/CodeGen/vector-compat-pixel-bool.c deleted file mode 100644 index 292431f5b07f..000000000000 --- a/clang/test/CodeGen/vector-compat-pixel-bool.c +++ /dev/null @@ -1,94 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s -// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR -// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s -// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s - -// CHECK-LABEL: @bi8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8> -// CHECK-NEXT: ret <16 x i8> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector unsigned char bi8(vector bool char a, vector bool char b) { - return a == b; -} - -// CHECK-LABEL: @bi16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector bool short bi16(vector bool short a, vector bool short b) { - return a == b; -} - -// CHECK-LABEL: @bi32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector bool int bi32(vector bool int a, vector bool int b) { - return a == b; -} - -// CHECK-LABEL: @bi64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x i64>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x i64>, align 16 -// CHECK-NEXT: store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i64> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64> -// CHECK-NEXT: ret <2 x i64> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector long long bi64(vector bool long long a, vector bool long long b) { - return a == b; -} - -// CHECK-LABEL: @VecPixel( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector pixel VecPixel(vector pixel a, vector pixel b) { - return a == b; -} diff --git a/clang/test/CodeGen/vector-compat-ternary.c b/clang/test/CodeGen/vector-compat-ternary.c deleted file mode 100644 index 9a7d9d958513..000000000000 --- a/clang/test/CodeGen/vector-compat-ternary.c +++ /dev/null @@ -1,180 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s -// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR -// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s -// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s -// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s - -// CHECK-LABEL: @ui8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequb.p(i32 2, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(16 * sizeof(char)))) char' (vector of 16 'char' values) where arithmetic or pointer type is required -int ui8(vector unsigned char a, vector unsigned char b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @si8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequb.p(i32 2, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(16 * sizeof(char)))) char' (vector of 16 'char' values) where arithmetic or pointer type is required -int si8(vector signed char a, vector signed char b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @ui16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required -int ui16(vector unsigned short a, vector unsigned short b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @si16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required -int si16(vector signed short a, vector signed short b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @ui32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequw.p(i32 2, <4 x i32> [[TMP0]], <4 x i32> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required -int ui32(vector unsigned int a, vector unsigned int b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @si32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequw.p(i32 2, <4 x i32> [[TMP0]], <4 x i32> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required -int si32(vector signed int a, vector signed int b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @si64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x i64>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x i64>, align 16 -// CHECK-NEXT: store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> [[TMP0]], <2 x i64> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(2 * sizeof(long long)))) long long' (vector of 2 'long long' values) where arithmetic or pointer type is required -int si64(vector long long a, vector long long b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @f32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x float>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x float>, align 16 -// CHECK-NEXT: store <4 x float> [[A:%.*]], <4 x float>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <4 x float> [[B:%.*]], <4 x float>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpeqfp.p(i32 2, <4 x float> [[TMP0]], <4 x float> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required -int f32(vector float a, vector float b) { - return a == b ? 3 : 7; -} - -// CHECK-LABEL: @f64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x double>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x double>, align 16 -// CHECK-NEXT: store <2 x double> [[A:%.*]], <2 x double>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <2 x double> [[B:%.*]], <2 x double>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.vsx.xvcmpeqdp.p(i32 2, <2 x double> [[TMP0]], <2 x double> [[TMP1]]) -// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64 -// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7 -// CHECK-NEXT: ret i32 [[COND]] -// -// ERROR: error: used type '__attribute__((__vector_size__(2 * sizeof(long long)))) long long' (vector of 2 'long long' values) where arithmetic or pointer type is required -int f64(vector double a, vector double b) { - return a == b ? 3 : 7; -} diff --git a/clang/test/CodeGen/vector-compat.c b/clang/test/CodeGen/vector-compat.c deleted file mode 100644 index 5f9f8d1db357..000000000000 --- a/clang/test/CodeGen/vector-compat.c +++ /dev/null @@ -1,162 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR -// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s -// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \ -// RUN: -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR -// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s -// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s - -// CHECK-LABEL: @ui8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8> -// CHECK-NEXT: ret <16 x i8> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector unsigned char ui8(vector unsigned char a, vector unsigned char b) { - return a == b; -} - -// CHECK-LABEL: @si8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16 -// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8> -// CHECK-NEXT: ret <16 x i8> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector signed char si8(vector signed char a, vector signed char b) { - return a == b; -} - -// CHECK-LABEL: @ui16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector unsigned short ui16(vector unsigned short a, vector unsigned short b) { - return a == b; -} - -// CHECK-LABEL: @si16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16 -// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector signed short si16(vector signed short a, vector signed short b) { - return a == b; -} - -// CHECK-LABEL: @ui32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector unsigned int ui32(vector unsigned int a, vector unsigned int b) { - return a == b; -} - -// CHECK-LABEL: @si32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16 -// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector signed int si32(vector signed int a, vector signed int b) { - return a == b; -} - -// CHECK-LABEL: @si64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x i64>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x i64>, align 16 -// CHECK-NEXT: store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i64> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64> -// CHECK-NEXT: ret <2 x i64> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector long long si64(vector long long a, vector long long b) { - return a == b; -} - -// CHECK-LABEL: @f32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x float>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x float>, align 16 -// CHECK-NEXT: store <4 x float> [[A:%.*]], <4 x float>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <4 x float> [[B:%.*]], <4 x float>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <4 x float> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector int f32(vector float a, vector float b) { - return a == b; -} - -// CHECK-LABEL: @f64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x double>, align 16 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x double>, align 16 -// CHECK-NEXT: store <2 x double> [[A:%.*]], <2 x double>* [[A_ADDR]], align 16 -// CHECK-NEXT: store <2 x double> [[B:%.*]], <2 x double>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* [[A_ADDR]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[B_ADDR]], align 16 -// CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <2 x double> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64> -// CHECK-NEXT: ret <2 x i64> [[SEXT]] -// -// ERROR: returning 'int' from a function with incompatible result type -vector long long f64(vector double a, vector double b) { - return a == b; -} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits