Author: Jim Lin
Date: 2019-12-10T19:15:11+08:00
New Revision: 9c3966379813c198129c57aa3ebecd68d6af1ebd
URL:
https://github.com/llvm/llvm-project/commit/9c3966379813c198129c57aa3ebecd68d6af1ebd
DIFF:
https://github.com/llvm/llvm-project/commit/9c3966379813c198129c57aa3ebecd68d6af1ebd.diff
LOG:
Author: Andrew Gaul
Date: 2019-12-13T11:02:40+08:00
New Revision: 4daa8d1de6dda58aebfa7b19547ed3ce4e9bc91a
URL:
https://github.com/llvm/llvm-project/commit/4daa8d1de6dda58aebfa7b19547ed3ce4e9bc91a
DIFF:
https://github.com/llvm/llvm-project/commit/4daa8d1de6dda58aebfa7b19547ed3ce4e9bc91a.diff
Author: Jim Lin
Date: 2019-12-10T13:24:21+08:00
New Revision: cefac9dfaac9c806433ad88cca85bd2f3ba1edad
URL:
https://github.com/llvm/llvm-project/commit/cefac9dfaac9c806433ad88cca85bd2f3ba1edad
DIFF:
https://github.com/llvm/llvm-project/commit/cefac9dfaac9c806433ad88cca85bd2f3ba1edad.diff
LOG:
Author: Jim Lin
Date: 2020-03-02T18:16:35+08:00
New Revision: d40afadec0acd5f093a5f46fa2362312aef54189
URL:
https://github.com/llvm/llvm-project/commit/d40afadec0acd5f093a5f46fa2362312aef54189
DIFF:
https://github.com/llvm/llvm-project/commit/d40afadec0acd5f093a5f46fa2362312aef54189.diff
LOG:
Author: Jim Lin
Date: 2020-02-18T10:49:13+08:00
New Revision: 466f8843f526b03c8944a46af5ebb374133b5389
URL:
https://github.com/llvm/llvm-project/commit/466f8843f526b03c8944a46af5ebb374133b5389
DIFF:
https://github.com/llvm/llvm-project/commit/466f8843f526b03c8944a46af5ebb374133b5389.diff
LOG:
Author: Jim Lin
Date: 2020-02-19T09:28:41+08:00
New Revision: 492d4a992d88516da471b60ecd9a37ea80dbf9a4
URL:
https://github.com/llvm/llvm-project/commit/492d4a992d88516da471b60ecd9a37ea80dbf9a4
DIFF:
https://github.com/llvm/llvm-project/commit/492d4a992d88516da471b60ecd9a37ea80dbf9a4.diff
LOG:
Author: Jim Lin
Date: 2020-02-19T08:36:07+08:00
New Revision: ea789f819f26a1b003a1bf07466fc9fa2fe558ec
URL:
https://github.com/llvm/llvm-project/commit/ea789f819f26a1b003a1bf07466fc9fa2fe558ec
DIFF:
https://github.com/llvm/llvm-project/commit/ea789f819f26a1b003a1bf07466fc9fa2fe558ec.diff
LOG:
Author: Alexander Lanin
Date: 2020-01-02T19:30:29+08:00
New Revision: 8188c998ffa4d20253444b257402907d2aa74dc2
URL:
https://github.com/llvm/llvm-project/commit/8188c998ffa4d20253444b257402907d2aa74dc2
DIFF:
Author: Jim Lin
Date: 2020-01-07T17:35:44+08:00
New Revision: ab1bcda851d95aeec03ffc1218bf9cae261a9280
URL:
https://github.com/llvm/llvm-project/commit/ab1bcda851d95aeec03ffc1218bf9cae261a9280
DIFF:
https://github.com/llvm/llvm-project/commit/ab1bcda851d95aeec03ffc1218bf9cae261a9280.diff
LOG:
Author: Jim Lin
Date: 2020-05-18T13:13:22+08:00
New Revision: 7ee479a760e0a4402b4eb7fb6168768a44f66945
URL:
https://github.com/llvm/llvm-project/commit/7ee479a760e0a4402b4eb7fb6168768a44f66945
DIFF:
https://github.com/llvm/llvm-project/commit/7ee479a760e0a4402b4eb7fb6168768a44f66945.diff
LOG:
Author: Jim Lin
Date: 2021-03-31T14:06:20+08:00
New Revision: 32ca5a037ab9191d570bf9b5e0f13e28c3db27d9
URL:
https://github.com/llvm/llvm-project/commit/32ca5a037ab9191d570bf9b5e0f13e28c3db27d9
DIFF:
https://github.com/llvm/llvm-project/commit/32ca5a037ab9191d570bf9b5e0f13e28c3db27d9.diff
LOG:
Author: Jim Lin
Date: 2021-03-16T14:57:45+08:00
New Revision: 678241795c957b18bc473045e48abe3f2a61ff5c
URL:
https://github.com/llvm/llvm-project/commit/678241795c957b18bc473045e48abe3f2a61ff5c
DIFF:
https://github.com/llvm/llvm-project/commit/678241795c957b18bc473045e48abe3f2a61ff5c.diff
LOG:
Author: Jim Lin
Date: 2021-04-12T14:10:52+08:00
New Revision: 8a2d375a77bfd9d73f7dbb12bed5c8a014aa2a53
URL:
https://github.com/llvm/llvm-project/commit/8a2d375a77bfd9d73f7dbb12bed5c8a014aa2a53
DIFF:
https://github.com/llvm/llvm-project/commit/8a2d375a77bfd9d73f7dbb12bed5c8a014aa2a53.diff
LOG:
Author: Jim Lin
Date: 2022-01-10T10:43:13+08:00
New Revision: 9b70ddaff6e1d1ffc538ac74aa43b4fd6f73bb02
URL:
https://github.com/llvm/llvm-project/commit/9b70ddaff6e1d1ffc538ac74aa43b4fd6f73bb02
DIFF:
https://github.com/llvm/llvm-project/commit/9b70ddaff6e1d1ffc538ac74aa43b4fd6f73bb02.diff
LOG:
Author: Jim Lin
Date: 2022-01-27T13:56:13+08:00
New Revision: ad39b5bc59b0e71c86f8cf290ead2d9dd09e5c3e
URL:
https://github.com/llvm/llvm-project/commit/ad39b5bc59b0e71c86f8cf290ead2d9dd09e5c3e
DIFF:
https://github.com/llvm/llvm-project/commit/ad39b5bc59b0e71c86f8cf290ead2d9dd09e5c3e.diff
LOG:
Author: Jim Lin
Date: 2022-01-25T22:46:12+08:00
New Revision: f3314e3747873fdf026a28742a30f372503baf32
URL:
https://github.com/llvm/llvm-project/commit/f3314e3747873fdf026a28742a30f372503baf32
DIFF:
https://github.com/llvm/llvm-project/commit/f3314e3747873fdf026a28742a30f372503baf32.diff
LOG:
Author: Jim Lin
Date: 2023-08-30T14:09:31+08:00
New Revision: d099dbb221a4c3474a15117b1658dedc5dcd6ebf
URL:
https://github.com/llvm/llvm-project/commit/d099dbb221a4c3474a15117b1658dedc5dcd6ebf
DIFF:
https://github.com/llvm/llvm-project/commit/d099dbb221a4c3474a15117b1658dedc5dcd6ebf.diff
LOG:
Author: Jim Lin
Date: 2023-08-30T16:05:55+08:00
New Revision: c1dda0f7934d28eb8dfc92206c49b188a1a091de
URL:
https://github.com/llvm/llvm-project/commit/c1dda0f7934d28eb8dfc92206c49b188a1a091de
DIFF:
https://github.com/llvm/llvm-project/commit/c1dda0f7934d28eb8dfc92206c49b188a1a091de.diff
LOG:
@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
tclin914 wrote:
Author: Jim Lin
Date: 2023-08-18T12:56:12+08:00
New Revision: af7231d1835b3dbfd938c7fdff8188ce49a3b58b
URL:
https://github.com/llvm/llvm-project/commit/af7231d1835b3dbfd938c7fdff8188ce49a3b58b
DIFF:
https://github.com/llvm/llvm-project/commit/af7231d1835b3dbfd938c7fdff8188ce49a3b58b.diff
LOG:
Author: Jim Lin
Date: 2023-06-15T10:22:06+08:00
New Revision: dc895d023e63fd9276fe493eded776e101015c86
URL:
https://github.com/llvm/llvm-project/commit/dc895d023e63fd9276fe493eded776e101015c86
DIFF:
https://github.com/llvm/llvm-project/commit/dc895d023e63fd9276fe493eded776e101015c86.diff
LOG:
Author: Jim Lin
Date: 2023-07-14T16:09:11+08:00
New Revision: 8fe0449ac99087c74f785ddbdd4fbba65b396b3b
URL:
https://github.com/llvm/llvm-project/commit/8fe0449ac99087c74f785ddbdd4fbba65b396b3b
DIFF:
https://github.com/llvm/llvm-project/commit/8fe0449ac99087c74f785ddbdd4fbba65b396b3b.diff
LOG:
Author: Jim Lin
Date: 2023-06-07T09:29:49+08:00
New Revision: d4c5b452934a31f9b3685cf58bd682104b686d1a
URL:
https://github.com/llvm/llvm-project/commit/d4c5b452934a31f9b3685cf58bd682104b686d1a
DIFF:
https://github.com/llvm/llvm-project/commit/d4c5b452934a31f9b3685cf58bd682104b686d1a.diff
LOG:
Author: Jim Lin
Date: 2023-05-22T10:28:27+08:00
New Revision: 33d3d51d77a7fb7ca6b919f9ba47999cd8531844
URL:
https://github.com/llvm/llvm-project/commit/33d3d51d77a7fb7ca6b919f9ba47999cd8531844
DIFF:
https://github.com/llvm/llvm-project/commit/33d3d51d77a7fb7ca6b919f9ba47999cd8531844.diff
LOG:
Author: Jim Lin
Date: 2023-08-07T14:03:33+08:00
New Revision: d7abafa6a03f3aa66b18b16cb040795201870845
URL:
https://github.com/llvm/llvm-project/commit/d7abafa6a03f3aa66b18b16cb040795201870845
DIFF:
https://github.com/llvm/llvm-project/commit/d7abafa6a03f3aa66b18b16cb040795201870845.diff
LOG:
Author: Jim Lin
Date: 2023-08-08T13:01:34+08:00
New Revision: 767ca3a70d6d60bd52ff0829335942aa6dafcc28
URL:
https://github.com/llvm/llvm-project/commit/767ca3a70d6d60bd52ff0829335942aa6dafcc28
DIFF:
https://github.com/llvm/llvm-project/commit/767ca3a70d6d60bd52ff0829335942aa6dafcc28.diff
LOG:
Author: Jim Lin
Date: 2023-08-02T10:46:42+08:00
New Revision: 1c1066797c5bb56616dc485b596fd40d5f03ece2
URL:
https://github.com/llvm/llvm-project/commit/1c1066797c5bb56616dc485b596fd40d5f03ece2
DIFF:
https://github.com/llvm/llvm-project/commit/1c1066797c5bb56616dc485b596fd40d5f03ece2.diff
LOG:
Author: Jim Lin
Date: 2023-06-26T13:15:37+08:00
New Revision: 612b7e10a9afa797d41e134bc62a8ef87a014caf
URL:
https://github.com/llvm/llvm-project/commit/612b7e10a9afa797d41e134bc62a8ef87a014caf
DIFF:
https://github.com/llvm/llvm-project/commit/612b7e10a9afa797d41e134bc62a8ef87a014caf.diff
LOG:
https://github.com/tclin914 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/79615
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https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/76422
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https://github.com/llvm/llvm-project/pull/76422
None
>From 460d1b9ece1fb208047a8c35088bd5dcb12279b2 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 27 Dec 2023 11:19:21 +0800
Subject: [PATCH] [RISCV] Remove redundant variable Log2LMUL for vset
intrinsic.
@@ -386,6 +393,11 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector ,
if (llvm::is_contained(Features, "+experimental"))
HasExperimental = true;
+ if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) {
+Diags.Report(diag::err_invalid_feature_combination)
+
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/77866
>From #75735, Zvfh implies Zvfhmin.
>From be8d27cf8a3cf511598437a401a2277b36752137 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Fri, 12 Jan 2024 09:58:49 +0800
Subject: [PATCH] [RISCV] Change required features
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/77866
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@@ -282,6 +282,9 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
}
}
+ if (BaseType == BasicType::BFloat16 && !TI.hasFeature("zvfbfmin"))
tclin914 wrote:
bfloat vector is only valid when zvfbfmin is enabled. So it doesn't need
@@ -797,6 +797,13 @@ def FeatureStdExtSvpbmt
: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
"'Svpbmt' (Page-Based Memory Types)">;
+def FeatureStdExtZalasr
tclin914 wrote:
Could we put this definition after Zacas.
@@ -0,0 +1,66 @@
+//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*-
tablegen -*-===//
tclin914 wrote:
exceed 80 characters
https://github.com/llvm/llvm-project/pull/79911
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@@ -0,0 +1,66 @@
+//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*-
tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+//
https://github.com/tclin914 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/79618
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@@ -0,0 +1,479 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN: -target-feature +zvfh
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL =
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL =
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL =
@@ -0,0 +1,218 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN: -target-feature +zvfh
@@ -21189,6 +21189,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
case RISCV::BI__builtin_riscv_clmulh_64:
case RISCV::BI__builtin_riscv_clmulr_32:
case RISCV::BI__builtin_riscv_clmulr_64:
+ case RISCV::BI__builtin_riscv_mopr_32:
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/87095
In M68kRegisterInfo.td, register SP is defined with name sp and alternate name
a7.
Fixes: https://github.com/llvm/llvm-project/issues/78620
>From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/87095
>From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Sat, 30 Mar 2024 01:37:49 +0800
Subject: [PATCH 1/3] [M68k] Change gcc register name from a7 to sp
In
tclin914 wrote:
> Is it possible use `TargetInfo::getGCCRegAliases` to model the aliasing
> between a7 and sp? Also, could you add a simple test?
Implement getGCCRegAliases and add testcase.
https://github.com/llvm/llvm-project/pull/87095
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https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/87095
>From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Sat, 30 Mar 2024 01:37:49 +0800
Subject: [PATCH 1/2] [M68k] Change gcc register name from a7 to sp
In
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/87095
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https://github.com/llvm/llvm-project/pull/87264
Enable frame pointer optimization by default to match it with gcc.
Fixes: https://github.com/llvm/llvm-project/issues/75013
>From 4eeb31d4ad8503db9a1cc079eeb9aa4186136719 Mon Sep 17 00:00:00 2001
From: Jim Lin
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