[PATCH] D64739: [SVE][Inline-Asm] Add support to clang for SVE inline assembly

kmclaughlin created this revision. kmclaughlin added reviewers: erichkeane, sdesmalen, cfe-commits. Herald added subscribers: psnobl, rkruppe, tschuett, javed.absar. Herald added a reviewer: rengolin. Herald added a project: clang. Adds the SVE vector and predicate registers to the list of known r

[PATCH] D64739: [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

kmclaughlin updated this revision to Diff 210821. kmclaughlin retitled this revision from "[SVE][Inline-Asm] Add support to clang for SVE inline assembly" to "[SVE][Inline-Asm] Add support to specify SVE registers in the clobber list". kmclaughlin added a comment. - Removed typo fixes from this

[PATCH] D64739: [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

kmclaughlin updated this revision to Diff 24. kmclaughlin added a comment. - Updated test to remove unused variable 't' CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64739/new/ https://reviews.llvm.org/D64739 Files: clang/lib/Basic/Targets/AArch64.cpp clang/test/CodeGen/aarch64

[PATCH] D64739: [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

kmclaughlin updated this revision to Diff 211264. kmclaughlin added a comment. - Removed second test in aarch64-sve-inline-asm.c which didn't use //-emit-llvm// CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64739/new/ https://reviews.llvm.org/D64739 Files: clang/lib/Basic/Targets/AA

[PATCH] D66302: [SVE][Inline-Asm] Support for SVE asm operands

kmclaughlin created this revision. kmclaughlin added reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov. Herald added subscribers: psnobl, rkruppe, tschuett, javed.absar. Herald added a reviewer: rengolin. Herald added a project: LLVM. Adds the following inline asm constraints for SVE: -

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

kmclaughlin updated this revision to Diff 219526. kmclaughlin added a comment. - Renamed the //isPredicateConstraint// function to //parsePredicateConstraint// - Added more thorough checks to the tests in aarch64-sve-asm.ll CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66524/new/ https:

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

kmclaughlin marked 3 inline comments as done. kmclaughlin added inline comments. Comment at: docs/LangRef.rst:3818 +- ``Upl``: One of the low eight SVE predicate registers (P0 to P7) +- ``Upa``: Any of the SVE predicate registers (P0 to P15) greened wrote: > Wh

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, SjoerdMeijer, greened. Herald added subscribers: jdoerfert, tschuett. Herald added a project: LLVM. Both match the type of another intrinsic parameter of a vector type, but where each element is subdivided to form a vector

[PATCH] D67550: [AArch64][SVE] Implement unpack intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, SjoerdMeijer, greened. Herald added subscribers: psnobl, rkruppe, kristof.beyls, tschuett. Herald added a reviewer: rengolin. kmclaughlin added a parent revision: D67549: [IntrinsicEmitter] Add overloaded types for SVE intr

[PATCH] D67551: [AArch64][SVE] Implement sdot and udot (lane) intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, SjoerdMeijer, greened. Herald added subscribers: psnobl, rkruppe, kristof.beyls, tschuett. Herald added a reviewer: rengolin. kmclaughlin added a parent revision: D67549: [IntrinsicEmitter] Add overloaded types for SVE intr

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

This revision was automatically updated to reflect the committed changes. Closed by commit rL371967: [SVE][Inline-Asm] Add constraints for SVE predicate registers (authored by kmclaughlin, committed by ). Changed prior to commit: https://reviews.llvm.org/D66524?vs=219526&id=220299#toc Reposito

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

kmclaughlin updated this revision to Diff 220845. kmclaughlin marked 5 inline comments as done. kmclaughlin added a reviewer: rovka. kmclaughlin added a comment. - Moved getNarrowerFpElementVectorType logic into getTruncatedElementVectorType - Shared code which handles Subdivide2Argument and Subdi

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

kmclaughlin added a comment. Thanks for reviewing this patch, @rovka and @sdesmalen! Comment at: include/llvm/IR/Intrinsics.h:130 + Kind == PtrToElt || Kind == VecElementArgument || + Kind == Subdivide2Argument || Kind == Subdivide4Argument); retu

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

kmclaughlin updated this revision to Diff 220886. kmclaughlin added a comment. - Some minor changes, including removing an unnecessary break - Simplified checks of D.Kind in Function.cpp to determine if it is a Subdivide2Argument or Subdivide4Argument CHANGES SINCE LAST ACTION https://reviews

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

This revision was automatically updated to reflect the committed changes. Closed by commit rL372380: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 &… (authored by kmclaughlin, committed by ). Changed prior to commit: https://reviews.llvm.org/D67549?vs=220886&id=220988#t

[PATCH] D67830: [AArch64][SVE] Implement punpk[hi|lo] intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, rovka. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. Adds the following two intrinsics: - int_aarch64_sve_punpkhi - int_aarc

[PATCH] D68021: [IntrinsicEmitter] Add overloaded type VecOfBitcastsToInt for SVE intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: c-rhodes, sdesmalen, rovka. Herald added subscribers: jdoerfert, hiraditya, tschuett. Herald added a project: LLVM. This allows intrinsics such as the following to be defined: - declare @llvm.something.nxv4f32(, , ) ...where is de

[PATCH] D68023: [AArch64][SVE] Implement int_aarch64_sve_cnt intrinsic

kmclaughlin created this revision. kmclaughlin added reviewers: c-rhodes, sdesmalen, rovka. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a project: LLVM. kmclaughlin added a parent revision: D68021: [IntrinsicEmitter] Add overloaded type VecOfBitcasts

[PATCH] D67830: [AArch64][SVE] Implement punpk[hi|lo] intrinsics

This revision was automatically updated to reflect the committed changes. Closed by commit rL373232: [AArch64][SVE] Implement punpk[hi|lo] intrinsics (authored by kmclaughlin, committed by ). Changed prior to commit: https://reviews.llvm.org/D67830?vs=221010&id=222458#toc Repository: rL LLVM

[PATCH] D68021: [IntrinsicEmitter] Add overloaded type VecOfBitcastsToInt for SVE intrinsics

This revision was automatically updated to reflect the committed changes. Closed by commit rL373437: [IntrinsicEmitter] Add overloaded type VecOfBitcastsToInt for SVE intrinsics (authored by kmclaughlin, committed by ). Changed prior to commit: https://reviews.llvm.org/D68021?vs=221756&id=22277

[PATCH] D68023: [AArch64][SVE] Implement int_aarch64_sve_cnt intrinsic

kmclaughlin updated this revision to Diff 222780. kmclaughlin added a comment. - Fixes alignment of last argument to //sve_int_un_pred_arit_1// in AArch64SVEInstrInfo.td CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68023/new/ https://reviews.llvm.org/D68023 Files: llvm/include/llvm

[PATCH] D68023: [AArch64][SVE] Implement int_aarch64_sve_cnt intrinsic

This revision was automatically updated to reflect the committed changes. Closed by commit rL373468: [AArch64][SVE] Implement int_aarch64_sve_cnt intrinsic (authored by kmclaughlin, committed by ). Changed prior to commit: https://reviews.llvm.org/D68023?vs=222780&id=222814#toc Repository: r

[PATCH] D67550: [AArch64][SVE] Implement unpack intrinsics

kmclaughlin updated this revision to Diff 224558. kmclaughlin added a comment. Removed unused //SDPatternOperator op// from sve_int_perm_unpk class CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67550/new/ https://reviews.llvm.org/D67550 Files: include/llvm/IR/IntrinsicsAArch64.td l

[PATCH] D67550: [AArch64][SVE] Implement unpack intrinsics

kmclaughlin marked 2 inline comments as done. kmclaughlin added inline comments. Comment at: lib/Target/AArch64/SVEInstrFormats.td:836 class sve_int_perm_unpk sz16_64, bits<2> opc, string asm, -ZPRRegOp zprty1, ZPRRegOp zprty2> +ZP

[PATCH] D67551: [AArch64][SVE] Implement sdot and udot (lane) intrinsics

This revision was automatically updated to reflect the committed changes. Closed by commit rGee0a0a34646f: [AArch64][SVE] Implement sdot and udot (lane) intrinsics (authored by kmclaughlin). Herald added a subscriber: hiraditya. Herald added a project: LLVM. Changed prior to commit: https://rev

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: huntergr, rovka, greened. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a project: LLVM. kmclaughlin added a parent revision: D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node. Adds suppor

[PATCH] D67550: [AArch64][SVE] Implement unpack intrinsics

This revision was automatically updated to reflect the committed changes. kmclaughlin marked an inline comment as done. Closed by commit rG0c7cc383e5b8: [AArch64][SVE] Implement unpack intrinsics (authored by kmclaughlin). Herald added a subscriber: hiraditya. Herald added a project: LLVM. Change

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

kmclaughlin updated this revision to Diff 225900. kmclaughlin edited the summary of this revision. kmclaughlin added a comment. - Rebased patch, removed extra sext & zext combine from DAGCombine which are no longer necessary - Added isVectorLoadExtDesirable to AArch64ISelLowering - Added more che

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

kmclaughlin marked 4 inline comments as done. kmclaughlin added a comment. Thanks for reviewing this, @dmgreen! I have updated the patch to make use of the changes to DAGCombine introduced by D68337 . Comment at: llvm/lib/CodeGen/SelectionDAG/

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

kmclaughlin updated this revision to Diff 226123. kmclaughlin added a comment. - Removed unnecessary pseudo from SVEInstrFormats.td CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68877/new/ https://reviews.llvm.org/D68877 Files: llvm/include/llvm/CodeGen/SelectionDAG.h llvm/lib/Code

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

kmclaughlin marked an inline comment as done. kmclaughlin added a comment. In D68877#1717820 , @dmgreen wrote: > I'm not sure if there is support yet for vector selects in the SVE codegen? There is not yet support for vector selects, so for this patch th

[PATCH] D69378: [AArch64][SVE] Implement masked store intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: huntergr, greened, dmgreen, rovka. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a project: LLVM. Adds support for codegen of masked stores, with non-truncating and truncating variants.

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

This revision was automatically updated to reflect the committed changes. Closed by commit rGda720a38b9f2: [AArch64][SVE] Implement masked load intrinsics (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D68877?vs=226123&id=226628#toc Repository: rG LLVM Github Mo

[PATCH] D69378: [AArch64][SVE] Implement masked store intrinsics

kmclaughlin updated this revision to Diff 226640. kmclaughlin added a reviewer: sdesmalen. kmclaughlin added a comment. - Split functions in sve-masked-ldst-nonext.ll into separate load & store tests CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69378/new/ https://reviews.llvm.org/D6937

[PATCH] D69378: [AArch64][SVE] Implement masked store intrinsics

kmclaughlin updated this revision to Diff 226885. kmclaughlin added a comment. - Removed masked load tests from sve-masked-ldst-trunc.ll CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69378/new/ https://reviews.llvm.org/D69378 Files: llvm/lib/Target/AArch64/AArch64InstrInfo.td llvm/

[PATCH] D69567: [AArch64][SVE] Implement additional integer arithmetic intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: huntergr, sdesmalen. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a project: LLVM. Add intrinsics for the following: - sxt[b|h|w] & uxt[b|h|w] - cls & clz - not & cnot Repository: rG

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin updated this revision to Diff 267183. kmclaughlin edited the summary of this revision. kmclaughlin added a comment. - Removed ReplaceExtensionResults and instead try to use extract_subvector as much as possible to legalise the result - Added ReplaceExtractSubVectorResults, which repla

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin updated this revision to Diff 267280. kmclaughlin added a comment. - Replaced uses of getVectorNumElements() with getVectorElementCount() - Moved the new tests into the existing sve-sext-zext.ll file CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79587/new/ https://reviews.ll

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin updated this revision to Diff 267695. kmclaughlin marked 7 inline comments as done. kmclaughlin added a comment. - Restricted the illegal types which should be lowered for EXTRACT_SUBVECTOR to those handled in this patch (nxv8i8, nxv4i16 & nxv2i32) - Removed unnecessary changes in Rep

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin marked 2 inline comments as done. kmclaughlin added a comment. Thanks for taking another look at this, @efriedma! Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10676 +ConstantSDNode *C = dyn_cast(Dup->getOperand(0)); +uint64_t ExtVal = C->getZE

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin marked an inline comment as not done. kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10676 +ConstantSDNode *C = dyn_cast(Dup->getOperand(0)); +uint64_t ExtVal = C->getZExtValue(); + efriedma wrot

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin updated this revision to Diff 267919. kmclaughlin marked 2 inline comments as done. kmclaughlin added a comment. - Added a truncate of ExtVal in performSVEAndCombine - Changed the assert added to performSignExtendInRegCombine in the previous revision CHANGES SINCE LAST ACTION http

[PATCH] D77054: [AArch64][SVE] Add SVE intrinsics for saturating add & subtract

This revision was automatically updated to reflect the committed changes. Closed by commit rG944e322f8897: [AArch64][SVE] Add SVE intrinsics for saturating add & subtract (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77054/

[PATCH] D76078: [AArch64][SVE] Add a pass for SVE intrinsic optimisations

kmclaughlin added a comment. Ping :) CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76078/new/ https://reviews.llvm.org/D76078 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commit

[PATCH] D76078: [AArch64][SVE] Add a pass for SVE intrinsic optimisations

This revision was automatically updated to reflect the committed changes. Closed by commit rG36c76de6789c: [AArch64][SVE] Add a pass for SVE intrinsic optimisations (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76078/new/

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin updated this revision to Diff 257349. kmclaughlin marked 4 inline comments as done. kmclaughlin edited the summary of this revision. kmclaughlin added a comment. Simplified performLD1RQCombine method & added negative tests where the immediate is out of range. CHANGES SINCE LAST ACTI

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin marked 2 inline comments as done. kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11592 +static SDValue performLD1RQCombine(SDNode *N, SelectionDAG &DAG) { + SDLoc DL(N); andwar wrote: > [Nit] I think

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin updated this revision to Diff 257657. kmclaughlin marked an inline comment as done. kmclaughlin added a comment. Ensure LoadChain is always preserved in performLD1RQCombine CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76929/new/ https://reviews.llvm.org/D76929 Files: llv

[PATCH] D78204: [AArch64][SVE] Remove LD1/ST1 dependency on llvm.masked.load/store

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, cameron.mcinally, c-rhodes. Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. The SVE masked load and stor

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11622 + if (VT.isFloatingPoint()) +Load = DAG.getNode(ISD::BITCAST, DL, VT, Load); + sdesmalen wrote: > I'd expect this to then use `Load.getValue(0)` ? I think th

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin updated this revision to Diff 268246. kmclaughlin added a comment. - Use APInt::trunc to truncate the constant in performSVEAndCombine CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79587/new/ https://reviews.llvm.org/D79587 Files: llvm/include/llvm/CodeGen/ValueTypes.h

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

This revision was automatically updated to reflect the committed changes. Closed by commit rG89fc0166f532: [CodeGen][SVE] Legalisation of extends with scalable types (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79587/new/

[PATCH] D79167: [SVE][CodeGen] Legalisation of vsetcc with scalable types

kmclaughlin updated this revision to Diff 271391. kmclaughlin retitled this revision from "[SVE][CodeGen] Legalise scalable vector types for vsetcc & vselect" to "[SVE][CodeGen] Legalisation of vsetcc with scalable types". kmclaughlin edited the summary of this revision. kmclaughlin added a comme

[PATCH] D82943: [SVE] Add more warnings checks to clang and LLVM SVE tests

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82943/new/ https://reviews.llvm.org/D82943 _

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, c-rhodes, efriedma, stuij, fpetrogalli, david-arm. Herald added subscribers: llvm-commits, cfe-commits, danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added projects: clang, LLVM. Bfloat16 support

[PATCH] D79167: [SVE][CodeGen] Legalisation of vsetcc with scalable types

kmclaughlin added a comment. In D79167#2098774 , @efriedma wrote: > Is it possible to write tests for this that don't result in a "max" or "min" > operation? Or does that fail for some other reason? > > Otherwise LGTM. Thanks for reviewing this, @efrie

[PATCH] D79167: [SVE][CodeGen] Legalisation of vsetcc with scalable types

kmclaughlin updated this revision to Diff 272483. kmclaughlin added a comment. Added tests to llvm-ir-to-intrinsic.ll which check the results of compare instructions CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79167/new/ https://reviews.llvm.org/D79167 Files: llvm/lib/CodeGen/Sele

[PATCH] D79167: [SVE][CodeGen] Legalisation of vsetcc with scalable types

This revision was automatically updated to reflect the committed changes. Closed by commit rG508050317403: [SVE][CodeGen] Legalisation of vsetcc with scalable types (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79167/new/

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

kmclaughlin updated this revision to Diff 272759. kmclaughlin added a comment. - Moved bfloat tests into separate files - Added checks to the bfloat test files which test the warnings given when ARM_FEATURE_SVE_BF16 is omitted in the RUN line CHANGES SINCE LAST ACTION https://reviews.llvm.org

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

This revision was automatically updated to reflect the committed changes. Closed by commit rG3d6cab271c7c: [AArch64][SVE] Add bfloat16 support to load intrinsics (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82298/new/ htt

[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, c-rhodes, fpetrogalli, efriedma, stuij, david-arm. Herald added subscribers: llvm-commits, cfe-commits, danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added projects: clang, LLVM. Bfloat16 support

[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics

kmclaughlin updated this revision to Diff 273092. kmclaughlin added a comment. - Added [HasBF16] predicate to new store pattern in AArch64SVEInstrInfo.td - Check hasBF16() is true for bfloat16 types in performST1Combine/performSTNT1Combine - Added bfloat16 test to sve-pred-contiguous-ldst-address

[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics

kmclaughlin marked 4 inline comments as done. kmclaughlin added a comment. Thanks for reviewing this again, @fpetrogalli! Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c:4 +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC

[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics

kmclaughlin updated this revision to Diff 273331. kmclaughlin added a comment. - Added HasSVE to Predicates in AArch64SVEInstrInfo.td - Removed unnecessary indentation changes in AArch64SVEInstrInfo.td - Removed hasBF16 variable from performST1Combine/performSTNT1Combine CHANGES SINCE LAST ACTIO

[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics

This revision was automatically updated to reflect the committed changes. Closed by commit rGedcfef8fee13: [AArch64][SVE] Add bfloat16 support to store intrinsics (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82448/new/ ht

[PATCH] D78204: [AArch64][SVE] Remove LD1/ST1 dependency on llvm.masked.load/store

This revision was automatically updated to reflect the committed changes. Closed by commit rG33ffce5414ec: [AArch64][SVE] Remove LD1/ST1 dependency on llvm.masked.load/store (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D78204?vs=257702&id=258694#toc Repository:

[PATCH] D78509: [AArch64][SVE] Add addressing mode for contiguous loads & stores

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, fpetrogalli, efriedma. Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. This patch adds the register + register add

[PATCH] D78509: [AArch64][SVE] Add addressing mode for contiguous loads & stores

kmclaughlin updated this revision to Diff 258954. kmclaughlin marked 5 inline comments as done. kmclaughlin added a comment. - Renamed ld1nf multiclass to ldnf1 - Split out existing reg+imm tests into their own files - Renamed 'offset' to 'index' in reg+reg tests CHANGES SINCE LAST ACTION http

[PATCH] D78509: [AArch64][SVE] Add addressing mode for contiguous loads & stores

kmclaughlin added a comment. Thanks for taking a look at this, @fpetrogalli! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78509/new/ https://reviews.llvm.org/D78509 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm

[PATCH] D78509: [AArch64][SVE] Add addressing mode for contiguous loads & stores

This revision was automatically updated to reflect the committed changes. Closed by commit rG0df40d6ef8b8: [AArch64][SVE] Add addressing mode for contiguous loads & stores (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D78509?vs=258954&id=258965#toc Repository:

[PATCH] D78569: [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, c-rhodes, efriedma, cameron.mcinally. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. This patch maps IR operations for sdiv &

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11622 + if (VT.isFloatingPoint()) +Load = DAG.getNode(ISD::BITCAST, DL, VT, Load); + sdesmalen wrote: > kmclaughlin wrote: > > sdesmalen wrote: > > > I'd expect th

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin updated this revision to Diff 259035. kmclaughlin marked an inline comment as done. kmclaughlin added a comment. - Use Load.getValue(0) when creating a bitcast in performLD1RQCombine CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76929/new/ https://reviews.llvm.org/D76929 Fi

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

This revision was automatically updated to reflect the committed changes. Closed by commit rG17f6e18acf5b: [AArch64][SVE] Add SVE intrinsic for LD1RQ (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76929/new/ https://reviews

[PATCH] D77871: [AArch64] Armv8.6-a Matrix Mult Assembly + Intrinsics

kmclaughlin added inline comments. Comment at: clang/test/CodeGen/aarch64-v8.6a-neon-intrinsics.c:3 +// RUN: -fallow-half-arguments-and-returns -S -disable-O0-optnone -emit-llvm -o - %s \ +// RUN: | opt -S -mem2reg \ +// RUN: | FileCheck %s Is it possible to use

[PATCH] D77871: [AArch64] Armv8.6-a Matrix Mult Assembly + Intrinsics

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. Thanks for the updates, @LukeGeeson, LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77871/new/ https://reviews.llvm.org/D77871 ___

[PATCH] D78569: [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics

kmclaughlin updated this revision to Diff 259610. kmclaughlin added a comment. - Removed changes to handle legalisation from this patch (this will be included in a follow up) - Added AArch64ISD nodes for SDIV_PRED & UDIV_PRED - Changed LowerDIV to use the new ISD nodes rather than lowering to SVE

[PATCH] D78569: [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics

This revision was automatically updated to reflect the committed changes. kmclaughlin marked an inline comment as done. Closed by commit rG53dd72a87aeb: [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D78569?vs=2596

[PATCH] D78569: [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics

kmclaughlin added a comment. Thank you both for your comments on this patch, @efriedma & @sdesmalen! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78569/new/ https://reviews.llvm.org/D78569 ___ cfe-com

[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, huntergr. Herald added subscribers: psnobl, rkruppe, hiraditya, tschuett. Herald added a project: LLVM. This patch handles illegal scalable types when lowering IR operations, addressing several places where the va

[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

kmclaughlin updated this revision to Diff 260603. kmclaughlin added a comment. - Use ElementCount with getVectorVT CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78812/new/ https://reviews.llvm.org/D78812 Files: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/CodeGen/

[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

kmclaughlin marked 2 inline comments as done. kmclaughlin added inline comments. Comment at: llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll:107 + ret %div +} efriedma wrote: > Maybe also worth adding a testcase for ``, assuming that > doesn't expose anythin

[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

kmclaughlin marked an inline comment as done. kmclaughlin added inline comments. Comment at: llvm/lib/CodeGen/TargetLoweringBase.cpp:1429 + !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) { +EltCnt.Min >>= 1; NumVectorRegs <<= 1; I will c

[PATCH] D79087: [SVE][Codegen] Lower legal min & max operations

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, dancgr. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. This patch adds AArch64ISD nodes for [S|U]MIN_PRED and [S|U]M

[PATCH] D79167: [SVE][CodeGen] Legalise scalable vector types for vsetcc & vselect

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, dancgr. Herald added subscribers: psnobl, rkruppe, hiraditya, tschuett. Herald added a project: LLVM. kmclaughlin added a parent revision: D79087: [SVE][Codegen] Lower legal min & max operations. The visitSelect

[PATCH] D79087: [SVE][Codegen] Lower legal min & max operations

kmclaughlin marked an inline comment as done. kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:3851 + def : SVE_1_Op_Imm_Arith_Pred_Pat(NAME # _S)>; + def : SVE_1_Op_Imm_Arith_Pred_Pat(NAME # _D)>; } efriedma wrote: > I

[PATCH] D79087: [SVE][Codegen] Lower legal min & max operations

kmclaughlin updated this revision to Diff 261462. kmclaughlin added a comment. - Added tests for the intrinsics where the second operand is an immediate - Changed the range SelectSVESignedArithImm checks for, as the range for the immediates of smin & smax is -128 to +127 (inclusive) CHANGES SIN

[PATCH] D79087: [SVE][Codegen] Lower legal min & max operations

kmclaughlin marked an inline comment as done. kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:3851 + def : SVE_1_Op_Imm_Arith_Pred_Pat(NAME # _S)>; + def : SVE_1_Op_Imm_Arith_Pred_Pat(NAME # _D)>; } efriedma wrote: > k

[PATCH] D79087: [SVE][Codegen] Lower legal min & max operations

This revision was automatically updated to reflect the committed changes. Closed by commit rG19f5da9c1d69: [SVE][Codegen] Lower legal min & max operations (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D79087?vs=261462&id=261787#toc Repository: rG LLVM Github Mo

[PATCH] D79478: [CodeGen][SVE] Lowering of shift operations with scalable types

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, ctetreau, huihuiz. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. kmclaughlin added a parent revision: D78812: [SVE][

[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

This revision was automatically updated to reflect the committed changes. Closed by commit rGa31f4c52bf85: [SVE][CodeGen] Fix legalisation for scalable types (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D78812?vs=260603&id=262580#toc Repository: rG LLVM Github

[PATCH] D79478: [CodeGen][SVE] Lowering of shift operations with scalable types

This revision was automatically updated to reflect the committed changes. Closed by commit rG3bcd3dd4734d: [CodeGen][SVE] Lowering of shift operations with scalable types (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D79478?vs=262333&id=262600#toc Repository: r

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, david-arm. Herald added subscribers: psnobl, rkruppe, hiraditya, tschuett. Herald added a project: LLVM. This patch adds legalisation of extensions where the operand of the extend is a legal scalable type but the

[PATCH] D151197: [Clang][SVE2p1] Add svpsel builtins

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. Thank you for updating this @CarolineConcatto, LGTM Comment at: clang/include/clang/Basic/arm_sve.td:1886 + + nit: extra whitespace Repository:

[PATCH] D151307: [Clang][SVE2.1] Add svwhile (predicate-as-counter) builtins

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151307/new/ https://reviews.llvm.org/D151307 _

[PATCH] D151433: [Clang][SVE2.1] Add builtins for Multi-vector load and store

kmclaughlin added inline comments. Comment at: clang/include/clang/Basic/arm_sve.td:1920 + +def SVST1B_X2 : MInst<"svst1[_{2}_x2]", "v}p2", "cUc", [IsStructStore,], MemEltTyDefault, "aarch64_sve_st1_pn_x2">; +def SVST1H_X2 : MInst<"svst1[_{2}_x2]", "v}p2", "sUshb", [IsStructStor

[PATCH] D151433: [Clang][SVE2.1] Add builtins for Multi-vector load and store

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. Thanks @CarolineConcatto, LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151433/new/ https://reviews.llvm.org/D151433 __

[PATCH] D66302: [SVE][Inline-Asm] Support for SVE asm operands

kmclaughlin updated this revision to Diff 216178. kmclaughlin added a comment. - Added a new test file, aarch64-sve-asm-negative.ll - Updated description of the 'y' constraint in LangRef.rst CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66302/new/ https://reviews.llvm.org/D66302 File

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

kmclaughlin created this revision. kmclaughlin added reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, cameron.mcinally, greened. Herald added subscribers: psnobl, rkruppe, tschuett, javed.absar. Herald added a reviewer: rengolin. Herald added a project: LLVM. kmclaughlin added a parent

[PATCH] D66302: [SVE][Inline-Asm] Support for SVE asm operands

kmclaughlin updated this revision to Diff 216574. kmclaughlin added a comment. - Changed printAsmRegInClass in AArch64AsmPrinter.cpp to accept //unsigned AltName// instead of //bool isVector// - Added a comment to explain the test in aarch64-sve-asm-negative.ll CHANGES SINCE LAST ACTION https

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