[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

khchen added a comment. LGTM, thanks for the patch! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69383/new/ https://reviews.llvm.org/D69383 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

khchen updated this revision to Diff 227606. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67508/new/ https://reviews.llvm.org/D67508 Files: clang/lib/Driver/ToolChains/Gnu.cpp clang/lib/Driver/ToolChains/RISCVToolchain.cpp

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

khchen updated this revision to Diff 229507. khchen added a comment. rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67508/new/ https://reviews.llvm.org/D67508 Files: clang/lib/Driver/ToolChains/Gnu.cpp

[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

khchen marked an inline comment as done. khchen added inline comments. Comment at: clang/lib/Driver/ToolChains/CommonArgs.cpp:498 +CmdArgs.push_back( +Args.MakeArgString(Twine("-plugin-opt=-target-abi=") + ABIName)); } efriedma wrote: > I don't

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen updated this revision to Diff 233082. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71124/new/ https://reviews.llvm.org/D71124 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Basic/Targets/RISCV.h

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen marked 3 inline comments as done. khchen added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:164 + +static constexpr llvm::StringLiteral ValidRV32CPUNames[] = {{"generic-rv32"}, +

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen marked an inline comment as done. khchen added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:585 +const llvm::opt::ArgList , +llvm::opt::ArgStringList ) { + // -mabi is not encoded

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen added a comment. In D71387#1786518 , @efriedma wrote: > My primary concern with this is that I'm not sure you should be passing this > information separately, as opposed to encoding it into the bitcode. > > On ARM, the ABI for a file is generally

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen updated this revision to Diff 233508. khchen added a comment. update missed code.. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71387/new/ https://reviews.llvm.org/D71387 Files: clang/lib/Driver/ToolChains/Arch/RISCV.cpp

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen created this revision. khchen added a project: clang. Herald added subscribers: cfe-commits, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27,

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen created this revision. khchen added reviewers: efriedma, lenary, asb, shiva0217, tejohnson. khchen added a project: clang. Herald added subscribers: cfe-commits, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, jocewei, PkmX, rkruppe, dexonsmith, the_o, brucehoult, MartinMosbeck,

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

khchen updated this revision to Diff 229966. khchen added a comment. rebase and fix failed testcases Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67508/new/ https://reviews.llvm.org/D67508 Files: clang/lib/Driver/ToolChains/Gnu.cpp

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

This revision was automatically updated to reflect the committed changes. Closed by commit rGb6d7bbfa0043: [RISCV] Support mutilib in baremetal environment (authored by khchen, committed by Zakk Chen zakk.c...@sifive.com). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

khchen added a comment. Re-applied with test fix in https://reviews.llvm.org/rG4fccd383d571865321b4723b81c3042d2c15fd80 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67508/new/ https://reviews.llvm.org/D67508

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen added a comment. In D71387#1788472 , @efriedma wrote: > > Unfortunately on RISCV, the ABI info is only derived from -mabi option and > > the target triple does not encode ABI info (same to gcc). > > How does gcc decide the default ABI for a

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen added a comment. In D71387#1790413 , @efriedma wrote: > > But in RISCV clang emits the same IR for different ABI (-mabi), > > This is not true. For simple cases, it does, yes, but there are some weird > edge cases for functions with many

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen planned changes to this revision. khchen marked an inline comment as done. khchen added a comment. The problem is how `-mcpu` interact with explicitly specified `-march` (or target features). 1. in GCC, -mcpu is only used to chose the pipeline model, 2. I also read this

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen planned changes to this revision. khchen added a subscriber: eli.friedman. khchen added a comment. I asked @kito-cheng about the GCC LTO behavior, GCC LTO encodes the ABI info in elf and the behavior in above examples match to @efriedma 's responses. So I think maybe encode ABI in module

[PATCH] D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata

khchen updated this revision to Diff 237084. khchen edited the summary of this revision. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72245/new/ https://reviews.llvm.org/D72245 Files: clang/lib/CodeGen/CodeGenModule.cpp clang/lib/Driver/ToolChains/RISCVToolchain.cpp

[PATCH] D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata

khchen updated this revision to Diff 237114. khchen added a comment. remote LTO related code. this PoC include D70837 patch for generate correct code. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72245/new/ https://reviews.llvm.org/D72245 Files:

[PATCH] D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata

khchen added a subscriber: efriedma. khchen added a comment. Hi @efriedma Could you please guide me and review this PoC? or take a look at this [[ take a look at | maillist ]] thread? Thank you! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72245/new/ https://reviews.llvm.org/D72245

[PATCH] D72755: [RISCV] Pass target-abi via module flag metadata

khchen created this revision. khchen added reviewers: lenary, asb. khchen added a project: clang. Herald added subscribers: cfe-commits, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones,

[PATCH] D72755: [RISCV] Pass target-abi via module flag metadata

khchen added a comment. In D72755#1821540 , @lenary wrote: > Please can you also add code for ensuring that the `target-abi` module flag > matches the `-target-abi` command line flag in llvm? please see D72768 , thanks!

[PATCH] D72624: [WIP] TargetMachine Hook for Module Metadata

khchen added a comment. I think putting the resetTargetDefaultOptions after instance of TargetMachine is too late. for example: ppc and mips

[PATCH] D72624: [WIP] TargetMachine Hook for Module Metadata

khchen added a comment. In D72624#1818605 , @khchen wrote: > I think putting the resetTargetDefaultOptions after instance of TargetMachine > is too late. > for example: > ppc >

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen marked an inline comment as done. khchen added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:164 + +static constexpr llvm::StringLiteral ValidRV32CPUNames[] = {{"generic-rv32"}, +

[PATCH] D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata

khchen created this revision. Herald added subscribers: llvm-commits, cfe-commits, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, dang, jocewei, PkmX, rkruppe, dexonsmith, the_o, brucehoult, MartinMosbeck, rogfer01, steven_wu, edward-jones, zzheng, MaskRay,

[PATCH] D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata

khchen updated this revision to Diff 236296. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72245/new/ https://reviews.llvm.org/D72245 Files: clang/lib/CodeGen/CodeGenModule.cpp clang/lib/Driver/ToolChains/RISCVToolchain.cpp clang/lib/Driver/ToolChains/RISCVToolchain.h

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen added a comment. I'd like to discuss what is good way to pass target-abi in maillist after I had a try to encoding ABI info into LLVM IR via module flag. any suggestions are welcome, thanks. Repository: rG LLVM

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen added a comment. @lenary (Sorry for the very late reply...) In D71124#1829998 , @lenary wrote: > In D71124#1792216 , @khchen wrote: > > > The problem is how `-mcpu` interact with explicitly specified

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen updated this revision to Diff 255377. khchen added reviewers: evandro, HsiangKai. khchen added a comment. Herald added a subscriber: hiraditya. update implementation and handle `-mcpu` with explicitly specified `-march`. If `-mcpu` has default march, explicitly `-march` will overwrite it.

[PATCH] D72624: [WIP] TargetMachine Hook for Module Metadata

khchen added a comment. Herald added a reviewer: herhut. Herald added subscribers: frgossen, grosul1, Joonsoo. Hi @lenary, I added a PoC patch D78035 to complete ThinLTO based on this patch. There is also a missed hook in `ParallelCG.cpp` @@ -28,6 +28,7 @@

[PATCH] D76757: Fix typo, targetFeature should be lowercase.

This revision was automatically updated to reflect the committed changes. Closed by commit rG64fe84185602: Fix typo, targetFeature should be lowercase. (authored by khchen, committed by Zakk Chen zakk.c...@sifive.com). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen updated this revision to Diff 261741. khchen added a comment. address kito's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71124/new/ https://reviews.llvm.org/D71124 Files: clang/lib/Basic/Targets/RISCV.cpp

[PATCH] D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV

khchen updated this revision to Diff 261132. khchen retitled this revision from "[PoC][RISCV] enable LTO/ThinLTO on RISCV " to "[PoC][RISCV] enable LTO/ThinLTO on RISCV". khchen edited the summary of this revision. khchen added a comment. Herald added a project: clang. Herald added a subscriber:

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen updated this revision to Diff 261165. khchen marked 9 inline comments as done. khchen added a comment. address @lenary's review feedback Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71124/new/ https://reviews.llvm.org/D71124 Files:

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen added a comment. In D71124#2010759 , @lenary wrote: > This is looking good. > > I remember we discussed this on the LLVM call a few weeks ago - there was a > discussion as to whether we should be prioritising `-march` or `-mcpu` - do > you recall

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen added a comment. In D71124#2012090 , @kito-cheng wrote: > Another proposal for -mcpu and -mtune: > > Decoupling the -mcpu and -mtune option, -mcpu only accept concrete CPU, and > -mtune for micro-arch/pipeline model, they accept different option

[PATCH] D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV

khchen updated this revision to Diff 262322. khchen added a comment. update testcases Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78035/new/ https://reviews.llvm.org/D78035 Files: clang/lib/Driver/ToolChains/RISCVToolchain.cpp

[PATCH] D89025: [RISCV] Add -mtune support

khchen added a comment. RISCV supports `-mcpu` with default empty arch to align gcc's `-mtune` behavior since clang didn't support `-mtune` before. But now clang has `-mtune`, is it a good idea to remove those options? (ex. `rocket-rv32/rv64`, `sifive-7-rv32/64`) Comment at:

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen planned changes to this revision. khchen marked an inline comment as done. khchen added a comment. BTW, this patch depends on D77030 , which aim to avoid the forcing of any ProcessorModel to have `FeatureRVCHints` feature. But if we decide to keep the

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen updated this revision to Diff 276951. khchen added a comment. addess asb's comment. [RISCV][Clang] Support -mcpu option. Summary: 1. gcc uses `-march` and `-mtune` flag to chose arch and pipeline model, but clang does not have `-mtune` flag, we uses `-mcpu` to chose both info. 2. Add

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen updated this revision to Diff 277067. khchen added a comment. avoid to check compiler version in testcase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71124/new/ https://reviews.llvm.org/D71124 Files: clang/lib/Basic/Targets/RISCV.cpp

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen updated this revision to Diff 277042. khchen added a comment. fix typo Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71124/new/ https://reviews.llvm.org/D71124 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Basic/Targets/RISCV.h

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen added a comment. Hi @lenary This is normal behavior in current clang implementation, `-mcpu=?` flag does not interact with any flags, it just print out the all of ProcessorModel registered in backend.

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen updated this revision to Diff 278106. khchen marked 8 inline comments as done. khchen added a comment. address @asb's comment. thanks. Thanks for @lenary bug report. I cannot reproduce the crash in local, but I though the problem is cause by removing "Choose a default based on the

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen updated this revision to Diff 278197. khchen added a comment. address @lenary's comment, good catch!! thanks!! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71124/new/ https://reviews.llvm.org/D71124 Files:

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen added a comment. @asb @lenary I thought this path is ready to land? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71124/new/ https://reviews.llvm.org/D71124 ___ cfe-commits mailing list

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen added a comment. In D71124#2415424 , @oceanfish81 wrote: > I tried to build the following: > >

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

khchen added inline comments. Comment at: clang/include/clang/Basic/RISCVVTypes.def:67 +RVV_VECTOR_TYPE_INT("__rvv_int8m2_t", RvvInt8m2, RvvInt8m2Ty, 16, 8, 1, true) +RVV_VECTOR_TYPE_INT("__rvv_int8m4_t", RvvInt8m4, RvvInt8m4Ty, 32, 8, 1, true)

[PATCH] D71124: [RISCV] support clang driver to select cpu

khchen added a comment. > How does the CLI options correspond with the back-end capabilities? `clang -print-supported-cpus` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71124/new/ https://reviews.llvm.org/D71124