[PATCH] D63498: [RISC-V] Add -msave-restore and -mno-save-restore to clang driver

lenary created this revision. lenary added reviewers: asb, luismarques. Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar. Herald adde

[PATCH] D63498: [RISC-V] Add -msave-restore and -mno-save-restore to clang driver

lenary updated this revision to Diff 205846. lenary added a comment. - Add CHECK lines for warnings Hopefully these will work regardless of race conditions in the merging of stdout and stderr. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63498/new

[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

lenary accepted this revision. lenary added a comment. This revision is now accepted and ready to land. Looks good to me! Thank you! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64737/new/ https://reviews.llvm.org/D64737 ___

[PATCH] D65500: [RISCV] Support 'f' Inline Assembly Constraint

This revision was automatically updated to reflect the committed changes. Closed by commit rL367403: [RISCV] Support 'f' Inline Assembly Constraint (authored by lenary, committed by ). Changed prior to commit: https://reviews.llvm.org/D65500?vs=212513&id=212543#toc Repository: rL LLVM CHANG

[PATCH] D65500: [RISCV] Support 'f' Inline Assembly Constraint

lenary created this revision. lenary added reviewers: asb, lewis-revill. Herald added subscribers: llvm-commits, cfe-commits, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sa

[PATCH] D65500: [RISCV] Support 'f' Inline Assembly Constraint

lenary updated this revision to Diff 212513. lenary added a comment. - Simplify inline-asm-invalid.ll test Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65500/new/ https://reviews.llvm.org/D65500 Files: clang/lib/Basic/Targets/RISCV.cpp clang/

[PATCH] D57795: [RISCV] Add FreeBSD targets

This revision was automatically updated to reflect the committed changes. Closed by commit rL367557: [RISCV] Add FreeBSD targets (authored by lenary, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit: https://reviews.llvm.org/D57795?v

[PATCH] D48357: [RISCV] Remove duplicated logic when determining the target ABI

lenary added a comment. Herald added subscribers: s.egerton, Jim, benna, psnobl, MaskRay. Given we now have support for the floating-point ABIs, can you rebase and update this patch? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D48357/new/ https://reviews.llvm.org/D48357 ___

[PATCH] D54214: [RISCV] Set triple based on -march flag

lenary added a comment. What happens if I pass `clang -march=rv32i -target riscv64-unknown-elf`? Should we care about the ordering of `-march` vs `-target`? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54214/new/ https://reviews.llvm.org/D54214

[PATCH] D63497: Add support for openSUSE RISC-V triple

This revision was automatically updated to reflect the committed changes. Closed by commit rL367565: Add support for openSUSE RISC-V triple (authored by lenary, committed by ). Herald added a subscriber: s.egerton. Changed prior to commit: https://reviews.llvm.org/D63497?vs=206423&id=212814#toc

[PATCH] D63497: Add support for openSUSE RISC-V triple

lenary added a comment. Thanks @schwab, sorry we took so long to merge your patch, but it's merged now! Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63497/new/ https://reviews.llvm.org/D63497 ___ cfe-commits mailing

[PATCH] D48357: [RISCV] Remove duplicated logic when determining the target ABI

lenary accepted this revision. lenary added a comment. This revision is now accepted and ready to land. Ok, sure! I think I'm happy for this to land then. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D48357/new/ https://reviews.llvm.org/D48357

[PATCH] D65634: [RISCV] Default to lp64d in 64-bit RISC-V Linux

lenary added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:385 + ? "ilp32" + : Triple.getOS() == llvm::Triple::Linux ? "lp64d" : "lp64"; } Please may you turn this into a set of if-statements? Nesting ternary ope

[PATCH] D66266: [WIP][RISCV] Set MaxAtomicPromoteWidth and MaxAtomicInlineWidth

lenary added a comment. Hi Pengxuan, Thanks for the patch! We have a similar patch from @asb under review at the moment, D57450 . There's one question about ABI compatibility that still needs to be answered, which we will discuss in the RISC-V sync-up later tod

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

lenary added a comment. Herald added subscribers: s.egerton, MaskRay. Given this is an ABI-compatibility issue, I've been looking at how GCC and Clang differ in how they deal with issues around size and alignment of atomic objects. All types of size less than or equal to `MaxAtomicPromoteWidth`

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

lenary commandeered this revision. lenary added a reviewer: asb. lenary added a comment. Chatted to @asb and he wants me to take over this set of changes. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57450/new/ https://reviews.llvm.org/D57450

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

lenary planned changes to this revision. lenary added a comment. Upon further thought, I realise that `MaxAtomicPromoteWidth` should be set to 128 regardless of whether a target `HasA`. I will be updating the patch with the new width and conditions early next week. Repository: rC Clang CHAN

[PATCH] D63498: [RISC-V] Add -msave-restore and -mno-save-restore to clang driver

This revision was automatically updated to reflect the committed changes. Closed by commit rL364018: [RISC-V] Add -msave-restore and -mno-save-restore to clang driver (authored by lenary, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commi

[PATCH] D64008: [RISCV] Avoid save-restore target feature warning

lenary created this revision. lenary added a reviewer: asb. Herald added subscribers: cfe-commits, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar. He

[PATCH] D64008: [RISCV] Avoid save-restore target feature warning

This revision was automatically updated to reflect the committed changes. Closed by commit rL364777: [RISCV] Avoid save-restore target feature warning (authored by lenary, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit: https://rev

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

lenary added a subscriber: luismarques. lenary added a comment. Nice, I like this new approach! One naming nit, but overall I think this is much better than the first version of the patch. LGTM but I would like @luismarques to take a look too. Comment at: llvm/lib/Target/RISC

[PATCH] D67065: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly

lenary added a comment. LGTM, now I've looked at how LLVM itself supports code models. I don't mind if that TODO is or isn't deleted. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67065/new/ https://reviews.llvm.org/D67065 _

[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

lenary added a comment. Can you add a test for `riscv64-unknown-linux-gnu`? I think RISCVToolchain.cpp is only used by the `riscv64-unknown-elf` target, but I could be wrong. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67409/new/ https://reviews.llvm.org/D6740

[PATCH] D67066: [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow

lenary accepted this revision. lenary added a comment. This revision is now accepted and ready to land. Looks good to me! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67066/new/ https://reviews.llvm.org/D67066 __

[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

lenary added a comment. I have some nits about explicit comments for arguments and default argument values for backwards compatibility. Other than that, it looks like a nice code cleanup. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:6071 // Add the target features -

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

lenary added a comment. We discussed this in the RISC-V meeting on 19 Sept 2019. @apazos says there are some SPEC failures in both 2006 and 2017, which would be good to triage. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62686/new/ https://revie

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

lenary added a comment. Two nits, that I wanted to submit before the meeting, but didn't get around to. Comment at: llvm/lib/Target/RISCV/RISCV.td:72 +def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", + "tr

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

lenary added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:72 +def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", + "true", "Enable save/restore.">; lewis-revill wrote: > lenary

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

lenary added a comment. Nice! Thanks for adding support for RISC-V. I like the use of the ABI register names rather than the numeric names. I have a few queries/nits, below. Comment at: libunwind/include/libunwind.h:835 +// 64-bit RISC-V registers +enum { P

[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

lenary accepted this revision. lenary added a comment. This revision is now accepted and ready to land. Herald added a subscriber: hiraditya. Nice, LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67409/new/ https://reviews.llvm.org/D67409 __

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

lenary added a comment. Note, D68862 is in-progress at the moment, which is related to this patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67185/new/ https://reviews.llvm.org/D67185 __

[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

lenary added a comment. @khchen do you need me to commit this for you? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67409/new/ https://reviews.llvm.org/D67409 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

This revision was automatically updated to reflect the committed changes. Closed by commit rGcdcf58e5af02: [RISCV] enable LTO support, pass some options to linker. (authored by lenary). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67409/new/ https:

[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

lenary added a comment. @khchen Thanks for your patch! It is now landed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67409/new/ https://reviews.llvm.org/D67409 ___ cfe-commits mailing list cfe-commit

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

lenary added a comment. Please can you rebase these changes? Something has changed in RISCVToolchain.cpp and they are failing to build. Q: Is there a plan to support multilib aliases (`MULTILIB_REUSE`)? I'm happy for this to be in a follow-up patch, would just like to know the plan.

[PATCH] D68407: [RISCV] Use compiler-rt if no GCC installation detected

lenary requested changes to this revision. lenary added a comment. This revision now requires changes to proceed. Please can you add a test for riscv32 and riscv64 without libgcc? I also think you want to be smarter about detecting the need/request for libgcc. Look for `AddRunTimeLibs` in clang/

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

lenary added a comment. One query, but this patch is starting to look good. I'm not a libunwind expert - it would be good to have one of the libunwind contributors look over this patch yet. Can you add one as a reviewer? Comment at: libunwind/src/Registers.hpp:3677 + case UN

[PATCH] D68391: [RISCV] Improve sysroot computation if no GCC install detected

lenary added a comment. In D68391#1694622 , @edward-jones wrote: > Rebased and added tests > > I've made this use the Triple from the driver rather than the parsed LLVM > triple, this means the Triple doesn't get normalized which seems like more > desir

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

lenary added inline comments. Comment at: libunwind/src/Registers.hpp:3756 +inline double Registers_riscv::getFloatRegister(int regNum) const { +#ifdef __riscv_float_abi_double + assert(validFloatRegister(regNum)); mhorne wrote: > lenary wrote: > > Is this an AB

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

lenary accepted this revision. lenary added a comment. This revision is now accepted and ready to land. I finally got my system well setup enough to check this patch with my risc-v toolchains. It looks good, I'm happy for this to land. There's no requirement to support MULTILIB_REUSE yet. It mig

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

lenary requested changes to this revision. lenary added a comment. This revision now requires changes to proceed. Sorry for approving, and then requesting changes. I've been investigating issues with this patch. When I try to use `-print-multi-lib` (a clang option that is very under-documented,

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

lenary added a comment. Ok, found a path forward for this patch. Notes inline: Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1547 + else if (IsRV64) +MArch = "rv64i"; + else khchen wrote: > lenary wrote: > > I think this line is the issue: where someone

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

lenary added inline comments. Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1547 + else if (IsRV64) +MArch = "rv64i"; + else lenary wrote: > khchen wrote: > > lenary wrote: > > > I think this line is the issue: where someone doesn't specify `-march`, > >

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

lenary created this revision. lenary added reviewers: asb, luismarques, rogfer01, kito-cheng, khchen. Herald added subscribers: cfe-commits, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, niosHD, s

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

lenary updated this revision to Diff 226252. lenary added a comment. - Correct code formatting issue Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69383/new/ https://reviews.llvm.org/D69383 Files: clang/lib/Driver/ToolChains/Arch/RISCV.cpp cla

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

lenary marked an inline comment as done. lenary added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:475 + +if (MArch.startswith_lower("rv32")) { + if (MArch.substr(4).contains_lower("d") || rogfer01 wrote: > `llvm::StringSwitch`

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

lenary marked an inline comment as done. lenary added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:537 + if (Triple.getArch() == llvm::Triple::riscv32) +return "rv32gc"; else khchen wrote: > Why do you set rv32gc and rv64gc as d

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

lenary added a comment. In D67508#1720228 , @khchen wrote: > But there is some issue if we set the default rv32 march as `rv32gc`. > Because the default multilib does not include `rv32gc`/`lp32d` in riscv gnu > toolchain, > https://github.com/riscv/r

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

lenary marked an inline comment as done. lenary added a comment. I agree backwards compatibility is hard here. - This method was introduced to have a single place to choose a default `march` string if none was chosen before. I think this change is useful (saves defaults being calculated in a mu

[PATCH] D68391: [RISCV] Improve sysroot computation if no GCC install detected

lenary accepted this revision. lenary added a comment. This revision is now accepted and ready to land. Herald added a subscriber: sameer.abuasal. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68391/new/ https://reviews.llvm.org/D68391 __

[PATCH] D80963: [WIP][clang] Allow {u}int_fastN_t to be different to {u}int_leastN_t

lenary created this revision. lenary added reviewers: luismarques, asb. Herald added a project: clang. This is in order to support psABIs where these two type sizes do not match for specific values of N. The default implementation matches clang's current behaviour where `getLeastIntTypeByWidth` is

[PATCH] D81083: [Clang] Allow "vector_size" applied to Booleans

lenary added inline comments. Comment at: clang/docs/LanguageExtensions.rst:473 +architectures. The size parameter of a boolean vector type is the number of +bits in the vector (for all non-bool vectors, the number refers to the number +of bytes in the vector).

[PATCH] D71124: [RISCV] support clang driver to select cpu

lenary added a comment. I realise this is almost certainly something we want to land before the LLVM 11 branch date, as we included schedules in LLVM 10 with no way to use them, and would like users to be able to use them. I'll bring it up on the call tomorrow - I hope this PR implements what w

[PATCH] D71124: [RISCV] support clang driver to select cpu

lenary added a comment. I've got one major issue (inline below), and I'm confused by some other behaviour: When I run `clang --target=riscv64 -mcpu=?`, the list includes both `generic-rv32` and `generic-rv64`. It doesn't show only the 64-bit cpus. This is not changed by giving a full triple, o

[PATCH] D71124: [RISCV] support clang driver to select cpu

lenary added a comment. Thanks for the fix! Please can you also update `clang/test/Misc/target-invalid-cpu-note.c` for riscv32 and riscv64 - it's likely you'll need the fix in the inline note below. Also, there are a bunch of clang-tidy issues, which I think we can fix now rather than later.

[PATCH] D71124: [RISCV] support clang driver to select cpu

lenary accepted this revision. lenary added a comment. This revision is now accepted and ready to land. I am happy with this. I think we should get it landed so we can backport it to the LLVM 11 branch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/

[PATCH] D71124: [RISCV] support clang driver to select cpu

lenary added a comment. Herald added a project: LLVM. Herald added a subscriber: llvm-commits. This is looking good. I remember we discussed this on the LLVM call a few weeks ago - there was a discussion as to whether we should be prioritising `-march` or `-mcpu` - do you recall the outcome of

[PATCH] D79322: [FEnv] Small fixes to implementation of flt.rounds

lenary added inline comments. Comment at: llvm/test/CodeGen/RISCV/flt-rounds.ll:23 +; RV64I-NEXT:sd ra, 8(sp) +; RV64I-NEXT:call __flt_rounds +; RV64I-NEXT:ld ra, 8(sp) I'm interested to understand how this function is provided. Is it part of `compil

[PATCH] D128415: [ARM] Add Support for Cortex-M85

lenary updated this revision to Diff 442079. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D128415/new/ https://reviews.llvm.org/D128415 Files: clang/docs/ReleaseNotes.rst clang/test/CodeGen/arm-target-features.c clang/test/Driver/arm-cortex-cp

[PATCH] D128415: [ARM] Add Support for Cortex-M85

lenary marked an inline comment as done. lenary added a comment. The other changes in this commit are to enable PACBTI by default, as agreed with stakeholders within Arm. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D128415/new/ https://reviews.ll

[PATCH] D128415: [ARM] Add Support for Cortex-M85

lenary added a comment. In D128415#3628274 , @tschuett wrote: > The Clang release notes indicate that PACBTI is off by default. In several > places, I can see PACBTI. Is the `ARM.td` missing something? Nope, I should have re-checked the whole patch. Upd

[PATCH] D128415: [ARM] Add Support for Cortex-M85

lenary updated this revision to Diff 442109. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D128415/new/ https://reviews.llvm.org/D128415 Files: clang/docs/ReleaseNotes.rst clang/test/CodeGen/arm-target-features.c clang/test/Driver/arm-cortex-cp

[PATCH] D128415: [ARM] Add Support for Cortex-M85

lenary added a comment. @tschuett I've corrected the patch based on your feedback. If you're happy, I'm going to land this. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D128415/new/ https://reviews.llvm.org/D128415 ___

[PATCH] D128415: [ARM] Add Support for Cortex-M85

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG1666f09933ee: [ARM] Add Support for Cortex-M85 (authored by lenary). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://revi

[PATCH] D128653: [PowerPC] Fix the check for scalar MASS conversion

lenary added a comment. You likely need `// REQUIRES: powerpc-registered-target` in the top of the test, as `-enable-ppc-gen-scalar-mass` is only present if the PowerPC target has been compiled into LLVM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.o

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary added a comment. In D119720#3339855 , @dmgreen wrote: > I have a high level question regarding RDF, as I've not seen it used in many > other places, so it may be under-tested on Arm systems at the moment. This > currently, for all code, builds an

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary updated this revision to Diff 419202. lenary added a comment. - Rewrite pass in terms of ReachingDefAnalysis - Split tests into separate commit, for ease of review. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119720/new/ https://reviews.ll

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary removed a reviewer: kparzysz. lenary added a comment. @kparzysz I have rewritten this to avoid using RDFGraph, so I don't think this needs you to review it any more. Comment at: llvm/test/CodeGen/ARM/aes-erratum-fix.ll:49 + +define <16 x i8> @aese_once_via_val(<16 x i8>

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary planned changes to this revision. lenary added inline comments. Comment at: llvm/lib/CodeGen/RDFGraph.cpp:1096 RegisterRef RR = PDA.Addr->getRegRef(*this); -#ifndef NDEBUG -// Assert if the register is defined in two or more unrelated defs. -// This could happ

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary updated this revision to Diff 419208. lenary added a comment. - Remove whitespace change in ARMSubtarget - Remove commented-out debug lines in RDFGraph Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119720/new/ https://reviews.llvm.org/D11972

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary added a comment. Thanks for the review. Lots of comments inline, hopefully Phab doesn't mangle the large one. Comment at: llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp:145 + case ARM::VMVNq: +return CondCodeIsAL(3); + // VMOV of 64-bit value between D regi

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary marked 6 inline comments as done. lenary added a comment. A few comments before I post the next version of the patch. Comment at: llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp:145 + case ARM::VMVNq: +return CondCodeIsAL(3); + // VMOV of 64-bit value between

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary updated this revision to Diff 421193. lenary marked 2 inline comments as done. lenary added a comment. - Updated set of safe instructions - Address reviewer feedback, including reordering passes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D

[PATCH] D119301: [AArch64][ARM] add -Wunaligned-access only for clang

lenary added a comment. I don't fully understand the reasoning for the patch, and you haven't really explained it. I think what you are saying is that the `IsAux` argument to `getTargetFeatures` should be considered because it's `true` for offloading to another compiler, but I don't understand

[PATCH] D119301: [AArch64][ARM] add -Wunaligned-access only for clang

lenary accepted this revision. lenary added a comment. This revision is now accepted and ready to land. Ah, I see. Please can you also remove the `CmdArgs` parameter from `arm::getARMTargetFeatures` when you commit this? This would be useful, along with a comment at the top of `getTargetFeature

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary added a comment. @kparzysz I've tagged you due to the changes in RDFGraph, which I believe you are the owner of. The asserts are hit in `llvm/test/CodeGen/ARM/inlineasm-error-t-toofewregs.ll` - the Register Allocator Chokes on the test due to not having enough registers for the inline a

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary added a comment. Ack to all the comment clarifications, will update patch with those soon (probably tomorrow). Comment at: llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp:146 + case ARM::VMVNd: + case ARM::VMVNq: + // VMOV of 64-bit value between D registers (w

[PATCH] D122747: [NFC][ARM] Tests for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary updated this revision to Diff 428975. lenary added a comment. Herald added subscribers: cfe-commits, MaskRay, hiraditya, mgorny. Herald added a project: clang. - Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D122747/new/ https://review

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary updated this revision to Diff 428978. lenary marked 3 inline comments as done. lenary added a comment. - Address comment nits - Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119720/new/ https://reviews.llvm.org/D119720 Files: clang

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary marked 3 inline comments as done. lenary added inline comments. Comment at: llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp:12-19 +// The intention is this: +// - Any 128-bit or 64-bit writes to the neon input register of an AES fused +// pair are safe (the inputs

[PATCH] D122747: [NFC][ARM] Tests for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary added a comment. I want to keep the number of llvm functions the same, as they cover a wide variety of control flow at a wide variety of data widths which the pass should cope with. One thing that I would like to cut down is the duplicated set of CHECK lines, one with scheduling and one

[PATCH] D122747: [NFC][ARM] Tests for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary added a comment. In D122747#3509495 , @lenary wrote: > I want to keep the number of llvm functions the same, as they cover a wide > variety of control flow at a wide variety of data widths which the pass > should cope with. > > One thing that I w

[PATCH] D122747: [NFC][ARM] Tests for Cortex-A57 and Cortex-A72 Fused AES Erratum

lenary added a comment. I spent some time last night trying to work out if a combination of `--enable-misched=false --pre-RA-sched=linearize -disable-post-ra -enable-post-misched=false` would help avoid having two sets of match lines, and none seemed to. @MaskRay as I can't find a quick way of

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG3a24df992cf8: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum (authored by lenary). Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D125775: [ARM] Don't Enable AES Pass for Generic Cores

lenary created this revision. lenary added reviewers: john.brawn, dmgreen. Herald added subscribers: hiraditya, kristof.beyls. Herald added a project: All. lenary requested review of this revision. Herald added projects: clang, LLVM. Herald added a subscriber: cfe-commits. This brings clang/llvm i

[PATCH] D125775: [ARM] Don't Enable AES Pass for Generic Cores

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2321c36fbf76: [ARM] Don't Enable AES Pass for Generic Cores (authored by lenary). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

lenary updated this revision to Diff 216594. lenary added a comment. Herald added a subscriber: pzheng. Update MaxAtomicPromote width to treat it like an ABI feature, and set it to 128 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57450/new/ https:

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

lenary added a comment. Cross linking to the relevant psABI pull request (still pending): https://github.com/riscv/riscv-elf-psabi-doc/pull/112 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57450/new/ https://reviews.llvm.org/D57450 ___

[PATCH] D66591: [RISCV] Correct Logic around ilp32e macros

lenary created this revision. lenary added reviewers: luismarques, asb. Herald added subscribers: cfe-commits, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal,

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

lenary added a comment. @jyknight I hear where you're coming from. I'll see what I can do about the psABI document. In that ticket, it's mentioned that the Darwin ABI explicitly says that non-power-of-two atomic types should be padded and realigned, but I cannot find any documentation explaini

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

lenary added a comment. In D57450#1641308 , @jyknight wrote: > In D57450#1641190 , @lenary wrote: > > > @jyknight I hear where you're coming from. I'll see what I can do about the > > psABI document. > > > > In tha

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

lenary updated this revision to Diff 217413. lenary added a comment. Address review feedback: - Add Test for MaxAtomicPromoteWidth Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57450/new/ https://reviews.llvm.org/D57450 Files: clang/lib/Basic/T

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

This revision was automatically updated to reflect the committed changes. Closed by commit rL370073: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64… (authored by lenary, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior

[PATCH] D67065: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly

lenary added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:91 Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32"); // TODO: modify when more code models are supported. + StringRef CodeModel = getTargetOpts().CodeModel; This TODO can

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

lenary added a comment. Backported to 9.0 in rL370181 Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57450/new/ https://reviews.llvm.org/D57450 ___ cfe-commits mailing list cfe-commi

[PATCH] D66591: [RISCV] Correct Logic around ilp32e macros

This revision was automatically updated to reflect the committed changes. Closed by commit rL370709: [RISCV] Correct Logic around ilp32e macros (authored by lenary, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit: https://reviews.ll

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

lenary added a comment. I don't quite understand all the details of this patch. I understand reserving registers that the compiler would otherwise be using as general-purpose registers. But what do we do about using registers within the calling convention when someone says they should be reser

[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

lenary accepted this revision. lenary added a comment. This revision is now accepted and ready to land. Herald added a subscriber: pzheng. I think my feeling is that this patch can land and we can change the default abi for baremetal targets in a follow-up patch. Comment at: c

[PATCH] D36949: [clang] Fix tests for Emitting Single Inline Remark

lenary created this revision. This change depends on https://reviews.llvm.org/D36054 and should be landed at the same time. https://reviews.llvm.org/D36949 Files: test/Frontend/optimization-remark-with-hotness.c test/Frontend/optimization-remark.c Index: test/Frontend/optimization-remark

[PATCH] D36949: [clang] Fix tests for Emitting Single Inline Remark

This revision was automatically updated to reflect the committed changes. Closed by commit rL311347: [clang] Fix tests for Emitting Single Inline Remark (authored by lenary). Repository: rL LLVM https://reviews.llvm.org/D36949 Files: cfe/trunk/test/Frontend/optimization-remark-with-hotness.

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