subject:"\[PATCH\] D108886\: Add RISC\-V sifive\-s51 cpu"

[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-02 Thread Alexander Pivovarov via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6cd4b508a8a5: [RISCV] Add SiFive core S51 (authored by 
apivovarov).

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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
  FeatureStdExtM,
  FeatureStdExtA,
Index: llvm/include/llvm/Support/RISCVTargetParser.def
===
--- llvm/include/llvm/Support/RISCVTargetParser.def
+++ llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
Index: clang/test/Misc/target-invalid-cpu-note.c
===
--- clang/test/Misc/target-invalid-cpu-note.c
+++ clang/test/Misc/target-invalid-cpu-note.c
@@ -196,7 +196,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-u54, sifive-u74
+// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -204,4 +204,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-u54, sifive-u74, generic, rocket, sifive-7-series
+// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74, generic, rocket, 
sifive-7-series
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | 
FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
+
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck 
-check-prefix=MCPU-SIFIVE-U54 %s
 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -71,7 +71,9 @@
 Modified Compiler Flags
 ---
 
-- ...
+- Support has been added for the following processors (``-mcpu`` identifiers 
in parentheses):
+
+  - RISC-V SiFive S51 (``sifive-s51``).
 
 Removed Compiler Flags
 -


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,

[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Evandro Menezes via Phabricator via cfe-commits

evandro added a comment.

In D108886#2978169 , @apivovarov 
wrote:

> Add Cortex-A78C Support for Clang and LLVM 
> 
>  is similar to this patch.  As we can see `cortex-a78c` support was included 
> to the ReleaseNotes 12.x 
> .
>  From the other side adding `sifive-e76` and `sifive-u74` support has not 
> been mentioned in the Release Notes for version 12.0

Fair enough.


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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Alexander Pivovarov via Phabricator via cfe-commits

apivovarov added a comment.

Add Cortex-A78C Support for Clang and LLVM 

 is similar to this patch.  As we can see `cortex-a78c` support was included to 
the ReleaseNotes 12.x 
.
 From the other side adding `sifive-e76` and `sifive-u74` support has not been 
mentioned in the Release Notes for version 12.0


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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Evandro Menezes via Phabricator via cfe-commits

evandro added a comment.

In D108886#2978038 , @apivovarov 
wrote:

> Evandro, similar notes have been made in the past for Release Notes 12.x and 
> 11.x for Arm and RISC-V processors:
> https://github.com/llvm/llvm-project/blob/release/12.x/clang/docs/ReleaseNotes.rst#modified-compiler-flags
> https://github.com/llvm/llvm-project/blob/release/11.x/clang/docs/ReleaseNotes.rst#modified-compiler-flags

Exactly, but they were not similar changes, but more significant ones, 
including the addition pipeline models.  But I don't feel strongly about it.


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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Alexander Pivovarov via Phabricator via cfe-commits

apivovarov added a comment.

Evandro, similar notes have been made in the past for Release Notes 12.x and 
11.x for Arm and RISC-V processors:
https://github.com/llvm/llvm-project/blob/release/12.x/clang/docs/ReleaseNotes.rst#modified-compiler-flags
https://github.com/llvm/llvm-project/blob/release/11.x/clang/docs/ReleaseNotes.rst#modified-compiler-flags


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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Evandro Menezes via Phabricator via cfe-commits

evandro added a comment.

I don't think that such a minor change makes sense to be added to the release 
notes.


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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Alexander Pivovarov via Phabricator via cfe-commits

apivovarov updated this revision to Diff 370072.
apivovarov added a comment.

Added a note to Release Notes


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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
  FeatureStdExtM,
  FeatureStdExtA,
Index: llvm/include/llvm/Support/RISCVTargetParser.def
===
--- llvm/include/llvm/Support/RISCVTargetParser.def
+++ llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
Index: clang/test/Misc/target-invalid-cpu-note.c
===
--- clang/test/Misc/target-invalid-cpu-note.c
+++ clang/test/Misc/target-invalid-cpu-note.c
@@ -196,7 +196,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-u54, sifive-u74
+// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -204,4 +204,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-u54, sifive-u74, generic, rocket, sifive-7-series
+// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74, generic, rocket, 
sifive-7-series
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | 
FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
+
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck 
-check-prefix=MCPU-SIFIVE-U54 %s
 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -71,7 +71,9 @@
 Modified Compiler Flags
 ---
 
-- ...
+- Support has been added for the following processors (``-mcpu`` identifiers 
in parentheses):
+
+  - RISC-V SiFive S51 (``sifive-s51``).
 
 Removed Compiler Flags
 -


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,

[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Jessica Clarke via Phabricator via cfe-commits

jrtc27 added a comment.

In D108886#2977873 , @apivovarov 
wrote:

> In D108886#2977733 , @jrtc27 wrote:
>
>> You don't need to tag people as well as adding them as reviewers, it's just 
>> annoying. Also, it's only been four days; the developer policy is that for 
>> non-urgent patches you shouldn't ping more than once a week.
>
> Jessica, Contributing to LLVM says - To make sure the right people see your 
> patch, please select suitable reviewers and add them to your patch when 
> requesting a review. Suitable reviewers are the code owner (see 
> CODE_OWNERS.txt) and other people doing work in the area your patch touches.
>
> The people I added as reviewers have contributed to RISC-V target code in the 
> past.

Yeah, but that means adding them as reviewers, you don't also need to @ them in 
general.


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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Evandro Menezes via Phabricator via cfe-commits

evandro accepted this revision.
evandro added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Alexander Pivovarov via Phabricator via cfe-commits

apivovarov added a comment.

In D108886#2977733 , @jrtc27 wrote:

> You don't need to tag people as well as adding them as reviewers, it's just 
> annoying. Also, it's only been four days; the developer policy is that for 
> non-urgent patches you shouldn't ping more than once a week.

Jessica, Contributing to LLVM says - To make sure the right people see your 
patch, please select suitable reviewers and add them to your patch when 
requesting a review. Suitable reviewers are the code owner (see 
CODE_OWNERS.txt) and other people doing work in the area your patch touches.

The people I added as reviewers contributes to RISC-V target code in the past.

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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Fangrui Song via Phabricator via cfe-commits

MaskRay added a comment.

Looks reasonable. You can add a bullet point to clang/docs/ReleaseNotes.rst


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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Jessica Clarke via Phabricator via cfe-commits

jrtc27 added a comment.

In D108886#2977730 , @apivovarov 
wrote:

> @evandro @kito-cheng @kito.cheng @khchen @MaskRay Could you review this 
> patch? Thank you

You don't need to tag people as well as adding them as reviewers, it's just 
annoying. Also, it's only been four days; the developer policy is that for 
non-urgent patches you shouldn't ping more than once a week.

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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-09-01 Thread Alexander Pivovarov via Phabricator via cfe-commits

apivovarov added a subscriber: kito.cheng.
apivovarov added a comment.

@evandro @kito-cheng @kito.cheng @khchen @MaskRay Could you review this patch? 
Thank you


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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-08-31 Thread Alexander Pivovarov via Phabricator via cfe-commits

apivovarov updated this revision to Diff 369745.
apivovarov added a comment.

Add `sifive-s51` to test `target-invalid-cpu-note.c` error messages match string


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Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
  FeatureStdExtM,
  FeatureStdExtA,
Index: llvm/include/llvm/Support/RISCVTargetParser.def
===
--- llvm/include/llvm/Support/RISCVTargetParser.def
+++ llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
Index: clang/test/Misc/target-invalid-cpu-note.c
===
--- clang/test/Misc/target-invalid-cpu-note.c
+++ clang/test/Misc/target-invalid-cpu-note.c
@@ -196,7 +196,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-u54, sifive-u74
+// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -204,4 +204,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-u54, sifive-u74, generic, rocket, sifive-7-series
+// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74, generic, rocket, 
sifive-7-series
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | 
FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
+
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck 
-check-prefix=MCPU-SIFIVE-U54 %s
 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
  FeatureStdExtM,

[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-08-31 Thread Alexander Pivovarov via Phabricator via cfe-commits

apivovarov updated this revision to Diff 369635.
apivovarov added a comment.

update the patch


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108886/new/

https://reviews.llvm.org/D108886

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
  FeatureStdExtM,
  FeatureStdExtA,
Index: llvm/include/llvm/Support/RISCVTargetParser.def
===
--- llvm/include/llvm/Support/RISCVTargetParser.def
+++ llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | 
FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
+
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck 
-check-prefix=MCPU-SIFIVE-U54 %s
 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
  FeatureStdExtM,
  FeatureStdExtA,
Index: llvm/include/llvm/Support/RISCVTargetParser.def
===
--- llvm/include/llvm/Support/RISCVTargetParser.def
+++ llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51:

[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-08-30 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added a comment.

Please upload patches with full context. Using -U99 as documented here 
https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-08-29 Thread Alexander Pivovarov via Phabricator via cfe-commits

apivovarov updated this revision to Diff 369369.
apivovarov added a comment.

fix typo in MCPU-ABI-SIFIVE-S51


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108886/new/

https://reviews.llvm.org/D108886

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
  FeatureStdExtM,
  FeatureStdExtA,
Index: llvm/include/llvm/Support/RISCVTargetParser.def
===
--- llvm/include/llvm/Support/RISCVTargetParser.def
+++ llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | 
FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
+
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck 
-check-prefix=MCPU-SIFIVE-U54 %s
 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
  FeatureStdExtM,
  FeatureStdExtA,
Index: llvm/include/llvm/Support/RISCVTargetParser.def
===
--- llvm/include/llvm/Support/RISCVTargetParser.def
+++ llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+//

[PATCH] D108886: Add RISC-V sifive-s51 cpu

2021-08-29 Thread Alexander Pivovarov via Phabricator via cfe-commits

apivovarov created this revision.
apivovarov added reviewers: evandro, kito-cheng, khchen.
Herald added subscribers: vkmr, frasercrmck, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
apivovarov requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Add RISC-V sifive-s51 cpu.

sifive-51 spec: https://www.sifive.com/cores/s51
gcc: 
https://github.com/riscv/riscv-gcc/blob/c3911e6425f35e0722129cb30cc5ccaf3390cd75/gcc/config/riscv/riscv-cores.def#L42


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108886

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
  FeatureStdExtM,
  FeatureStdExtA,
Index: llvm/include/llvm/Support/RISCVTargetParser.def
===
--- llvm/include/llvm/Support/RISCVTargetParser.def
+++ llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | 
FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-SIFIVE-S51: "-target-abi" "lp64"
+
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck 
-check-prefix=MCPU-SIFIVE-U54 %s
 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"


Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
  FeatureStdExtM,
  FeatureStdExtA,
Index: llvm/include/llvm/Support/RISCVTargetParser.def
===
--- llvm/include/llvm/Support/RISCVTargetParser.def
+++ llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

[PATCH] D108886: Add RISC-V sifive-s51 cpu

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