[PATCH] D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed
This revision was automatically updated to reflect the committed changes. Closed by commit rC342034: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed (authored by miyuki, committed by ). Repository: rC Clang https://reviews.llvm.org/D50507 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/arm-vfp16-arguments.c test/CodeGen/arm_neon_intrinsics.c Index: test/CodeGen/arm_neon_intrinsics.c === --- test/CodeGen/arm_neon_intrinsics.c +++ test/CodeGen/arm_neon_intrinsics.c @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple thumbv7s-apple-darwin -target-abi apcs-gnu\ -// RUN: -target-cpu swift -fallow-half-arguments-and-returns -ffreestanding \ +// RUN: -target-cpu swift -fallow-half-arguments-and-returns \ +// RUN: -target-feature +fullfp16 -ffreestanding \ // RUN: -disable-O0-optnone -emit-llvm -o - %s \ // RUN: | opt -S -mem2reg | FileCheck %s @@ -3896,9 +3897,8 @@ // CHECK-LABEL: @test_vld1q_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[VLD1:%.*]] = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* [[TMP0]], i32 2) -// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[VLD1]] to <8 x half> -// CHECK: ret <8 x half> [[TMP1]] +// CHECK: [[VLD1:%.*]] = call <8 x half> @llvm.arm.neon.vld1.v8f16.p0i8(i8* [[TMP0]], i32 2) +// CHECK: ret <8 x half> [[VLD1]] float16x8_t test_vld1q_f16(float16_t const * a) { return vld1q_f16(a); } @@ -3990,9 +3990,8 @@ // CHECK-LABEL: @test_vld1_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[VLD1:%.*]] = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* [[TMP0]], i32 2) -// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VLD1]] to <4 x half> -// CHECK: ret <4 x half> [[TMP1]] +// CHECK: [[VLD1:%.*]] = call <4 x half> @llvm.arm.neon.vld1.v4f16.p0i8(i8* [[TMP0]], i32 2) +// CHECK: ret <4 x half> [[VLD1]] float16x4_t test_vld1_f16(float16_t const * a) { return vld1_f16(a); } @@ -4106,12 +4105,11 @@ // CHECK-LABEL: @test_vld1q_dup_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 -// CHECK: [[TMP3:%.*]] = insertelement <8 x i16> undef, i16 [[TMP2]], i32 0 -// CHECK: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> [[TMP3]], <8 x i32> zeroinitializer -// CHECK: [[TMP4:%.*]] = bitcast <8 x i16> [[LANE]] to <8 x half> -// CHECK: ret <8 x half> [[TMP4]] +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]], align 2 +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> undef, half [[TMP2]], i32 0 +// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP3]], <8 x half> [[TMP3]], <8 x i32> zeroinitializer +// CHECK: ret <8 x half> [[LANE]] float16x8_t test_vld1q_dup_f16(float16_t const * a) { return vld1q_dup_f16(a); } @@ -4233,12 +4231,11 @@ // CHECK-LABEL: @test_vld1_dup_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 -// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[TMP2]], i32 0 -// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> [[TMP3]], <4 x i32> zeroinitializer -// CHECK: [[TMP4:%.*]] = bitcast <4 x i16> [[LANE]] to <4 x half> -// CHECK: ret <4 x half> [[TMP4]] +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]], align 2 +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> undef, half [[TMP2]], i32 0 +// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> zeroinitializer +// CHECK: ret <4 x half> [[LANE]] float16x4_t test_vld1_dup_f16(float16_t const * a) { return vld1_dup_f16(a); } @@ -4365,12 +4362,11 @@ // CHECK-LABEL: @test_vld1q_lane_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8> -// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP4:%.*]] = load i16, i16* [[TMP3]], align 2 -// CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP4]], i32 7 -// CHECK: [[TMP5:%.*]] = bitcast <8 x i16> [[VLD1_LANE]] to <8 x half> -// CHECK: ret <8 x half> [[TMP5]] +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP4:%.*]] = load half, half* [[TMP3]], align 2 +// CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x half> [[TMP2]], half [[TMP4]], i32 7 +// CHECK: ret <8 x half> [[VLD1_LANE]] float16x8_t test_vld1q_lane_f16(float16_t const * a, float16x8_t b) { return vld1q_lane_f16(a, b, 7); } @@ -4498,12 +4494,11 @@ // CHECK-LABEL: @test_vld1_lane_f16( // CHECK: [[TMP0:%.*]] = bitcast
[PATCH] D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed
efriedma accepted this revision. efriedma added a comment. LGTM https://reviews.llvm.org/D50507 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed
miyuki added a comment. ping https://reviews.llvm.org/D50507 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed
miyuki updated this revision to Diff 160317. miyuki added a comment. Handle return of homogeneous aggregates https://reviews.llvm.org/D50507 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/arm-vfp16-arguments.c test/CodeGen/arm_neon_intrinsics.c Index: test/CodeGen/arm_neon_intrinsics.c === --- test/CodeGen/arm_neon_intrinsics.c +++ test/CodeGen/arm_neon_intrinsics.c @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple thumbv7s-apple-darwin -target-abi apcs-gnu\ -// RUN: -target-cpu swift -fallow-half-arguments-and-returns -ffreestanding \ +// RUN: -target-cpu swift -fallow-half-arguments-and-returns \ +// RUN: -target-feature +fullfp16 -ffreestanding \ // RUN: -disable-O0-optnone -emit-llvm -o - %s \ // RUN: | opt -S -mem2reg | FileCheck %s @@ -3896,9 +3897,8 @@ // CHECK-LABEL: @test_vld1q_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[VLD1:%.*]] = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* [[TMP0]], i32 2) -// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[VLD1]] to <8 x half> -// CHECK: ret <8 x half> [[TMP1]] +// CHECK: [[VLD1:%.*]] = call <8 x half> @llvm.arm.neon.vld1.v8f16.p0i8(i8* [[TMP0]], i32 2) +// CHECK: ret <8 x half> [[VLD1]] float16x8_t test_vld1q_f16(float16_t const * a) { return vld1q_f16(a); } @@ -3990,9 +3990,8 @@ // CHECK-LABEL: @test_vld1_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[VLD1:%.*]] = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* [[TMP0]], i32 2) -// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VLD1]] to <4 x half> -// CHECK: ret <4 x half> [[TMP1]] +// CHECK: [[VLD1:%.*]] = call <4 x half> @llvm.arm.neon.vld1.v4f16.p0i8(i8* [[TMP0]], i32 2) +// CHECK: ret <4 x half> [[VLD1]] float16x4_t test_vld1_f16(float16_t const * a) { return vld1_f16(a); } @@ -4106,12 +4105,11 @@ // CHECK-LABEL: @test_vld1q_dup_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 -// CHECK: [[TMP3:%.*]] = insertelement <8 x i16> undef, i16 [[TMP2]], i32 0 -// CHECK: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> [[TMP3]], <8 x i32> zeroinitializer -// CHECK: [[TMP4:%.*]] = bitcast <8 x i16> [[LANE]] to <8 x half> -// CHECK: ret <8 x half> [[TMP4]] +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]], align 2 +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> undef, half [[TMP2]], i32 0 +// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP3]], <8 x half> [[TMP3]], <8 x i32> zeroinitializer +// CHECK: ret <8 x half> [[LANE]] float16x8_t test_vld1q_dup_f16(float16_t const * a) { return vld1q_dup_f16(a); } @@ -4233,12 +4231,11 @@ // CHECK-LABEL: @test_vld1_dup_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 -// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[TMP2]], i32 0 -// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> [[TMP3]], <4 x i32> zeroinitializer -// CHECK: [[TMP4:%.*]] = bitcast <4 x i16> [[LANE]] to <4 x half> -// CHECK: ret <4 x half> [[TMP4]] +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]], align 2 +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> undef, half [[TMP2]], i32 0 +// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> zeroinitializer +// CHECK: ret <4 x half> [[LANE]] float16x4_t test_vld1_dup_f16(float16_t const * a) { return vld1_dup_f16(a); } @@ -4365,12 +4362,11 @@ // CHECK-LABEL: @test_vld1q_lane_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8> -// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP4:%.*]] = load i16, i16* [[TMP3]], align 2 -// CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP4]], i32 7 -// CHECK: [[TMP5:%.*]] = bitcast <8 x i16> [[VLD1_LANE]] to <8 x half> -// CHECK: ret <8 x half> [[TMP5]] +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP4:%.*]] = load half, half* [[TMP3]], align 2 +// CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x half> [[TMP2]], half [[TMP4]], i32 7 +// CHECK: ret <8 x half> [[VLD1_LANE]] float16x8_t test_vld1q_lane_f16(float16_t const * a, float16x8_t b) { return vld1q_lane_f16(a, b, 7); } @@ -4498,12 +4494,11 @@ // CHECK-LABEL: @test_vld1_lane_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8> -// CHECK: [[TMP2:%.*]] = bitcast <8 x
[PATCH] D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed
efriedma added inline comments. Comment at: lib/CodeGen/TargetInfo.cpp:5788 + llvm::Type *Ty = llvm::ArrayType::get(NewVecTy, Members); + return ABIArgInfo::getDirect(Ty, 0, nullptr, false); +} Do we need equivalent code in classifyReturnType? https://reviews.llvm.org/D50507 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed
miyuki updated this revision to Diff 160121. miyuki edited the summary of this revision. miyuki added a comment. Fix handling of homogeneous aggregates of FP16 vectors https://reviews.llvm.org/D50507 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/arm-vfp16-arguments.c test/CodeGen/arm_neon_intrinsics.c Index: test/CodeGen/arm_neon_intrinsics.c === --- test/CodeGen/arm_neon_intrinsics.c +++ test/CodeGen/arm_neon_intrinsics.c @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple thumbv7s-apple-darwin -target-abi apcs-gnu\ -// RUN: -target-cpu swift -fallow-half-arguments-and-returns -ffreestanding \ +// RUN: -target-cpu swift -fallow-half-arguments-and-returns \ +// RUN: -target-feature +fullfp16 -ffreestanding \ // RUN: -disable-O0-optnone -emit-llvm -o - %s \ // RUN: | opt -S -mem2reg | FileCheck %s @@ -3896,9 +3897,8 @@ // CHECK-LABEL: @test_vld1q_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[VLD1:%.*]] = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* [[TMP0]], i32 2) -// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[VLD1]] to <8 x half> -// CHECK: ret <8 x half> [[TMP1]] +// CHECK: [[VLD1:%.*]] = call <8 x half> @llvm.arm.neon.vld1.v8f16.p0i8(i8* [[TMP0]], i32 2) +// CHECK: ret <8 x half> [[VLD1]] float16x8_t test_vld1q_f16(float16_t const * a) { return vld1q_f16(a); } @@ -3990,9 +3990,8 @@ // CHECK-LABEL: @test_vld1_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[VLD1:%.*]] = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* [[TMP0]], i32 2) -// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VLD1]] to <4 x half> -// CHECK: ret <4 x half> [[TMP1]] +// CHECK: [[VLD1:%.*]] = call <4 x half> @llvm.arm.neon.vld1.v4f16.p0i8(i8* [[TMP0]], i32 2) +// CHECK: ret <4 x half> [[VLD1]] float16x4_t test_vld1_f16(float16_t const * a) { return vld1_f16(a); } @@ -4106,12 +4105,11 @@ // CHECK-LABEL: @test_vld1q_dup_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 -// CHECK: [[TMP3:%.*]] = insertelement <8 x i16> undef, i16 [[TMP2]], i32 0 -// CHECK: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> [[TMP3]], <8 x i32> zeroinitializer -// CHECK: [[TMP4:%.*]] = bitcast <8 x i16> [[LANE]] to <8 x half> -// CHECK: ret <8 x half> [[TMP4]] +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]], align 2 +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> undef, half [[TMP2]], i32 0 +// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP3]], <8 x half> [[TMP3]], <8 x i32> zeroinitializer +// CHECK: ret <8 x half> [[LANE]] float16x8_t test_vld1q_dup_f16(float16_t const * a) { return vld1q_dup_f16(a); } @@ -4233,12 +4231,11 @@ // CHECK-LABEL: @test_vld1_dup_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 -// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[TMP2]], i32 0 -// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> [[TMP3]], <4 x i32> zeroinitializer -// CHECK: [[TMP4:%.*]] = bitcast <4 x i16> [[LANE]] to <4 x half> -// CHECK: ret <4 x half> [[TMP4]] +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]], align 2 +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> undef, half [[TMP2]], i32 0 +// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> zeroinitializer +// CHECK: ret <4 x half> [[LANE]] float16x4_t test_vld1_dup_f16(float16_t const * a) { return vld1_dup_f16(a); } @@ -4365,12 +4362,11 @@ // CHECK-LABEL: @test_vld1q_lane_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8> -// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP4:%.*]] = load i16, i16* [[TMP3]], align 2 -// CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP4]], i32 7 -// CHECK: [[TMP5:%.*]] = bitcast <8 x i16> [[VLD1_LANE]] to <8 x half> -// CHECK: ret <8 x half> [[TMP5]] +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP4:%.*]] = load half, half* [[TMP3]], align 2 +// CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x half> [[TMP2]], half [[TMP4]], i32 7 +// CHECK: ret <8 x half> [[VLD1_LANE]] float16x8_t test_vld1q_lane_f16(float16_t const * a, float16x8_t b) { return vld1q_lane_f16(a, b, 7); } @@ -4498,12 +4494,11 @@ // CHECK-LABEL: @test_vld1_lane_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x
[PATCH] D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed
efriedma added a comment. Do we need to check for homogeneous aggregates of half vectors somewhere? https://reviews.llvm.org/D50507 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed
miyuki created this revision. miyuki added reviewers: eli.friedman, olista01, SjoerdMeijer. Herald added a reviewer: javed.absar. Herald added subscribers: chrib, kristof.beyls. On targets that do not support FP16 natively LLVM currently legalizes vectors of FP16 values by scalarizing them and promoting to FP32. This causes problems for the following code: void foo(int, ...); typedef __attribute__((neon_vector_type(4))) __fp16 float16x4_t; void bar(float16x4_t x) { foo(42, x); } According to the AAPCS (appendix A.2) float16x4_t is a containerized vector fundamental type, so 'foo' expects that the 4 16-bit FP values are packed into 2 32-bit registers, but instead bar promotes them to 4 single precision values. Since we already handle scalar FP16 values in the frontend by bitcasting them to/from integers, this patch adds similar handling for vector types. One existing test required some adjustments because we now generate more bitcasts (so the patch changes the test to target a machine with native FP16 support). https://reviews.llvm.org/D50507 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/arm-vfp16-arguments.c test/CodeGen/arm_neon_intrinsics.c Index: test/CodeGen/arm_neon_intrinsics.c === --- test/CodeGen/arm_neon_intrinsics.c +++ test/CodeGen/arm_neon_intrinsics.c @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple thumbv7s-apple-darwin -target-abi apcs-gnu\ -// RUN: -target-cpu swift -fallow-half-arguments-and-returns -ffreestanding \ +// RUN: -target-cpu swift -fallow-half-arguments-and-returns \ +// RUN: -target-feature +fullfp16 -ffreestanding \ // RUN: -disable-O0-optnone -emit-llvm -o - %s \ // RUN: | opt -S -mem2reg | FileCheck %s @@ -3896,9 +3897,8 @@ // CHECK-LABEL: @test_vld1q_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[VLD1:%.*]] = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* [[TMP0]], i32 2) -// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[VLD1]] to <8 x half> -// CHECK: ret <8 x half> [[TMP1]] +// CHECK: [[VLD1:%.*]] = call <8 x half> @llvm.arm.neon.vld1.v8f16.p0i8(i8* [[TMP0]], i32 2) +// CHECK: ret <8 x half> [[VLD1]] float16x8_t test_vld1q_f16(float16_t const * a) { return vld1q_f16(a); } @@ -3990,9 +3990,8 @@ // CHECK-LABEL: @test_vld1_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[VLD1:%.*]] = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* [[TMP0]], i32 2) -// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VLD1]] to <4 x half> -// CHECK: ret <4 x half> [[TMP1]] +// CHECK: [[VLD1:%.*]] = call <4 x half> @llvm.arm.neon.vld1.v4f16.p0i8(i8* [[TMP0]], i32 2) +// CHECK: ret <4 x half> [[VLD1]] float16x4_t test_vld1_f16(float16_t const * a) { return vld1_f16(a); } @@ -4106,12 +4105,11 @@ // CHECK-LABEL: @test_vld1q_dup_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 -// CHECK: [[TMP3:%.*]] = insertelement <8 x i16> undef, i16 [[TMP2]], i32 0 -// CHECK: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> [[TMP3]], <8 x i32> zeroinitializer -// CHECK: [[TMP4:%.*]] = bitcast <8 x i16> [[LANE]] to <8 x half> -// CHECK: ret <8 x half> [[TMP4]] +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]], align 2 +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> undef, half [[TMP2]], i32 0 +// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP3]], <8 x half> [[TMP3]], <8 x i32> zeroinitializer +// CHECK: ret <8 x half> [[LANE]] float16x8_t test_vld1q_dup_f16(float16_t const * a) { return vld1q_dup_f16(a); } @@ -4233,12 +4231,11 @@ // CHECK-LABEL: @test_vld1_dup_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* -// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 -// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[TMP2]], i32 0 -// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> [[TMP3]], <4 x i32> zeroinitializer -// CHECK: [[TMP4:%.*]] = bitcast <4 x i16> [[LANE]] to <4 x half> -// CHECK: ret <4 x half> [[TMP4]] +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half* +// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]], align 2 +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> undef, half [[TMP2]], i32 0 +// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> zeroinitializer +// CHECK: ret <4 x half> [[LANE]] float16x4_t test_vld1_dup_f16(float16_t const * a) { return vld1_dup_f16(a); } @@ -4365,12 +4362,11 @@ // CHECK-LABEL: @test_vld1q_lane_f16( // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8> -// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK: [[TMP3:%.*]] =