[PATCH] D54295: [WIP, RISCV] Add inline asm constraint A for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 187335.
lewis-revill added a comment.
Herald added subscribers: llvm-commits, jdoerfert.
Herald added a project: LLVM.

Correct test.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54295/new/

https://reviews.llvm.org/D54295

Files:
  lib/Basic/Targets/RISCV.cpp
  test/CodeGen/riscv-inline-asm.c


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -56,6 +56,10 @@
 // A 5-bit unsigned immediate for CSR access instructions.
 Info.setRequiresImmediate(0, 31);
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -56,6 +56,10 @@
 // A 5-bit unsigned immediate for CSR access instructions.
 Info.setRequiresImmediate(0, 31);
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 
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[PATCH] D54295: [WIP, RISCV] Add inline asm constraint A for RISC-V

[James Clarke via Phabricator via cfe-commits]

jrtc27 requested changes to this revision.
jrtc27 added inline comments.
This revision now requires changes to proceed.
Herald added a project: clang.



Comment at: test/CodeGen/riscv-inline-asm.c:32
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm volatile "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));

Should be `sideeffect`


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54295/new/

https://reviews.llvm.org/D54295



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[PATCH] D54295: [WIP, RISCV] Add inline asm constraint A for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill created this revision.
lewis-revill added a reviewer: asb.
Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o, 
brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, 
eraman.

This allows the constraint A to be used in inline asm for RISC-V, which allows 
an address held in a register to be used.

This patch adds the minimal amount of code required to get operands with the 
right constraints to compile. Semantically it would be nice to be able to use 
`setAllowsRegister` rather than `setAllowsMemory` and fall through to the 
backend to verify and lower the register as a memory operand.


Repository:
  rC Clang

https://reviews.llvm.org/D54295

Files:
  lib/Basic/Targets/RISCV.cpp
  test/CodeGen/riscv-inline-asm.c


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm volatile "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -57,6 +57,10 @@
 // A 5-bit unsigned immediate for CSR access instructions.
 Info.setRequiresImmediate(0, 31);
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm volatile "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -57,6 +57,10 @@
 // A 5-bit unsigned immediate for CSR access instructions.
 Info.setRequiresImmediate(0, 31);
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 
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