[PATCH] D59557: Fix CodeGen/arm64-microsoft-status-reg.cpp test

2019-03-19 Thread Eli Friedman via Phabricator via cfe-commits 
efriedma added a comment.

Usually no... I wasn't think about it the last time I reviewed a change to this 
file.  Patch welcome to just zap it, assuming we have appropriate coverage in 
llvm/test/CodeGen/AArch64.


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[PATCH] D59557: Fix CodeGen/arm64-microsoft-status-reg.cpp test

2019-03-19 Thread Simon Pilgrim via Phabricator via cfe-commits 
RKSimon added a comment.

I thought we weren't supposed to reference asm codegen in clang tests? (PR24580)


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[PATCH] D59557: Fix CodeGen/arm64-microsoft-status-reg.cpp test

2019-03-19 Thread Jordan Rupprecht via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rC356517: Fix CodeGen/arm64-microsoft-status-reg.cpp test 
(authored by rupprecht, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D59557?vs=191379=191390#toc

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Files:
  test/CodeGen/arm64-microsoft-status-reg.cpp

Index: test/CodeGen/arm64-microsoft-status-reg.cpp
===
--- test/CodeGen/arm64-microsoft-status-reg.cpp
+++ test/CodeGen/arm64-microsoft-status-reg.cpp
@@ -30,103 +30,103 @@
 void check_ReadWriteStatusReg(__int64 v) {
   __int64 ret;
   ret = _ReadStatusReg(ARM64_CNTVCT);
-// CHECK-ASM: mrs x0, CNTVCT_EL0
+// CHECK-ASM: mrs x8, CNTVCT_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
-// CHECK-ASM: mrs x0, PMCCNTR_EL0
+// CHECK-ASM: mrs x8, PMCCNTR_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMSELR_EL0);
-// CHECK-ASM: mrs x0, PMSELR_EL0
+// CHECK-ASM: mrs x8, PMSELR_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
-// CHECK-ASM: mrs x0, PMXEVCNTR_EL0
+// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
-// CHECK-ASM: mrs x0, PMEVCNTR0_EL0
+// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
-// CHECK-ASM: mrs x0, PMEVCNTR1_EL0
+// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
-// CHECK-ASM: mrs x0, PMEVCNTR30_EL0
+// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_TPIDR_EL0);
-// CHECK-ASM: mrs x0, TPIDR_EL0
+// CHECK-ASM: mrs x8, TPIDR_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
-// CHECK-ASM: mrs x0, TPIDRRO_EL0
+// CHECK-ASM: mrs x8, TPIDRRO_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_TPIDR_EL1);
-// CHECK-ASM: mrs x0, TPIDR_EL1
+// CHECK-ASM: mrs x8, TPIDR_EL1
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
 
   _WriteStatusReg(ARM64_CNTVCT, v);
-// CHECK-ASM: msr S3_3_C14_C0_2, x0
+// CHECK-ASM: msr S3_3_C14_C0_2, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMCCNTR_EL0, v);
-// CHECK-ASM: msr PMCCNTR_EL0, x0
+// CHECK-ASM: msr PMCCNTR_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMSELR_EL0, v);
-// CHECK-ASM: msr PMSELR_EL0, x0
+// CHECK-ASM: msr PMSELR_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
-// CHECK-ASM: msr PMXEVCNTR_EL0, x0
+// CHECK-ASM: msr PMXEVCNTR_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
-// CHECK-ASM: msr PMEVCNTR0_EL0, x0
+// CHECK-ASM: msr PMEVCNTR0_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v);
-// CHECK-ASM: msr PMEVCNTR1_EL0, x0
+// CHECK-ASM: msr PMEVCNTR1_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v);
-// CHECK-ASM: msr PMEVCNTR30_EL0, x0
+// CHECK-ASM: msr PMEVCNTR30_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64

[PATCH] D59557: Fix CodeGen/arm64-microsoft-status-reg.cpp test

2019-03-19 Thread Eli Friedman via Phabricator via cfe-commits 
efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D59557: Fix CodeGen/arm64-microsoft-status-reg.cpp test

2019-03-19 Thread Jordan Rupprecht via Phabricator via cfe-commits 
rupprecht created this revision.
rupprecht added reviewers: arsenm, MatzeB.
Herald added subscribers: cfe-commits, kristof.beyls, javed.absar, wdng.
Herald added a project: clang.

This test is failing after r356499. Update the register selection used in the 
test.


Repository:
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Files:
  clang/test/CodeGen/arm64-microsoft-status-reg.cpp

Index: clang/test/CodeGen/arm64-microsoft-status-reg.cpp
===
--- clang/test/CodeGen/arm64-microsoft-status-reg.cpp
+++ clang/test/CodeGen/arm64-microsoft-status-reg.cpp
@@ -30,103 +30,103 @@
 void check_ReadWriteStatusReg(__int64 v) {
   __int64 ret;
   ret = _ReadStatusReg(ARM64_CNTVCT);
-// CHECK-ASM: mrs x0, CNTVCT_EL0
+// CHECK-ASM: mrs x8, CNTVCT_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
-// CHECK-ASM: mrs x0, PMCCNTR_EL0
+// CHECK-ASM: mrs x8, PMCCNTR_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMSELR_EL0);
-// CHECK-ASM: mrs x0, PMSELR_EL0
+// CHECK-ASM: mrs x8, PMSELR_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
-// CHECK-ASM: mrs x0, PMXEVCNTR_EL0
+// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
-// CHECK-ASM: mrs x0, PMEVCNTR0_EL0
+// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
-// CHECK-ASM: mrs x0, PMEVCNTR1_EL0
+// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
-// CHECK-ASM: mrs x0, PMEVCNTR30_EL0
+// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_TPIDR_EL0);
-// CHECK-ASM: mrs x0, TPIDR_EL0
+// CHECK-ASM: mrs x8, TPIDR_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
-// CHECK-ASM: mrs x0, TPIDRRO_EL0
+// CHECK-ASM: mrs x8, TPIDRRO_EL0
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
   ret = _ReadStatusReg(ARM64_TPIDR_EL1);
-// CHECK-ASM: mrs x0, TPIDR_EL1
+// CHECK-ASM: mrs x8, TPIDR_EL1
 // CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
 // CHECK-IR-NEXT: store i64 %[[VAR]]
 
 
   _WriteStatusReg(ARM64_CNTVCT, v);
-// CHECK-ASM: msr S3_3_C14_C0_2, x0
+// CHECK-ASM: msr S3_3_C14_C0_2, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMCCNTR_EL0, v);
-// CHECK-ASM: msr PMCCNTR_EL0, x0
+// CHECK-ASM: msr PMCCNTR_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMSELR_EL0, v);
-// CHECK-ASM: msr PMSELR_EL0, x0
+// CHECK-ASM: msr PMSELR_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
-// CHECK-ASM: msr PMXEVCNTR_EL0, x0
+// CHECK-ASM: msr PMXEVCNTR_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
-// CHECK-ASM: msr PMEVCNTR0_EL0, x0
+// CHECK-ASM: msr PMEVCNTR0_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v);
-// CHECK-ASM: msr PMEVCNTR1_EL0, x0
+// CHECK-ASM: msr PMEVCNTR1_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 %[[VAR]])
 
   _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v);
-// CHECK-ASM: msr PMEVCNTR30_EL0, x0
+// CHECK-ASM: msr PMEVCNTR30_EL0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
 // CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64 %[[VAR]])