[PATCH] D76714: [ARM,MVE] Add missing tests for vqdmlash intrinsics.

2020-03-25 Thread Simon Tatham via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8f1651ccead1: [ARM,MVE] Add missing tests for vqdmlash 
intrinsics. (authored by simon_tatham).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76714/new/

https://reviews.llvm.org/D76714

Files:
  clang/test/CodeGen/arm-mve-intrinsics/ternary.c
  llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll

Index: llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
===
--- llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
+++ llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
@@ -295,6 +295,38 @@
   ret <4 x i32> %0
 }
 
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmlashq_n_s8(<16 x i8> %m1, <16 x i8> %m2, i8 signext %add) {
+; CHECK-LABEL: test_vqdmlashq_n_s8:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vqdmlash.s8 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = zext i8 %add to i32
+  %1 = tail call <16 x i8> @llvm.arm.mve.vqdmlash.v16i8(<16 x i8> %m1, <16 x i8> %m2, i32 %0)
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmlashq_n_s16(<8 x i16> %m1, <8 x i16> %m2, i16 signext %add) {
+; CHECK-LABEL: test_vqdmlashq_n_s16:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vqdmlash.s16 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = zext i16 %add to i32
+  %1 = tail call <8 x i16> @llvm.arm.mve.vqdmlash.v8i16(<8 x i16> %m1, <8 x i16> %m2, i32 %0)
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlashq_n_s32(<4 x i32> %m1, <4 x i32> %m2, i32 %add) {
+; CHECK-LABEL: test_vqdmlashq_n_s32:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vqdmlash.s32 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlash.v4i32(<4 x i32> %m1, <4 x i32> %m2, i32 %add)
+  ret <4 x i32> %0
+}
+
 define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlahq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
 ; CHECK-LABEL: test_vqrdmlahq_n_s8:
 ; CHECK:   @ %bb.0: @ %entry
@@ -711,6 +743,50 @@
   ret <4 x i32> %2
 }
 
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmlashq_m_n_s8(<16 x i8> %m1, <16 x i8> %m2, i8 signext %add, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlashq_m_n_s8:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vmsr p0, r1
+; CHECK-NEXT:vpst
+; CHECK-NEXT:vqdmlasht.s8 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = zext i8 %add to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
+  %3 = tail call <16 x i8> @llvm.arm.mve.vqdmlash.predicated.v16i8.v16i1(<16 x i8> %m1, <16 x i8> %m2, i32 %0, <16 x i1> %2)
+  ret <16 x i8> %3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmlashq_m_n_s16(<8 x i16> %m1, <8 x i16> %m2, i16 signext %add, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlashq_m_n_s16:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vmsr p0, r1
+; CHECK-NEXT:vpst
+; CHECK-NEXT:vqdmlasht.s16 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = zext i16 %add to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
+  %3 = tail call <8 x i16> @llvm.arm.mve.vqdmlash.predicated.v8i16.v8i1(<8 x i16> %m1, <8 x i16> %m2, i32 %0, <8 x i1> %2)
+  ret <8 x i16> %3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlashq_m_n_s32(<4 x i32> %m1, <4 x i32> %m2, i32 %add, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlashq_m_n_s32:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vmsr p0, r1
+; CHECK-NEXT:vpst
+; CHECK-NEXT:vqdmlasht.s32 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlash.predicated.v4i32.v4i1(<4 x i32> %m1, <4 x i32> %m2, i32 %add, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
 define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlahq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vqrdmlahq_m_n_s8:
 ; CHECK:   @ %bb.0: @ %entry
@@ -816,6 +892,9 @@
 declare <16 x i8> @llvm.arm.mve.vqdmlah.v16i8(<16 x i8>, <16 x i8>, i32)
 declare <8 x i16> @llvm.arm.mve.vqdmlah.v8i16(<8 x i16>, <8 x i16>, i32)
 declare <4 x i32> @llvm.arm.mve.vqdmlah.v4i32(<4 x i32>, <4 x i32>, i32)
+declare <16 x i8> @llvm.arm.mve.vqdmlash.v16i8(<16 x i8>, <16 x i8>, i32)
+declare <8 x i16> @llvm.arm.mve.vqdmlash.v8i16(<8 x i16>, <8 x i16>, i32)
+declare <4 x i32> @llvm.arm.mve.vqdmlash.v4i32(<4 x i32>, <4 x i32>, i32)
 declare <16 x i8> @llvm.arm.mve.vqrdmlah.v16i8(<16 x i8>, <16 x i8>, i32)
 declare <8 x i16> @llvm.arm.mve.vqrdmlah.v8i16(<8 x i16>, <8 x i16>, i32)
 declare <4 x i32> @llvm.arm.mve.vqrdmlah.v4i32(<4 x i32>, <4 x i32>, i32)
@@ -825,6 +904,9 @@
 declare <16 x i8> @llvm.arm.mve.vqdmlah.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
 declare <8 x i16> @llvm.arm.mve.vqdmlah.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
 declare <4 x i32> @llvm.arm.mve.vqdmlah.predic

[PATCH] D76714: [ARM,MVE] Add missing tests for vqdmlash intrinsics.

2020-03-25 Thread Mikhail Maltsev via Phabricator via cfe-commits 
miyuki accepted this revision.
miyuki added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76714/new/

https://reviews.llvm.org/D76714



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[PATCH] D76714: [ARM,MVE] Add missing tests for vqdmlash intrinsics.

2020-03-24 Thread Simon Tatham via Phabricator via cfe-commits 
simon_tatham created this revision.
simon_tatham added a reviewer: miyuki.
Herald added subscribers: cfe-commits, dmgreen, kristof.beyls.
Herald added a project: clang.

These were accidentally left out of D76123 . I 
added tests for the
other three instructions in this small cross-product family (vqdmlah,
vqrdmlah, vqrdmlash) but missed this one.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76714

Files:
  clang/test/CodeGen/arm-mve-intrinsics/ternary.c
  llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll

Index: llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
===
--- llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
+++ llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
@@ -295,6 +295,38 @@
   ret <4 x i32> %0
 }
 
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmlashq_n_s8(<16 x i8> %m1, <16 x i8> %m2, i8 signext %add) {
+; CHECK-LABEL: test_vqdmlashq_n_s8:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vqdmlash.s8 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = zext i8 %add to i32
+  %1 = tail call <16 x i8> @llvm.arm.mve.vqdmlash.v16i8(<16 x i8> %m1, <16 x i8> %m2, i32 %0)
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmlashq_n_s16(<8 x i16> %m1, <8 x i16> %m2, i16 signext %add) {
+; CHECK-LABEL: test_vqdmlashq_n_s16:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vqdmlash.s16 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = zext i16 %add to i32
+  %1 = tail call <8 x i16> @llvm.arm.mve.vqdmlash.v8i16(<8 x i16> %m1, <8 x i16> %m2, i32 %0)
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlashq_n_s32(<4 x i32> %m1, <4 x i32> %m2, i32 %add) {
+; CHECK-LABEL: test_vqdmlashq_n_s32:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vqdmlash.s32 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlash.v4i32(<4 x i32> %m1, <4 x i32> %m2, i32 %add)
+  ret <4 x i32> %0
+}
+
 define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlahq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
 ; CHECK-LABEL: test_vqrdmlahq_n_s8:
 ; CHECK:   @ %bb.0: @ %entry
@@ -711,6 +743,50 @@
   ret <4 x i32> %2
 }
 
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmlashq_m_n_s8(<16 x i8> %m1, <16 x i8> %m2, i8 signext %add, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlashq_m_n_s8:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vmsr p0, r1
+; CHECK-NEXT:vpst
+; CHECK-NEXT:vqdmlasht.s8 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = zext i8 %add to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
+  %3 = tail call <16 x i8> @llvm.arm.mve.vqdmlash.predicated.v16i8.v16i1(<16 x i8> %m1, <16 x i8> %m2, i32 %0, <16 x i1> %2)
+  ret <16 x i8> %3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmlashq_m_n_s16(<8 x i16> %m1, <8 x i16> %m2, i16 signext %add, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlashq_m_n_s16:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vmsr p0, r1
+; CHECK-NEXT:vpst
+; CHECK-NEXT:vqdmlasht.s16 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = zext i16 %add to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
+  %3 = tail call <8 x i16> @llvm.arm.mve.vqdmlash.predicated.v8i16.v8i1(<8 x i16> %m1, <8 x i16> %m2, i32 %0, <8 x i1> %2)
+  ret <8 x i16> %3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlashq_m_n_s32(<4 x i32> %m1, <4 x i32> %m2, i32 %add, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlashq_m_n_s32:
+; CHECK:   @ %bb.0: @ %entry
+; CHECK-NEXT:vmsr p0, r1
+; CHECK-NEXT:vpst
+; CHECK-NEXT:vqdmlasht.s32 q0, q1, r0
+; CHECK-NEXT:bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlash.predicated.v4i32.v4i1(<4 x i32> %m1, <4 x i32> %m2, i32 %add, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
 define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlahq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vqrdmlahq_m_n_s8:
 ; CHECK:   @ %bb.0: @ %entry
@@ -816,6 +892,9 @@
 declare <16 x i8> @llvm.arm.mve.vqdmlah.v16i8(<16 x i8>, <16 x i8>, i32)
 declare <8 x i16> @llvm.arm.mve.vqdmlah.v8i16(<8 x i16>, <8 x i16>, i32)
 declare <4 x i32> @llvm.arm.mve.vqdmlah.v4i32(<4 x i32>, <4 x i32>, i32)
+declare <16 x i8> @llvm.arm.mve.vqdmlash.v16i8(<16 x i8>, <16 x i8>, i32)
+declare <8 x i16> @llvm.arm.mve.vqdmlash.v8i16(<8 x i16>, <8 x i16>, i32)
+declare <4 x i32> @llvm.arm.mve.vqdmlash.v4i32(<4 x i32>, <4 x i32>, i32)
 declare <16 x i8> @llvm.arm.mve.vqrdmlah.v16i8(<16 x i8>, <16 x i8>, i32)
 declare <8 x i16> @llvm.arm.mve.vqrdmlah.v8i16(<8 x i16>, <8 x i16>, i32)
 declare <4 x i32> @llvm.arm.mve.vqrdmlah.v4i32(<4 x i32>, <4 x i32>, i32)
@@ -825,6 +904,9 @@
 declare <16 x i8> @llvm.arm.mve.vqdmlah.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
 declare <8 x i16>