subject:"\[clang\] \[llvm\] \[RISCV\] Add Zilsd and Zclsd Extensions \(PR #131094\)"

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-04-05 Thread via cfe-commits



@@ -176,6 +176,13 @@ def HasStdExtZicfiss : 
Predicate<"Subtarget->hasStdExtZicfiss()">,
   "'Zicfiss' (Shadow stack)">;
 def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
 
+def FeatureStdExtZilsd
+: RISCVExtension<1, 0,
+ "Load/Store Pair Instructions">;

dong-miao wrote:

You mean what benefits does the zilsd extension bring to RV32?  The relevant 
benefits are mentioned in Chapter 1. Introduction of the [specification 
document](https://drive.google.com/file/d/1oMMxKJSuNKNcjiZdJEPeUqOCxr8VcxCn/view).

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-04-05 Thread Pengcheng Wang via cfe-commits



@@ -176,6 +176,13 @@ def HasStdExtZicfiss : 
Predicate<"Subtarget->hasStdExtZicfiss()">,
   "'Zicfiss' (Shadow stack)">;
 def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
 
+def FeatureStdExtZilsd
+: RISCVExtension<1, 0,
+ "Load/Store Pair Instructions">;

wangpc-pp wrote:

Would making Zilsd imply RV32 help?

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-19 Thread Sam Elliott via cfe-commits


https://github.com/lenary closed 
https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-19 Thread Sam Elliott via cfe-commits


https://github.com/lenary approved this pull request.

LGTM. Thanks!

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-19 Thread via cfe-commits


dong-miao wrote:

> do you need someone to merge this?

Yes,Please help me merge.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-19 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/36] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/36] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/36] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/36] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/36] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Craig Topper via cfe-commits


https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread via cfe-commits



@@ -0,0 +1,112 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//
+//===--===//
+
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+  let Name = "GPRPairNoX0RV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairNoX0";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+  let Name = "GPRPairCRV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairC";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CI;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore funct3, string OpcodeStr,
+  DAGOperand RC, DAGOperand opnd>
+: RVInst16CSS;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri funct3, string OpcodeStr,
+   DAGOperand RC, DAGOperand opnd>
+: RVInst16CL;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CS;
+ 
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in 
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32, 
uimm9_lsb000>, 
+  Sched<[WriteLDD, ReadMemBase]> {
+  let Inst{4-2} = imm{8-6};
+}
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in 
+def C_SDSP_RV32 : PairCStackStore<0b111, "c.sdsp", GPRPairRV32, uimm9_lsb000>, 
+  Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+  let Inst{9-7} = imm{8-6};
+}
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LD_RV32 : PairCLoad_ri<0b011, "c.ld", GPRPairCRV32, uimm8_lsb000>,
+Sched<[WriteLDD, ReadMemBase]> {
+  bits<8> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6-5} = imm{7-6};
+}
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SD_RV32 : PairCStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000>,
+Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+  bits<8> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6-5} = imm{7-6};
+}// Predicates = [HasStdExtZclsd, IsRV32]
+
+//===--===//
+// Compress Instruction tablegen backend.
+//===--===//
+
+let Predicates = [HasStdExtZclsd, HasStdExtZilsd, IsRV32] in {
+def : CompressPat<(LD_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
+  (C_LDSP_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, 
uimm9_lsb000:$imm)>;
+def : CompressPat<(SD_RV32 GPRPairRV32:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
+  (C_SDSP_RV32 GPRPairRV32:$rs2, SPMem:$rs1, 
uimm9_lsb000:$imm)>;
+} // Predicates = [HasStdExtZclsd, HasStdExtZilsd, IsRV32]
+
+let Predicates = [HasStdExtZclsd, HasStdExtZilsd, IsRV32] in {

dong-miao wrote:

Complete relevant modifications.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/35] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/35] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/35] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/35] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/35] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread via cfe-commits



@@ -176,6 +176,13 @@ def HasStdExtZicfiss : 
Predicate<"Subtarget->hasStdExtZicfiss()">,
   "'Zicfiss' (Shadow stack)">;
 def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
 
+def FeatureStdExtZilsd
+: RISCVExtension<1, 0,
+ "Load/Store Pair Instructions">;

dong-miao wrote:

Many instruction sets that are only 32-bit or 64 bit have already been declared 
and defined in this format. To reduce some code and disrupt the overall 
definition format, it may not be a good choice.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Craig Topper via cfe-commits


https://github.com/topperc edited 
https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Craig Topper via cfe-commits


https://github.com/topperc edited 
https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Craig Topper via cfe-commits



@@ -19,31 +19,29 @@
 
 # TODO: more exhaustive testing of immediate encoding.
 
-# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
-# CHECK-ASM: encoding: [0x82,0x60]
+# CHECK-ASM-AND-OBJ: c.ldsp s0, 0(sp)
+# CHECK-ASM: encoding: [0x02,0x64]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed 
Instructions) or 'Zca' (part of the C extension, excluding compressed floating 
point loads/stores){{$}}
-# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base 
Instruction Set{{$}}
-c.ldsp ra, 0(sp)
-# CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp)
-# CHECK-ASM: encoding: [0x86,0xff]
+# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' 
(Compressed Load/Store pair instructions){{$}}

topperc wrote:

I don't think there's any way to fix this. The system is going to print the 
missing features from the closest matching instruction. It isn't aggregating 
across possible matches.

I think its uncommon for people to mistakenly compiling code using RV32 when 
they meant RV64 or vice versa. We can probably trust that their used the right 
base.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Sam Elliott via cfe-commits



@@ -401,6 +408,14 @@ def FeatureStdExtZcf
  "Compressed Single-Precision Floating-Point Instructions",
  [FeatureStdExtF, FeatureStdExtZca]>;
 
+def FeatureStdExtZclsd
+: RISCVExtension<1, 0,
+ "Compressed Load/Store pair instructions",
+ [FeatureStdExtZilsd,FeatureStdExtZca]>; 
+def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd() && 
!Subtarget->hasStdExtZcf()">,

lenary wrote:

This is not yet resolved, the check here should be exactly the following:
```suggestion
def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd()">,
```

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Sam Elliott via cfe-commits



@@ -780,6 +780,14 @@ Error RISCVISAInfo::checkDependency() {
   return getIncompatibleError("xwchc", "zcb");
   }
 
+  if (Exts.count("zclsd") != 0) {
+if (XLen != 32)
+  return getError("'zclsd' is only supported for 'rv32'");
+
+if (Exts.count("zcf") != 0)
+  return getIncompatibleError("zclsd", "zcf");
+  }
+

lenary wrote:

This code is not tested. There should be tests in RISCVISAInfoTest.cpp 
`TEST(ParseArchString, RejectsConflictingExtensions)`

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/33] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/33] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/33] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/33] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/33] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Pengcheng Wang via cfe-commits



@@ -176,6 +176,13 @@ def HasStdExtZicfiss : 
Predicate<"Subtarget->hasStdExtZicfiss()">,
   "'Zicfiss' (Shadow stack)">;
 def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
 
+def FeatureStdExtZilsd
+: RISCVExtension<1, 0,
+ "Load/Store Pair Instructions">;

wangpc-pp wrote:

No, I meant maybe we can make `FeatureStdExtZilsd` implies `RV32` here, so that 
we can reduce some checks/predicates. This is because `Zilsd` can only be 
implemented in RV32. But I don't know if this is right.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Sudharsan Veeravalli via cfe-commits



@@ -0,0 +1,12 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+zilsd < %s 2>&1 | FileCheck %s
+
+# Out of range immediates
+## simm12
+ld t1, -2049(a0) # CHECK: :[[@LINE]]:8: error: operand must be a symbol with 
%lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+sd t1, 2048(a0) # CHECK: :[[@LINE]]:8: error: operand must be a symbol with 
%lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Invalid register names
+ld t2, (4)a0 # CHECK: :[[@LINE]]:4: error: register must be even
+ld s3, (4)a0 # CHECK: :[[@LINE]]:4: error: register must be even
+sd t2, (10)s2 # CHECK: :[[@LINE]]:4: error: register must be even
+sd a7, (10)s2 # CHECK: :[[@LINE]]:4: error: register must be even

svs-quic wrote:

Nit: Please add a new line at the end of the file

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Sudharsan Veeravalli via cfe-commits



@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zclsd -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zclsd< %s \
+# RUN: | llvm-objdump --mattr=+zclsd --no-print-imm-hex -M no-aliases -d 
-r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: c.ldsp t1, 176(sp)
+# CHECK-ASM: encoding: [0x4a,0x73]
+c.ldsp t1, 176(sp)
+# CHECK-ASM-AND-OBJ: c.sdsp t1, 360(sp)
+# CHECK-ASM: encoding: [0x9a,0xf6]
+c.sdsp t1, 360(sp)
+# CHECK-ASM-AND-OBJ: c.ld a4, 0(a3)
+# CHECK-ASM: encoding: [0x98,0x62]
+c.ld a4, 0(a3)
+# CHECK-ASM-AND-OBJ: c.sd s0, 248(a3)
+# CHECK-ASM: encoding: [0xe0,0xfe]
+c.sd s0, 248(a3)

svs-quic wrote:

Nit: Please add a new line at the end of the file

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Christian Herber via cfe-commits



@@ -205,6 +206,7 @@ on support follow.
  ``Zihintntl`` Supported
  ``Zihintpause``   Assembly Support
  ``Zihpm`` (`See Note <#riscv-i2p1-note>`__)
+ ``Zilsd`` Supported

christian-herber-nxp wrote:

Supported would indicate there is also code generation. Otherwise, should state 
Assembly Support.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Pengcheng Wang via cfe-commits


https://github.com/wangpc-pp commented:

Please add a ReleaseNote.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Pengcheng Wang via cfe-commits



@@ -19,31 +19,29 @@
 
 # TODO: more exhaustive testing of immediate encoding.
 
-# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
-# CHECK-ASM: encoding: [0x82,0x60]
+# CHECK-ASM-AND-OBJ: c.ldsp s0, 0(sp)
+# CHECK-ASM: encoding: [0x02,0x64]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed 
Instructions) or 'Zca' (part of the C extension, excluding compressed floating 
point loads/stores){{$}}
-# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base 
Instruction Set{{$}}
-c.ldsp ra, 0(sp)
-# CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp)
-# CHECK-ASM: encoding: [0x86,0xff]
+# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' 
(Compressed Load/Store pair instructions){{$}}

wangpc-pp wrote:

This message seems to be inaccurate. We should print both Zclsd and RV64?

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-18 Thread Pengcheng Wang via cfe-commits


https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-17 Thread via cfe-commits



@@ -0,0 +1,25 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zilsd -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zilsd < %s \
+# RUN: | llvm-objdump  --mattr=+zilsd --no-print-imm-hex -M no-aliases -d 
-r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: ld t1, 12(a0)
+# CHECK-ASM: encoding: [0x03,0x33,0xc5,0x00]
+ld t1, 12(a0)
+# CHECK-ASM-AND-OBJ: ld a0, 4(a2)
+# CHECK-ASM: encoding: [0x03,0x35,0x46,0x00]
+ld a0, +4(a2)
+# CHECK-ASM-AND-OBJ: ld t1, -2048(a4)
+# CHECK-ASM: encoding: [0x03,0x33,0x07,0x80]
+ld t1, -2048(a4)
+# CHECK-ASM-AND-OBJ: ld t1, 2047(a4)
+# CHECK-ASM: encoding: [0x03,0x33,0xf7,0x7f]
+ld t1, 2047(a4)
+
+# CHECK-ASM-AND-OBJ: sd s0, 2047(a0)
+# CHECK-ASM: encoding: [0xa3,0x3f,0x85,0x7e]
+sd s0, 2047(a0)
+# CHECK-ASM-AND-OBJ: sd a0, -2048(a2)
+# CHECK-ASM: encoding: [0x23,0x30,0xa6,0x80]
+sd a0, -2048(a2)

dong-miao wrote:

Relevant modifications have been completed.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-17 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/30] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/30] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/30] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/30] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/30] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-17 Thread Sudharsan Veeravalli via cfe-commits



@@ -0,0 +1,22 @@
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zclsd < %s 2>&1 | FileCheck %s
+
+## GPRPairC
+c.ld t1, 4(sp) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+c.sd s2, 4(sp) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+
+## GPRPairNoX0
+c.ldsp  x0, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.ldsp  zero, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for 
instruction
+
+## uimm9_lsb000
+c.ldsp t1, 512(sp) # CHECK: :[[@LINE]]:12: error: immediate must be a multiple 
of 8 bytes in the range [0, 504]
+c.sdsp t1, -8(sp) # CHECK: :[[@LINE]]:12: error: immediate must be a multiple 
of 8 bytes in the range [0, 504]
+## uimm8_lsb000
+c.ld  s0, -8(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple 
of 8 bytes in the range [0, 248]
+c.sd  s0, 256(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple 
of 8 bytes in the range [0, 248]
+
+# Invalid register names
+c.ld a1, 4(sp) # CHECK: :[[@LINE]]:6: error: register must be even
+c.sd a3, 4(sp) # CHECK: :[[@LINE]]:6: error: register must be even
+c.ldsp ra, 4(sp) # CHECK: :[[@LINE]]:8: error: register must be even
+c.ldsp t0, 4(sp) # CHECK: :[[@LINE]]:8: error: register must be even

svs-quic wrote:

Nit: Please add a new line at the end of the file

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-17 Thread Sudharsan Veeravalli via cfe-commits



@@ -0,0 +1,25 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zilsd -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zilsd < %s \
+# RUN: | llvm-objdump  --mattr=+zilsd --no-print-imm-hex -M no-aliases -d 
-r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: ld t1, 12(a0)
+# CHECK-ASM: encoding: [0x03,0x33,0xc5,0x00]
+ld t1, 12(a0)
+# CHECK-ASM-AND-OBJ: ld a0, 4(a2)
+# CHECK-ASM: encoding: [0x03,0x35,0x46,0x00]
+ld a0, +4(a2)
+# CHECK-ASM-AND-OBJ: ld t1, -2048(a4)
+# CHECK-ASM: encoding: [0x03,0x33,0x07,0x80]
+ld t1, -2048(a4)
+# CHECK-ASM-AND-OBJ: ld t1, 2047(a4)
+# CHECK-ASM: encoding: [0x03,0x33,0xf7,0x7f]
+ld t1, 2047(a4)
+
+# CHECK-ASM-AND-OBJ: sd s0, 2047(a0)
+# CHECK-ASM: encoding: [0xa3,0x3f,0x85,0x7e]
+sd s0, 2047(a0)
+# CHECK-ASM-AND-OBJ: sd a0, -2048(a2)
+# CHECK-ASM: encoding: [0x23,0x30,0xa6,0x80]
+sd a0, -2048(a2)

svs-quic wrote:

Nit: Please add a new line at the end of the file

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-17 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/29] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/29] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/29] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/29] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/29] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-17 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/26] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/26] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/26] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/26] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/26] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-17 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/28] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/28] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/28] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/28] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/28] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-17 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/27] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/27] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/27] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/27] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/27] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-15 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/25] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/25] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/25] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/25] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/25] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-15 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/25] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/25] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/25] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/25] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/25] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-15 Thread Craig Topper via cfe-commits



@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+  let Name = "GPRPairNoX0RV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairNoX0";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+  let Name = "GPRPairCRV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairC";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CI;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore funct3, string OpcodeStr,
+  DAGOperand RC, DAGOperand opnd>
+: RVInst16CSS;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri funct3, string OpcodeStr,
+   DAGOperand RC, DAGOperand opnd>
+: RVInst16CL;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CS;
+ 
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in 
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32, 
uimm9_lsb000>, 
+ Sched<[WriteLDD, ReadMemBase]> {

topperc wrote:

Align `Sched` with `PairCStackLoad` on previous line

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-15 Thread via cfe-commits


https://github.com/dong-miao ready_for_review 
https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-15 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/22] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/22] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/22] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/22] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/22] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-14 Thread via cfe-commits


dong-miao wrote:

> This should fix your failures
> 
> ```
> diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
> b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
> index 214378d4b554..59ab59703ac7 100644
> --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
> +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
> @@ -763,7 +763,7 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst 
> &MI, uint64_t &Size,
>TRY_TO_DECODE_AND_ADD_SP(true, DecoderTableRISCV32Only_16,
> "RISCV32Only_16 (16-bit Instruction)");
>// Zc* instructions incompatible with Zcf or Zcd.
> -  TRY_TO_DECODE(true, DecoderTableZcOverlap16,
> +  TRY_TO_DECODE_AND_ADD_SP(true, DecoderTableZcOverlap16,
>  "ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)");
>  
>return MCDisassembler::Fail;
> diff --git a/llvm/test/MC/RISCV/rv64c-valid.s 
> b/llvm/test/MC/RISCV/rv64c-valid.s
> index f8736e5d5453..b0d2bc576be9 100644
> --- a/llvm/test/MC/RISCV/rv64c-valid.s
> +++ b/llvm/test/MC/RISCV/rv64c-valid.s
> @@ -19,26 +19,26 @@
>  
>  # TODO: more exhaustive testing of immediate encoding.
>  
> -# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
> -# CHECK-ASM: encoding: [0x82,0x60]
> +# CHECK-ASM-AND-OBJ: c.ldsp s0, 0(sp)
> +# CHECK-ASM: encoding: [0x02,0x64]
>  # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed 
> Instructions) or 'Zca' (part of the C extension, excluding compressed 
> floating point loads/stores){{$}}
> -# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base 
> Instruction Set{{$}}
> -c.ldsp ra, 0(sp)
> -# CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp)
> -# CHECK-ASM: encoding: [0x86,0xff]
> +# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' 
> (Compressed Load/Store pair instructions){{$}}
> +c.ldsp s0, 0(sp)
> +# CHECK-ASM-AND-OBJ: c.sdsp s2, 504(sp)
> +# CHECK-ASM: encoding: [0xca,0xff]
>  # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed 
> Instructions) or 'Zca' (part of the C extension, excluding compressed 
> floating point loads/stores){{$}}
> -# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base 
> Instruction Set{{$}}
> -c.sdsp ra, 504(sp)
> +# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' 
> (Compressed Load/Store pair instructions){{$}}
> +c.sdsp s2, 504(sp)
>  # CHECK-ASM-AND-OBJ: c.ld a4, 0(a3)
>  # CHECK-ASM: encoding: [0x98,0x62]
>  # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed 
> Instructions) or 'Zca' (part of the C extension, excluding compressed 
> floating point loads/stores){{$}}
> -# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base 
> Instruction Set{{$}}
> +# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' 
> (Compressed Load/Store pair instructions){{$}}
>  c.ld a4, 0(a3)
> -# CHECK-ASM-AND-OBJ: c.sd a5, 248(a3)
> -# CHECK-ASM: encoding: [0xfc,0xfe]
> +# CHECK-ASM-AND-OBJ: c.sd a2, 248(a3)
> +# CHECK-ASM: encoding: [0xf0,0xfe]
>  # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed 
> Instructions) or 'Zca' (part of the C extension, excluding compressed 
> floating point loads/stores){{$}}
> -# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base 
> Instruction Set{{$}}
> -c.sd a5, 248(a3)
> +# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' 
> (Compressed Load/Store pair instructions){{$}}
> +c.sd a2, 248(a3)
>  
>  # CHECK-ASM-AND-OBJ: c.subw a3, a4
>  # CHECK-ASM: encoding: [0x99,0x9e]
> ```

Thanks for your help. I have successfully solved the problem.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-14 Thread via cfe-commits


dong-miao wrote:

> commented
Thanks for your help. I have successfully solved the problem.


https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-14 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/25] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/25] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/25] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/25] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/25] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-14 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/24] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/24] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/24] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/24] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/24] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-14 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/23] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/23] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/23] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/23] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/23] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-14 Thread Craig Topper via cfe-commits


topperc wrote:

This should fix your failures

```
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 214378d4b554..59ab59703ac7 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -763,7 +763,7 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst 
&MI, uint64_t &Size,
   TRY_TO_DECODE_AND_ADD_SP(true, DecoderTableRISCV32Only_16,
"RISCV32Only_16 (16-bit Instruction)");
   // Zc* instructions incompatible with Zcf or Zcd.
-  TRY_TO_DECODE(true, DecoderTableZcOverlap16,
+  TRY_TO_DECODE_AND_ADD_SP(true, DecoderTableZcOverlap16,
 "ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)");
 
   return MCDisassembler::Fail;
diff --git a/llvm/test/MC/RISCV/rv64c-valid.s b/llvm/test/MC/RISCV/rv64c-valid.s
index f8736e5d5453..b0d2bc576be9 100644
--- a/llvm/test/MC/RISCV/rv64c-valid.s
+++ b/llvm/test/MC/RISCV/rv64c-valid.s
@@ -19,26 +19,26 @@
 
 # TODO: more exhaustive testing of immediate encoding.
 
-# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
-# CHECK-ASM: encoding: [0x82,0x60]
+# CHECK-ASM-AND-OBJ: c.ldsp s0, 0(sp)
+# CHECK-ASM: encoding: [0x02,0x64]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed 
Instructions) or 'Zca' (part of the C extension, excluding compressed floating 
point loads/stores){{$}}
-# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base 
Instruction Set{{$}}
-c.ldsp ra, 0(sp)
-# CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp)
-# CHECK-ASM: encoding: [0x86,0xff]
+# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' 
(Compressed Load/Store pair instructions){{$}}
+c.ldsp s0, 0(sp)
+# CHECK-ASM-AND-OBJ: c.sdsp s2, 504(sp)
+# CHECK-ASM: encoding: [0xca,0xff]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed 
Instructions) or 'Zca' (part of the C extension, excluding compressed floating 
point loads/stores){{$}}
-# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base 
Instruction Set{{$}}
-c.sdsp ra, 504(sp)
+# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' 
(Compressed Load/Store pair instructions){{$}}
+c.sdsp s2, 504(sp)
 # CHECK-ASM-AND-OBJ: c.ld a4, 0(a3)
 # CHECK-ASM: encoding: [0x98,0x62]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed 
Instructions) or 'Zca' (part of the C extension, excluding compressed floating 
point loads/stores){{$}}
-# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base 
Instruction Set{{$}}
+# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' 
(Compressed Load/Store pair instructions){{$}}
 c.ld a4, 0(a3)
-# CHECK-ASM-AND-OBJ: c.sd a5, 248(a3)
-# CHECK-ASM: encoding: [0xfc,0xfe]
+# CHECK-ASM-AND-OBJ: c.sd a2, 248(a3)
+# CHECK-ASM: encoding: [0xf0,0xfe]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed 
Instructions) or 'Zca' (part of the C extension, excluding compressed floating 
point loads/stores){{$}}
-# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base 
Instruction Set{{$}}
-c.sd a5, 248(a3)
+# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' 
(Compressed Load/Store pair instructions){{$}}
+c.sd a2, 248(a3)
 
 # CHECK-ASM-AND-OBJ: c.subw a3, a4
 # CHECK-ASM: encoding: [0x99,0x9e]
```

https://github.com/llvm/llvm-project/pull/131094
___
cfe-commits mailing list
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https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-14 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/24] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/24] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/24] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/24] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/24] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-14 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/23] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/23] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/23] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/23] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/23] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-14 Thread via cfe-commits


dong-miao wrote:

When I tested with `sudo ninja - C build check lvm` locally, there were two 
testing errors that I couldn't solve.  For rv32zclsd-valid. s, errors may occur 
during the disassembly process because the test file does not report errors 
when I remove Check-ASM-AND-OBJ.
[Error 
record.txt](https://github.com/user-attachments/files/19243231/Error.record.txt)


https://github.com/llvm/llvm-project/pull/131094
___
cfe-commits mailing list
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https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-14 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/11] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/11] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/11] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/11] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/11] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/21] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/21] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/21] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/21] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/21] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/20] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/20] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/20] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/20] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/20] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits



@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+  let Name = "GPRPairNoX0RV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairNoX0";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+  let Name = "GPRPairCRV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairC";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CI;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore funct3, string OpcodeStr,
+  DAGOperand RC, DAGOperand opnd>
+: RVInst16CSS;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri funct3, string OpcodeStr,
+   DAGOperand RC, DAGOperand opnd>
+: RVInst16CL;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CS;
+ 
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in 
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32, 
uimm9_lsb000>, 
+ Sched<[WriteLDD, ReadMemBase]> {
+  let Inst{4-2} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in 
+def C_SDSP_RV32 : PairCStackStore<0b111, "c.sdsp", GPRPairRV32, uimm9_lsb000>, 
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+  let Inst{9-7} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LD_RV32 : PairCLoad_ri<0b011, "c.ld", GPRPairCRV32, uimm8_lsb000>,
+   Sched<[WriteLDD, ReadMemBase]> {
+  bits<8> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6-5} = imm{7-6};
+}
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SD_RV32 : PairCStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000>,
+   Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+  bits<8> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6-5} = imm{7-6};
+}// Predicates = [HasStdExtZclsd, IsRV32]

topperc wrote:

Go ahead and add RISCVInstrinInfoZclsd.td after RISCVInstrinInfoZilsd.td. I'll 
investigate if we should change the order.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits


https://github.com/topperc edited 
https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits



@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+  let Name = "GPRPairNoX0RV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairNoX0";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+  let Name = "GPRPairCRV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairC";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CI;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore funct3, string OpcodeStr,
+  DAGOperand RC, DAGOperand opnd>
+: RVInst16CSS;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri funct3, string OpcodeStr,
+   DAGOperand RC, DAGOperand opnd>
+: RVInst16CL;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CS;
+ 
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in 
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32, 
uimm9_lsb000>, 
+ Sched<[WriteLDD, ReadMemBase]> {
+  let Inst{4-2} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in 
+def C_SDSP_RV32 : PairCStackStore<0b111, "c.sdsp", GPRPairRV32, uimm9_lsb000>, 
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+  let Inst{9-7} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LD_RV32 : PairCLoad_ri<0b011, "c.ld", GPRPairCRV32, uimm8_lsb000>,
+   Sched<[WriteLDD, ReadMemBase]> {
+  bits<8> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6-5} = imm{7-6};
+}
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SD_RV32 : PairCStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000>,
+   Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+  bits<8> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6-5} = imm{7-6};
+}// Predicates = [HasStdExtZclsd, IsRV32]

dong-miao wrote:

I added it, but due to the file reference order in 
llvm/lib/Target/RISCVInstrInfo.td, an error occurred: Variable not defined: 
'LD_RV32' `def : CompressPat<(LD_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, 
uimm9_lsb000:$imm)`. 
May I ask what I should do? Do I need to directly add 'RISCVInstrinInfoZclsd. 
td' after 'RISCVInstrinInfoZilsd. td'? But this will disrupt the order of file 
references in RISCVInstrInfo.td.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits



@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the standard 'Zilsd',
+// Load/Store pair instructions extension.
+//
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ld_r
+: RVInstI<0b011, OPC_LOAD, (outs RC:$rd), 
+(ins GPRMem:$rs1, simm12:$imm12),
+  opcodestr, "${rd}, ${imm12}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class sd_r

topperc wrote:

> I don't understand why the naming suffix is' _r 'or' _ri 'or' _rri '. It 
> seems to be related to' ins'. Is my guess correct?

Yes.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits



@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the standard 'Zilsd',
+// Load/Store pair instructions extension.
+//
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ld_r
+: RVInstI<0b011, OPC_LOAD, (outs RC:$rd), 
+(ins GPRMem:$rs1, simm12:$imm12),
+  opcodestr, "${rd}, ${imm12}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class sd_r

dong-miao wrote:

I don't understand why the naming suffix is' _r 'or' _ri 'or' _rri '. It seems 
to be related to' ins'. Is my guess correct?

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/10] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/10] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/10] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/10] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/10] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits



@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the standard 'Zilsd',
+// Load/Store pair instructions extension.
+//
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ld_r
+: RVInstI<0b011, OPC_LOAD, (outs RC:$rd), 
+(ins GPRMem:$rs1, simm12:$imm12),

topperc wrote:

The `ins` need to be indented 2 more spaced to align with `0b011` on the 
previous line.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits



@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+  let Name = "GPRPairNoX0RV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairNoX0";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+  let Name = "GPRPairCRV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairC";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CI;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore funct3, string OpcodeStr,
+  DAGOperand RC, DAGOperand opnd>
+: RVInst16CSS;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri funct3, string OpcodeStr,
+   DAGOperand RC, DAGOperand opnd>
+: RVInst16CL;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CS;
+ 
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in 
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32, 
uimm9_lsb000>, 
+ Sched<[WriteLDD, ReadMemBase]> {
+  let Inst{4-2} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in 
+def C_SDSP_RV32 : PairCStackStore<0b111, "c.sdsp", GPRPairRV32, uimm9_lsb000>, 
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+  let Inst{9-7} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LD_RV32 : PairCLoad_ri<0b011, "c.ld", GPRPairCRV32, uimm8_lsb000>,
+   Sched<[WriteLDD, ReadMemBase]> {
+  bits<8> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6-5} = imm{7-6};
+}
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SD_RV32 : PairCStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000>,
+   Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+  bits<8> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6-5} = imm{7-6};
+}// Predicates = [HasStdExtZclsd, IsRV32]

topperc wrote:

Missing CompressPats? They're considered part of the MC layer since they effect 
the assembler.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits



@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the standard 'Zilsd',
+// Load/Store pair instructions extension.
+//
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ld_r
+: RVInstI<0b011, OPC_LOAD, (outs RC:$rd), 
+(ins GPRMem:$rs1, simm12:$imm12),
+  opcodestr, "${rd}, ${imm12}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class sd_r
+: RVInstS<0b011, OPC_STORE, (outs),
+ (ins RC:$rs2, GPRMem:$rs1, simm12:$imm12),

topperc wrote:

Indent `ins` one more space

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits



@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===--===//
+// Instruction Class Templates

topperc wrote:

Please add a blank line and another horizontal line to separate this from the 
file header.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits



@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the standard 'Zilsd',
+// Load/Store pair instructions extension.
+//
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ld_r
+: RVInstI<0b011, OPC_LOAD, (outs RC:$rd), 
+(ins GPRMem:$rs1, simm12:$imm12),
+  opcodestr, "${rd}, ${imm12}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class sd_r

topperc wrote:

PairStore_rri?

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits



@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the standard 'Zilsd',
+// Load/Store pair instructions extension.
+//
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ld_r

topperc wrote:

ld_r -> PairLoad_ri?

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits



@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+  let Name = "GPRPairNoX0RV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairNoX0";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+  let Name = "GPRPairCRV32";
+  let ParserMethod = "parseGPRPair";
+  let PredicateMethod = "isGPRPairC";
+  let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand {
+  let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CI;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore funct3, string OpcodeStr,
+  DAGOperand RC, DAGOperand opnd>
+: RVInst16CSS;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri funct3, string OpcodeStr,
+   DAGOperand RC, DAGOperand opnd>
+: RVInst16CL;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CS;
+ 
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in 
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32, 
uimm9_lsb000>, 
+ Sched<[WriteLDD, ReadMemBase]> {
+  let Inst{4-2} = imm{8-6};
+ }

topperc wrote:

Closing curly brace should be at the start of the line.

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread Craig Topper via cfe-commits



@@ -401,6 +408,14 @@ def FeatureStdExtZcf
  "Compressed Single-Precision Floating-Point Instructions",
  [FeatureStdExtF, FeatureStdExtZca]>;
 
+def FeatureStdExtZclsd
+: RISCVExtension<1, 0,
+ "Compressed Load/Store pair instructions",
+ [FeatureStdExtZilsd,FeatureStdExtZca]>; 
+def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd() && 
!Subtarget->hasStdExtZcf()">,

topperc wrote:

The conflict with Zcf needs to be checked in `RISCVISAInfo::checkDependency` in 
llvm/lib/TargetParser/RISCVISAInfo.cpp 

https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/19] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/19] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/19] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/19] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/19] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/18] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/18] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/18] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/18] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/18] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/17] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/17] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/17] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/17] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/17] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/16] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/16] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/16] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/16] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/16] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/13] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/13] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/13] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/13] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/13] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/12] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/12] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/12] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/12] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/12] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 1/9] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 2/9] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 3/9] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 4/9] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 5/9] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: 
e

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao updated 
https://github.com/llvm/llvm-project/pull/131094

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 1/8] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 2/8] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 3/8] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 4/8] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 5/8] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: 
e

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao converted_to_draft 
https://github.com/llvm/llvm-project/pull/131094
___
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff 8d1e260fc419e31bb11cb5a2f1f872a2b679d217 
2c3440f10357b41e9a19ddacf63f161c58bc5f45 --extensions cpp,c -- 
clang/test/Driver/print-supported-extensions-riscv.c 
clang/test/Preprocessor/riscv-target-features.c 
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
``





View the diff from clang-format here.


``diff
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 1e51314f90..8603cd59ae 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -219,7 +219,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
   ParseStatus parseRegReg(OperandVector &Operands);
   ParseStatus parseRetval(OperandVector &Operands);
   ParseStatus parseZcmpStackAdj(OperandVector &Operands,
-bool ExpectNegative = false);  
 
+bool ExpectNegative = false);
   ParseStatus parseZcmpNegStackAdj(OperandVector &Operands) {
 return parseZcmpStackAdj(Operands, /*ExpectNegative*/ true);
   }
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 8631bed8ae..d342260a9d 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -224,16 +224,16 @@ static DecodeStatus DecodeGPRPairCRegisterClass(MCInst 
&Inst, uint32_t RegNo,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeGPRPairNoX0RegisterClass(MCInst &Inst, uint32_t 
RegNo,
-  uint64_t Address,
-  const MCDisassembler 
*Decoder) {
-if (RegNo == 0) {
-  return MCDisassembler::Fail;
-}
-  
-return DecodeGPRPairRegisterClass(Inst, RegNo, Address, Decoder);
-}
-  
+static DecodeStatus
+DecodeGPRPairNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address,
+   const MCDisassembler *Decoder) {
+  if (RegNo == 0) {
+return MCDisassembler::Fail;
+  }
+
+  return DecodeGPRPairRegisterClass(Inst, RegNo, Address, Decoder);
+}
+
 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {

``




https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

2025-03-13 Thread via cfe-commits


https://github.com/dong-miao created 
https://github.com/llvm/llvm-project/pull/131094

This commit adds the Load/Store pair instructions (Zilsd) and  Compressed 
Load/Store pair instructions (Zclsd).
[Specification 
link](https://github.com/riscv/riscv-isa-manual/blob/main/src/zilsd.adoc).

>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 1/7] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
 // Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
 
 
//===--===//
 // Machine Configuration

>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 2/7] Update rv32-hypervisor-csr-names.s

---
 llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s 
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
 csrrs t1, vsiph, zero
 # uimm12
 csrrs t2, 0x254, zero
+
+##
+# Hypervisor Trap Setup
+##
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero

>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 3/7] Update rv32-machine-csr-names.s

---
 llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s 
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
 #
 # Machine Configuration
 #

>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 4/7] Update RISCVSystemOperands.td

---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td 
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
 def : SysReg<"hedelegh", 0x612>;
 
 
//===--===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
 def : SysReg<"medelegh", 0x312>;
 
 
//===--===//

>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao 
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 5/7] Update rv32-only-csr-names.s

---
 llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 
 1 file changed, 4 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s 
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88ea

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