[clang-tools-extra] [X86][RFC] Support AVX10 options (PR #67278)

2023-10-18 Thread Evgenii Kudriashov via cfe-commits 

https://github.com/e-kud approved this pull request.

LGTM. Thanks!

https://github.com/llvm/llvm-project/pull/67278
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[clang-tools-extra] [X86][RFC] Support AVX10 options (PR #67278)

2023-10-18 Thread Phoebe Wang via cfe-commits 

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/67278

>From eaf36c8cac3fe6d9bb3dcb1387b0b4f1febf5ef7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 25 Sep 2023 10:31:37 +0800
Subject: [PATCH 1/2] [X86][RFC] Support AVX10 options

AVX10 Architecture Specification: 
https://cdrdv2.intel.com/v1/dl/getContent/784267
AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343
RFC: https://discourse.llvm.org/t/rfc-design-for-avx10-options-support/73672
---
 clang/docs/ReleaseNotes.rst   |  1 +
 clang/include/clang/Driver/Options.td |  9 +
 clang/lib/Basic/Targets/X86.cpp   | 37 +--
 clang/lib/Basic/Targets/X86.h |  2 +
 clang/lib/Driver/ToolChains/Arch/X86.cpp  | 30 +++
 clang/test/CodeGen/X86/avx512-error.c | 20 +++---
 clang/test/CodeGen/attr-target-x86.c  | 14 +--
 clang/test/CodeGen/target-avx-abi-diag.c  |  4 ++
 clang/test/Driver/x86-target-features.c   | 20 ++
 clang/test/Preprocessor/x86_target_features.c | 14 +++
 llvm/docs/ReleaseNotes.rst|  2 +
 .../llvm/TargetParser/X86TargetParser.def |  2 +
 llvm/lib/Target/X86/X86.td|  8 
 llvm/lib/Target/X86/X86InstrInfo.td   |  2 +
 llvm/lib/TargetParser/Host.cpp|  6 +++
 llvm/lib/TargetParser/X86TargetParser.cpp |  9 +
 16 files changed, 168 insertions(+), 12 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 7abcb8d799e09dc..419bab7577cfad4 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -387,6 +387,7 @@ X86 Support
 
 - Added option ``-m[no-]evex512`` to disable ZMM and 64-bit mask instructions
   for AVX512 features.
+- Support ISA of ``AVX10.1``.
 
 Arm and AArch64 Support
 ^^^
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 0f93479170d73bc..dd44333e6cb30a7 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -197,6 +197,9 @@ def m_wasm_Features_Driver_Group : OptionGroup<"">,
 def m_x86_Features_Group : OptionGroup<"">,
Group, Visibility<[ClangOption, CLOption]>,
DocName<"X86">;
+def m_x86_AVX10_Features_Group : OptionGroup<"">,
+ Group, Visibility<[ClangOption, 
CLOption]>,
+ DocName<"X86 AVX10">;
 def m_riscv_Features_Group : OptionGroup<"">,
  Group, DocName<"RISC-V">;
 def m_ve_Features_Group : OptionGroup<"">,
@@ -5693,6 +5696,12 @@ def msse4a : Flag<["-"], "msse4a">, 
Group;
 def mno_sse4a : Flag<["-"], "mno-sse4a">, Group;
 def mavx : Flag<["-"], "mavx">, Group;
 def mno_avx : Flag<["-"], "mno-avx">, Group;
+def mavx10_1_256 : Flag<["-"], "mavx10.1-256">, 
Group;
+def mno_avx10_1_256 : Flag<["-"], "mno-avx10.1-256">, 
Group;
+def mavx10_1_512 : Flag<["-"], "mavx10.1-512">, 
Group;
+def mno_avx10_1_512 : Flag<["-"], "mno-avx10.1-512">, 
Group;
+def mavx10_1 : Flag<["-"], "mavx10.1">, Alias;
+def mno_avx10_1 : Flag<["-"], "mno-avx10.1">, Alias;
 def mavx2 : Flag<["-"], "mavx2">, Group;
 def mno_avx2 : Flag<["-"], "mno-avx2">, Group;
 def mavx512f : Flag<["-"], "mavx512f">, Group;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 022d5753135e160..746414181926f7d 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -121,6 +121,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedFeaturesVec;
   bool HasEVEX512 = true;
   bool HasAVX512F = false;
+  bool HasAVX10 = false;
   for (const auto  : FeaturesVec) {
 // Expand general-regs-only to -x86, -mmx and -sse
 if (Feature == "+general-regs-only") {
@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap(
   continue;
 }
 
-if (!HasAVX512F && Feature.substr(0, 7) == "+avx512")
+if (Feature.substr(0, 7) == "+avx10.") {
+  HasAVX10 = true;
   HasAVX512F = true;
-if (HasAVX512F && Feature == "-avx512f")
+  if (Feature.substr(Feature.size() - 3, 3) == "512") {
+HasEVEX512 = true;
+  } else if (Feature.substr(7, 2) == "1-") {
+HasEVEX512 = false;
+  }
+} else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") {
+  HasAVX512F = true;
+} else if (HasAVX512F && Feature == "-avx512f") {
+  HasAVX512F = false;
+} else if (HasAVX10 && Feature == "-avx10.1-256") {
+  HasAVX10 = false;
   HasAVX512F = false;
-if (HasEVEX512 && Feature == "-evex512")
+} else if (!HasEVEX512 && Feature == "+evex512") {
+  HasEVEX512 = true;
+} else if (HasEVEX512 && Feature == "-avx10.1-512") {
   HasEVEX512 = false;
+} else if (HasEVEX512 && Feature == "-evex512") {
+  HasEVEX512 = false;
+}
 
 UpdatedFeaturesVec.push_back(Feature);
   }

[clang-tools-extra] [X86][RFC] Support AVX10 options (PR #67278)

2023-10-17 Thread Evgenii Kudriashov via cfe-commits 


@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap(
   continue;
 }
 
-if (!HasAVX512F && Feature.substr(0, 7) == "+avx512")
+if (Feature.substr(0, 7) == "+avx10.") {
+  HasAVX10 = true;
   HasAVX512F = true;
-if (HasAVX512F && Feature == "-avx512f")
+  if (Feature.substr(Feature.size() - 3, 3) == "512") {
+HasEVEX512 = true;
+  } else if (Feature.substr(7, 2) == "1-") {

e-kud wrote:

I'm not sure whether the comment here is needed or not, but I've had the first 
question: why don't we reset `HasEVEX512` for `avx10.2-256`. And only after 
realization that `avx10.2-256` implies `avx10.1-256`, it makes sense.

https://github.com/llvm/llvm-project/pull/67278
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[clang-tools-extra] [X86][RFC] Support AVX10 options (PR #67278)

2023-10-15 Thread Phoebe Wang via cfe-commits 

phoebewang wrote:

Ping~

https://github.com/llvm/llvm-project/pull/67278
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[clang-tools-extra] [X86][RFC] Support AVX10 options (PR #67278)

2023-10-15 Thread Phoebe Wang via cfe-commits 

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/67278

>From eaf36c8cac3fe6d9bb3dcb1387b0b4f1febf5ef7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 25 Sep 2023 10:31:37 +0800
Subject: [PATCH 1/2] [X86][RFC] Support AVX10 options

AVX10 Architecture Specification: 
https://cdrdv2.intel.com/v1/dl/getContent/784267
AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343
RFC: https://discourse.llvm.org/t/rfc-design-for-avx10-options-support/73672
---
 clang/docs/ReleaseNotes.rst   |  1 +
 clang/include/clang/Driver/Options.td |  9 +
 clang/lib/Basic/Targets/X86.cpp   | 37 +--
 clang/lib/Basic/Targets/X86.h |  2 +
 clang/lib/Driver/ToolChains/Arch/X86.cpp  | 30 +++
 clang/test/CodeGen/X86/avx512-error.c | 20 +++---
 clang/test/CodeGen/attr-target-x86.c  | 14 +--
 clang/test/CodeGen/target-avx-abi-diag.c  |  4 ++
 clang/test/Driver/x86-target-features.c   | 20 ++
 clang/test/Preprocessor/x86_target_features.c | 14 +++
 llvm/docs/ReleaseNotes.rst|  2 +
 .../llvm/TargetParser/X86TargetParser.def |  2 +
 llvm/lib/Target/X86/X86.td|  8 
 llvm/lib/Target/X86/X86InstrInfo.td   |  2 +
 llvm/lib/TargetParser/Host.cpp|  6 +++
 llvm/lib/TargetParser/X86TargetParser.cpp |  9 +
 16 files changed, 168 insertions(+), 12 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 7abcb8d799e09dc..419bab7577cfad4 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -387,6 +387,7 @@ X86 Support
 
 - Added option ``-m[no-]evex512`` to disable ZMM and 64-bit mask instructions
   for AVX512 features.
+- Support ISA of ``AVX10.1``.
 
 Arm and AArch64 Support
 ^^^
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 0f93479170d73bc..dd44333e6cb30a7 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -197,6 +197,9 @@ def m_wasm_Features_Driver_Group : OptionGroup<"">,
 def m_x86_Features_Group : OptionGroup<"">,
Group, Visibility<[ClangOption, CLOption]>,
DocName<"X86">;
+def m_x86_AVX10_Features_Group : OptionGroup<"">,
+ Group, Visibility<[ClangOption, 
CLOption]>,
+ DocName<"X86 AVX10">;
 def m_riscv_Features_Group : OptionGroup<"">,
  Group, DocName<"RISC-V">;
 def m_ve_Features_Group : OptionGroup<"">,
@@ -5693,6 +5696,12 @@ def msse4a : Flag<["-"], "msse4a">, 
Group;
 def mno_sse4a : Flag<["-"], "mno-sse4a">, Group;
 def mavx : Flag<["-"], "mavx">, Group;
 def mno_avx : Flag<["-"], "mno-avx">, Group;
+def mavx10_1_256 : Flag<["-"], "mavx10.1-256">, 
Group;
+def mno_avx10_1_256 : Flag<["-"], "mno-avx10.1-256">, 
Group;
+def mavx10_1_512 : Flag<["-"], "mavx10.1-512">, 
Group;
+def mno_avx10_1_512 : Flag<["-"], "mno-avx10.1-512">, 
Group;
+def mavx10_1 : Flag<["-"], "mavx10.1">, Alias;
+def mno_avx10_1 : Flag<["-"], "mno-avx10.1">, Alias;
 def mavx2 : Flag<["-"], "mavx2">, Group;
 def mno_avx2 : Flag<["-"], "mno-avx2">, Group;
 def mavx512f : Flag<["-"], "mavx512f">, Group;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 022d5753135e160..746414181926f7d 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -121,6 +121,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedFeaturesVec;
   bool HasEVEX512 = true;
   bool HasAVX512F = false;
+  bool HasAVX10 = false;
   for (const auto  : FeaturesVec) {
 // Expand general-regs-only to -x86, -mmx and -sse
 if (Feature == "+general-regs-only") {
@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap(
   continue;
 }
 
-if (!HasAVX512F && Feature.substr(0, 7) == "+avx512")
+if (Feature.substr(0, 7) == "+avx10.") {
+  HasAVX10 = true;
   HasAVX512F = true;
-if (HasAVX512F && Feature == "-avx512f")
+  if (Feature.substr(Feature.size() - 3, 3) == "512") {
+HasEVEX512 = true;
+  } else if (Feature.substr(7, 2) == "1-") {
+HasEVEX512 = false;
+  }
+} else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") {
+  HasAVX512F = true;
+} else if (HasAVX512F && Feature == "-avx512f") {
+  HasAVX512F = false;
+} else if (HasAVX10 && Feature == "-avx10.1-256") {
+  HasAVX10 = false;
   HasAVX512F = false;
-if (HasEVEX512 && Feature == "-evex512")
+} else if (!HasEVEX512 && Feature == "+evex512") {
+  HasEVEX512 = true;
+} else if (HasEVEX512 && Feature == "-avx10.1-512") {
   HasEVEX512 = false;
+} else if (HasEVEX512 && Feature == "-evex512") {
+  HasEVEX512 = false;
+}
 
 UpdatedFeaturesVec.push_back(Feature);
   }

[clang-tools-extra] [X86][RFC] Support AVX10 options (PR #67278)

2023-09-30 Thread Phoebe Wang via cfe-commits 

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/67278

>From eaf36c8cac3fe6d9bb3dcb1387b0b4f1febf5ef7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 25 Sep 2023 10:31:37 +0800
Subject: [PATCH 1/2] [X86][RFC] Support AVX10 options

AVX10 Architecture Specification: 
https://cdrdv2.intel.com/v1/dl/getContent/784267
AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343
RFC: https://discourse.llvm.org/t/rfc-design-for-avx10-options-support/73672
---
 clang/docs/ReleaseNotes.rst   |  1 +
 clang/include/clang/Driver/Options.td |  9 +
 clang/lib/Basic/Targets/X86.cpp   | 37 +--
 clang/lib/Basic/Targets/X86.h |  2 +
 clang/lib/Driver/ToolChains/Arch/X86.cpp  | 30 +++
 clang/test/CodeGen/X86/avx512-error.c | 20 +++---
 clang/test/CodeGen/attr-target-x86.c  | 14 +--
 clang/test/CodeGen/target-avx-abi-diag.c  |  4 ++
 clang/test/Driver/x86-target-features.c   | 20 ++
 clang/test/Preprocessor/x86_target_features.c | 14 +++
 llvm/docs/ReleaseNotes.rst|  2 +
 .../llvm/TargetParser/X86TargetParser.def |  2 +
 llvm/lib/Target/X86/X86.td|  8 
 llvm/lib/Target/X86/X86InstrInfo.td   |  2 +
 llvm/lib/TargetParser/Host.cpp|  6 +++
 llvm/lib/TargetParser/X86TargetParser.cpp |  9 +
 16 files changed, 168 insertions(+), 12 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 7abcb8d799e09dc..419bab7577cfad4 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -387,6 +387,7 @@ X86 Support
 
 - Added option ``-m[no-]evex512`` to disable ZMM and 64-bit mask instructions
   for AVX512 features.
+- Support ISA of ``AVX10.1``.
 
 Arm and AArch64 Support
 ^^^
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 0f93479170d73bc..dd44333e6cb30a7 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -197,6 +197,9 @@ def m_wasm_Features_Driver_Group : OptionGroup<"">,
 def m_x86_Features_Group : OptionGroup<"">,
Group, Visibility<[ClangOption, CLOption]>,
DocName<"X86">;
+def m_x86_AVX10_Features_Group : OptionGroup<"">,
+ Group, Visibility<[ClangOption, 
CLOption]>,
+ DocName<"X86 AVX10">;
 def m_riscv_Features_Group : OptionGroup<"">,
  Group, DocName<"RISC-V">;
 def m_ve_Features_Group : OptionGroup<"">,
@@ -5693,6 +5696,12 @@ def msse4a : Flag<["-"], "msse4a">, 
Group;
 def mno_sse4a : Flag<["-"], "mno-sse4a">, Group;
 def mavx : Flag<["-"], "mavx">, Group;
 def mno_avx : Flag<["-"], "mno-avx">, Group;
+def mavx10_1_256 : Flag<["-"], "mavx10.1-256">, 
Group;
+def mno_avx10_1_256 : Flag<["-"], "mno-avx10.1-256">, 
Group;
+def mavx10_1_512 : Flag<["-"], "mavx10.1-512">, 
Group;
+def mno_avx10_1_512 : Flag<["-"], "mno-avx10.1-512">, 
Group;
+def mavx10_1 : Flag<["-"], "mavx10.1">, Alias;
+def mno_avx10_1 : Flag<["-"], "mno-avx10.1">, Alias;
 def mavx2 : Flag<["-"], "mavx2">, Group;
 def mno_avx2 : Flag<["-"], "mno-avx2">, Group;
 def mavx512f : Flag<["-"], "mavx512f">, Group;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 022d5753135e160..746414181926f7d 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -121,6 +121,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedFeaturesVec;
   bool HasEVEX512 = true;
   bool HasAVX512F = false;
+  bool HasAVX10 = false;
   for (const auto  : FeaturesVec) {
 // Expand general-regs-only to -x86, -mmx and -sse
 if (Feature == "+general-regs-only") {
@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap(
   continue;
 }
 
-if (!HasAVX512F && Feature.substr(0, 7) == "+avx512")
+if (Feature.substr(0, 7) == "+avx10.") {
+  HasAVX10 = true;
   HasAVX512F = true;
-if (HasAVX512F && Feature == "-avx512f")
+  if (Feature.substr(Feature.size() - 3, 3) == "512") {
+HasEVEX512 = true;
+  } else if (Feature.substr(7, 2) == "1-") {
+HasEVEX512 = false;
+  }
+} else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") {
+  HasAVX512F = true;
+} else if (HasAVX512F && Feature == "-avx512f") {
+  HasAVX512F = false;
+} else if (HasAVX10 && Feature == "-avx10.1-256") {
+  HasAVX10 = false;
   HasAVX512F = false;
-if (HasEVEX512 && Feature == "-evex512")
+} else if (!HasEVEX512 && Feature == "+evex512") {
+  HasEVEX512 = true;
+} else if (HasEVEX512 && Feature == "-avx10.1-512") {
   HasEVEX512 = false;
+} else if (HasEVEX512 && Feature == "-evex512") {
+  HasEVEX512 = false;
+}
 
 UpdatedFeaturesVec.push_back(Feature);
   }