Hello all, ** **
We have an urgent requirement with one of direct Client for the following position.**** ** ** Job Title : Associate Consultant**** Location : Folsom CA**** ** ** We are looking for a candidate minimum 2 years of experience in developing, implementing or architecting information systems with listed responsibilities and skill sets.**** ** ** Responsibilities : **** ** ** TECHNOLOGY ANALYST**** **· **Understand the requirement both (functional and non-functional) by going through the specifications and with inputs from Business Analysts, and participate in creating high level estimate as well as translating the same to system requirements**** **· **Participate in creating architecture document**** **· **Develop and review artifacts (code, documentation, test scripts) conduct reviews for self and peers, conduct unit tests and document unit tests for complex programs**** **· **Perform validation activities ( Functional, integration, system, user experience) based on the plans, identification and validation of defects found (including UAT) creation and reviewing of artifacts (test scripts, documentation, automation, setups) participate in performance testing**** **· **Participate in creating the implementation plan as per the project level quality plan and work on go live activities as per the implementation plan.**** **· **Respond to production issues and arrive at a solution with inputs from stakeholders, participate in estimating the effort needed to implement solution, test and implement the solution**** **· **Participate in handling customers as on site coordinators.**** **· **Please Note: This description does not cover or contain a comprehensive listing of activities, duties or responsibilities that are required of the employee.**** ** ** Skills : **** **· **Hands on knowledge of System Verilog**** **· **Hands on working knowledge of methodologies like VMM, OVM, eRM **** **· **Strong hands-on experience on SOC projects.**** **· **Good experience in Full chip SOC and unit level validation.*** * **· **Good knowledge of digital design concepts**** **· **Good knowledge of ASIC design flow**** **· **Hands on knowledge of complete ASIC Front-end verification flow – Verification planning to closure.**** **· **Good knowledge of Verilog/VHDL**** **· **Experience in defining verification plan**** **· **Experience in building re-usable verification environment**** **· **Understand the concept of random test generation and coverage* *** **· **Experience on coverage points and SV assertion**** **· **Good team player and ability to work with stakeholders like RTL team, DFT team and Physical Design team**** **· **Good hands on knowledge of Gate level simulations (with back annotated delay values)**** **· **Good hands on knowledge of Planning and execution of IP level and fullchip verification**** ** ** Additional Skills:**** **· **Experience on Intel SOCs**** **· **Experience on X86**** **· **Qualification **** **· **Bachelor’s degree**** **· **BE/BS/MS/MTECH (EE, EC)**** ** ** Please go through the requirement/Job description & respond me if the above job description suits your profile **** ** ** Thanks & Regards**** ** ** Robert**** New York Technology Partners - Rochester**** 332 Jefferson Rd**** Rochester, NY 14623**** T: 201-680-0200 xt. 7018**** rob...@nytpartners.com**** www.nytpartners.com**** ** ** -- You received this message because you are subscribed to the Google Groups "Citrix and Sap problems" group. To unsubscribe from this group and stop receiving emails from it, send an email to citrix-and-sap-problems+unsubscr...@googlegroups.com. To post to this group, send email to citrix-and-sap-problems@googlegroups.com. Visit this group at http://groups.google.com/group/citrix-and-sap-problems. For more options, visit https://groups.google.com/groups/opt_out.
