On Thu, Dec 20, 2012 at 3:17 AM, Hal Murray hmur...@megapathdsl.net wrote:
If I was going to do something like that, I'd build a small/simple CPU and do
the work in microcode.
There are two ppc 440 cpus already onboard the 10GigE device, I think.
It's a REALLY NICE fpga.
dave.t...@gmail.com said:
If I was going to do something like that, I'd build a small/simple CPU
the work in microcode.
There are two ppc 440 cpus already onboard the 10GigE device, I think. It's
a REALLY NICE fpga.
I'd also looked at the octeon and the latest arm chipset from TI which I
On Thu, Dec 20, 2012 at 8:53 AM, dpr...@reed.com wrote:
I have lately been using (for my very wideband software defined radio
amateur radio transceiver project) the brand new, very nice device called
the Zynq 7000 series of Platform FPGA's from Xilinx. It's a complete system
on a chip, with
OK, I ordered 2. It's not clear how the ethernet is fully implemented
(The marvel phy is documented, the actual ethernet interface is not so
far as I can see, so some source code reading is going to be
required. )
I note that me doing this is also kind of driven by supplies of the
wndr3800
Hi everybody,
Today i made some tests on my tplink home router powered by the lastest
snapshot build of Openwrt.
So, i configured tc to make fq_codel the default queuing algorithm for 2 eth
ports available on the router (leaving unchanged default values).
So, i started some TCP sessions through
Is the bottleneck actually at your router, or (as is more usual) at the
modem?
- Jonathan Morton
On Dec 20, 2012 7:57 PM, Alessandro Bolletta alessan...@mediaspot.net
wrote:
Hi everybody,
Today i made some tests on my tplink home router powered by the lastest
snapshot build of Openwrt.
So,
