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utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 046ff785bed948bbb812e0a1df79ffa219a56230
Author: Fabio Utzig <ut...@apache.org>
AuthorDate: Sat Jun 6 07:19:00 2020 -0300
bsp: nucleo-f439zi add UART_1 pins
Allow use of USART_1, which uses HW USART2, located on CN9 connector.
---
hw/bsp/nucleo-f439zi/src/hal_bsp.c | 14 ++++++++++++++
hw/bsp/nucleo-f439zi/syscfg.yml | 2 ++
2 files changed, 16 insertions(+)
diff --git a/hw/bsp/nucleo-f439zi/src/hal_bsp.c
b/hw/bsp/nucleo-f439zi/src/hal_bsp.c
index 7ccce33..5c62516 100644
--- a/hw/bsp/nucleo-f439zi/src/hal_bsp.c
+++ b/hw/bsp/nucleo-f439zi/src/hal_bsp.c
@@ -86,6 +86,20 @@ const struct stm32_uart_cfg os_bsp_uart0_cfg = {
};
#endif
+#if MYNEWT_VAL(UART_1)
+const struct stm32_uart_cfg os_bsp_uart1_cfg = {
+ .suc_uart = USART2,
+ .suc_rcc_reg = &RCC->APB1ENR,
+ .suc_rcc_dev = RCC_APB1ENR_USART2EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_1_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_1_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_1_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_1_PIN_CTS),
+ .suc_pin_af = GPIO_AF7_USART2,
+ .suc_irqn = USART2_IRQn
+};
+#endif
+
#if MYNEWT_VAL(ETH_0)
const struct stm32_eth_cfg os_bsp_eth0_cfg = {
/*
diff --git a/hw/bsp/nucleo-f439zi/syscfg.yml b/hw/bsp/nucleo-f439zi/syscfg.yml
index af88585..90b830d 100644
--- a/hw/bsp/nucleo-f439zi/syscfg.yml
+++ b/hw/bsp/nucleo-f439zi/syscfg.yml
@@ -49,6 +49,8 @@ syscfg.vals:
STM32_DATA_CACHE_ENABLE: 1
UART_0_PIN_TX: 'MCU_GPIO_PORTD(8)'
UART_0_PIN_RX: 'MCU_GPIO_PORTD(9)'
+ UART_1_PIN_TX: 'MCU_GPIO_PORTD(5)'
+ UART_1_PIN_RX: 'MCU_GPIO_PORTD(6)'
SPI_0_PIN_SS: 'MCU_GPIO_PORTA(4)'
SPI_0_PIN_SCK: 'MCU_GPIO_PORTB(3)'
SPI_0_PIN_MISO: 'MCU_GPIO_PORTB(4)'
