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mlaz pushed a commit to branch master
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The following commit(s) were added to refs/heads/master by this push:
new 9fe0f2b Trying to add NRF52811 support
new da4049c Merge pull request #1855 from alvarop/nrf52811_support
9fe0f2b is described below
commit 9fe0f2b96322a48824418bc005db42f1c52d0a22
Author: Alvaro Prieto <sou...@alvaroprieto.com>
AuthorDate: Fri May 31 16:58:10 2019 -0700
Trying to add NRF52811 support
---
hw/mcu/nordic/nrf52xxx/include/mcu/nrf52_hal.h | 14 +
hw/mcu/nordic/nrf52xxx/include/nrfx52810_config.h | 196 +++++++++++++
hw/mcu/nordic/nrf52xxx/include/nrfx52811_config.h | 196 +++++++++++++
hw/mcu/nordic/nrf52xxx/include/nrfx_config.h | 4 +
hw/mcu/nordic/nrf52xxx/pkg.yml | 5 -
hw/mcu/nordic/nrf52xxx/src/hal_flash.c | 9 +
hw/mcu/nordic/nrf52xxx/src/hal_gpio.c | 2 +-
hw/mcu/nordic/nrf52xxx/src/hal_i2c.c | 5 +
hw/mcu/nordic/nrf52xxx/src/system_nrf52.c | 327 ++++++++++++++++++++++
hw/mcu/nordic/nrf52xxx/syscfg.yml | 6 +
hw/mcu/nordic/pkg.yml | 4 +
11 files changed, 762 insertions(+), 6 deletions(-)
diff --git a/hw/mcu/nordic/nrf52xxx/include/mcu/nrf52_hal.h
b/hw/mcu/nordic/nrf52xxx/include/mcu/nrf52_hal.h
index 2e5f3ab..f566024 100644
--- a/hw/mcu/nordic/nrf52xxx/include/mcu/nrf52_hal.h
+++ b/hw/mcu/nordic/nrf52xxx/include/mcu/nrf52_hal.h
@@ -85,6 +85,20 @@ struct nrf52_hal_spi_cfg {
#define HAL_GPIOTE_PIN_MASK GPIOTE_CONFIG_PSEL_Msk
#endif
+#ifdef NRF52810_XXAA
+#define HAL_GPIO_INDEX(pin) (pin)
+#define HAL_GPIO_PORT(pin) (NRF_P0)
+#define HAL_GPIO_MASK(pin) (1 << pin)
+#define HAL_GPIOTE_PIN_MASK GPIOTE_CONFIG_PSEL_Msk
+#endif
+
+#ifdef NRF52811_XXAA
+#define HAL_GPIO_INDEX(pin) (pin)
+#define HAL_GPIO_PORT(pin) (NRF_P0)
+#define HAL_GPIO_MASK(pin) (1 << pin)
+#define HAL_GPIOTE_PIN_MASK GPIOTE_CONFIG_PSEL_Msk
+#endif
+
#ifdef NRF52840_XXAA
#define HAL_GPIO_INDEX(pin) ((pin) & 0x1F)
#define HAL_GPIO_PORT(pin) ((pin) > 31 ? NRF_P1 : NRF_P0)
diff --git a/hw/mcu/nordic/nrf52xxx/include/nrfx52810_config.h
b/hw/mcu/nordic/nrf52xxx/include/nrfx52810_config.h
new file mode 100644
index 0000000..349e5a2
--- /dev/null
+++ b/hw/mcu/nordic/nrf52xxx/include/nrfx52810_config.h
@@ -0,0 +1,196 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef NRFX52810_CONFIG_H__
+#define NRFX52810_CONFIG_H__
+
+#include "syscfg/syscfg.h"
+
+#ifndef NRFX_CLOCK_ENABLED
+#define NRFX_CLOCK_ENABLED 0
+#endif
+
+#ifndef NRFX_COMP_ENABLED
+#define NRFX_COMP_ENABLED 0
+#endif
+
+#ifndef NRFX_GPIOTE_ENABLED
+#define NRFX_GPIOTE_ENABLED 0
+#endif
+
+#ifndef NRFX_I2S_ENABLED
+#define NRFX_I2S_ENABLED 0
+#endif
+
+// #ifndef NRFX_LPCOMP_ENABLED
+// #define NRFX_LPCOMP_ENABLED 0
+// #endif
+
+#ifndef NRFX_PDM_ENABLED
+#define NRFX_PDM_ENABLED 0
+#endif
+
+#ifndef NRFX_POWER_ENABLED
+#define NRFX_POWER_ENABLED 0
+#endif
+
+#ifndef NRFX_PPI_ENABLED
+#define NRFX_PPI_ENABLED 0
+#endif
+
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 0
+#endif
+
+#ifndef NRFX_QDEC_ENABLED
+#define NRFX_QDEC_ENABLED 0
+#endif
+
+#ifndef NRFX_RNG_ENABLED
+#define NRFX_RNG_ENABLED 0
+#endif
+
+#ifndef NRFX_RTC_ENABLED
+#define NRFX_RTC_ENABLED 0
+#endif
+
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
+#endif
+
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 0
+#endif
+
+#ifndef NRFX_SPI_ENABLED
+#define NRFX_SPI_ENABLED 0
+#endif
+
+#ifndef NRFX_SWI_ENABLED
+#define NRFX_SWI_ENABLED 0
+#endif
+
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 0
+#endif
+
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
+#endif
+
+#ifndef NRFX_TWIM_ENABLED
+#define NRFX_TWIM_ENABLED 0
+#endif
+
+#ifndef NRFX_TWIS_ENABLED
+#define NRFX_TWIS_ENABLED 0
+#endif
+
+#ifndef NRFX_TWI_ENABLED
+#define NRFX_TWI_ENABLED 0
+#endif
+
+#ifndef NRFX_UARTE_ENABLED
+#define NRFX_UARTE_ENABLED 0
+#endif
+
+#ifndef NRFX_UART_ENABLED
+#define NRFX_UART_ENABLED 0
+#endif
+
+#ifndef NRFX_WDT_ENABLED
+#define NRFX_WDT_ENABLED 0
+#endif
+
+#if MYNEWT_VAL(ADC_0)
+#ifndef NRFX_SAADC_ENABLED
+#define NRFX_SAADC_ENABLED 1
+#endif
+
+#ifndef NRFX_SAADC_CONFIG_RESOLUTION
+#define NRFX_SAADC_CONFIG_RESOLUTION 1
+#endif
+
+#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE
+#define NRFX_SAADC_CONFIG_OVERSAMPLE 0
+#endif
+
+#ifndef NRFX_SAADC_CONFIG_LP_MODE
+#define NRFX_SAADC_CONFIG_LP_MODE 0
+#endif
+
+#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY
+#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 7
+#endif
+
+#endif
+
+#if MYNEWT_VAL(PWM_0)
+
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 1
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 0xff
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 0xff
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 0xff
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 0xff
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK
+#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE
+#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+#endif
+
+#if MYNEWT_VAL(PWM_0)
+#define NRFX_PWM0_ENABLED 1
+#endif
+
+#endif // NRFX52810_CONFIG_H__
diff --git a/hw/mcu/nordic/nrf52xxx/include/nrfx52811_config.h
b/hw/mcu/nordic/nrf52xxx/include/nrfx52811_config.h
new file mode 100644
index 0000000..08c736b
--- /dev/null
+++ b/hw/mcu/nordic/nrf52xxx/include/nrfx52811_config.h
@@ -0,0 +1,196 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef NRFX52811_CONFIG_H__
+#define NRFX52811_CONFIG_H__
+
+#include "syscfg/syscfg.h"
+
+#ifndef NRFX_CLOCK_ENABLED
+#define NRFX_CLOCK_ENABLED 0
+#endif
+
+#ifndef NRFX_COMP_ENABLED
+#define NRFX_COMP_ENABLED 0
+#endif
+
+#ifndef NRFX_GPIOTE_ENABLED
+#define NRFX_GPIOTE_ENABLED 0
+#endif
+
+#ifndef NRFX_I2S_ENABLED
+#define NRFX_I2S_ENABLED 0
+#endif
+
+// #ifndef NRFX_LPCOMP_ENABLED
+// #define NRFX_LPCOMP_ENABLED 0
+// #endif
+
+#ifndef NRFX_PDM_ENABLED
+#define NRFX_PDM_ENABLED 0
+#endif
+
+#ifndef NRFX_POWER_ENABLED
+#define NRFX_POWER_ENABLED 0
+#endif
+
+#ifndef NRFX_PPI_ENABLED
+#define NRFX_PPI_ENABLED 0
+#endif
+
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 0
+#endif
+
+#ifndef NRFX_QDEC_ENABLED
+#define NRFX_QDEC_ENABLED 0
+#endif
+
+#ifndef NRFX_RNG_ENABLED
+#define NRFX_RNG_ENABLED 0
+#endif
+
+#ifndef NRFX_RTC_ENABLED
+#define NRFX_RTC_ENABLED 0
+#endif
+
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
+#endif
+
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 0
+#endif
+
+#ifndef NRFX_SPI_ENABLED
+#define NRFX_SPI_ENABLED 0
+#endif
+
+#ifndef NRFX_SWI_ENABLED
+#define NRFX_SWI_ENABLED 0
+#endif
+
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 0
+#endif
+
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
+#endif
+
+#ifndef NRFX_TWIM_ENABLED
+#define NRFX_TWIM_ENABLED 0
+#endif
+
+#ifndef NRFX_TWIS_ENABLED
+#define NRFX_TWIS_ENABLED 0
+#endif
+
+#ifndef NRFX_TWI_ENABLED
+#define NRFX_TWI_ENABLED 0
+#endif
+
+#ifndef NRFX_UARTE_ENABLED
+#define NRFX_UARTE_ENABLED 0
+#endif
+
+#ifndef NRFX_UART_ENABLED
+#define NRFX_UART_ENABLED 0
+#endif
+
+#ifndef NRFX_WDT_ENABLED
+#define NRFX_WDT_ENABLED 0
+#endif
+
+#if MYNEWT_VAL(ADC_0)
+#ifndef NRFX_SAADC_ENABLED
+#define NRFX_SAADC_ENABLED 1
+#endif
+
+#ifndef NRFX_SAADC_CONFIG_RESOLUTION
+#define NRFX_SAADC_CONFIG_RESOLUTION 1
+#endif
+
+#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE
+#define NRFX_SAADC_CONFIG_OVERSAMPLE 0
+#endif
+
+#ifndef NRFX_SAADC_CONFIG_LP_MODE
+#define NRFX_SAADC_CONFIG_LP_MODE 0
+#endif
+
+#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY
+#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 7
+#endif
+
+#endif
+
+#if MYNEWT_VAL(PWM_0)
+
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 1
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 0xff
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 0xff
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 0xff
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 0xff
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK
+#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE
+#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0
+#endif
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+#endif
+
+#if MYNEWT_VAL(PWM_0)
+#define NRFX_PWM0_ENABLED 1
+#endif
+
+#endif // NRFX52811_CONFIG_H__
diff --git a/hw/mcu/nordic/nrf52xxx/include/nrfx_config.h
b/hw/mcu/nordic/nrf52xxx/include/nrfx_config.h
index 0281270..d38a654 100644
--- a/hw/mcu/nordic/nrf52xxx/include/nrfx_config.h
+++ b/hw/mcu/nordic/nrf52xxx/include/nrfx_config.h
@@ -22,6 +22,10 @@
#if NRF52
#include "nrfx52_config.h"
+#elif NRF52810_XXAA
+#include "nrfx52810_config.h"
+#elif NRF52811_XXAA
+#include "nrfx52811_config.h"
#elif NRF52840_XXAA
#include "nrfx52840_config.h"
#else
diff --git a/hw/mcu/nordic/nrf52xxx/pkg.yml b/hw/mcu/nordic/nrf52xxx/pkg.yml
index f2fe61a..e324b1e 100644
--- a/hw/mcu/nordic/nrf52xxx/pkg.yml
+++ b/hw/mcu/nordic/nrf52xxx/pkg.yml
@@ -37,11 +37,6 @@ pkg.deps.'BUS_DRIVER_PRESENT && MCU_BUS_DRIVER_I2C_USE_TWIM':
pkg.deps.'BUS_DRIVER_PRESENT && !MCU_BUS_DRIVER_I2C_USE_TWIM':
- "@apache-mynewt-core/hw/bus/drivers/i2c_hal"
-# NRF52810 doesn't support SPI/I2C (Use SPIM/I2CM instead)
-pkg.ign_files.BSP_NRF52810:
- - "hal_spi.c"
- - "hal_i2c.c"
-
pkg.cflags.NFC_PINS_AS_GPIO:
- '-DCONFIG_NFCT_PINS_AS_GPIOS=1'
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_flash.c
b/hw/mcu/nordic/nrf52xxx/src/hal_flash.c
index f711083..c1d520a 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_flash.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_flash.c
@@ -61,6 +61,15 @@ const struct hal_flash nrf52k_flash_dev = {
.hf_align = 1,
.hf_erased_val = 0xff,
};
+#elif defined(NRF52811_XXAA)
+const struct hal_flash nrf52k_flash_dev = {
+ .hf_itf = &nrf52k_flash_funcs,
+ .hf_base_addr = 0x00000000,
+ .hf_size = 192 * 1024, /* XXX read from factory info? */
+ .hf_sector_cnt = 48, /* XXX read from factory info? */
+ .hf_align = 1,
+ .hf_erased_val = 0xff,
+};
#elif defined(NRF52832_XXAA)
const struct hal_flash nrf52k_flash_dev = {
.hf_itf = &nrf52k_flash_funcs,
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
b/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
index 6d4f3a7..57d31f1 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
@@ -47,7 +47,7 @@
* user specifies a pin that is not used by the processor. If an invalid pin
* number is used unexpected and/or erroneous behavior will result.
*/
-#if defined(NRF52832_XXAA) || defined(NRF52810_XXAA)
+#if defined(NRF52832_XXAA) || defined(NRF52810_XXAA) || defined(NRF52811_XXAA)
#define HAL_GPIO_INDEX(pin) (pin)
#define HAL_GPIO_PORT(pin) (NRF_P0)
#define HAL_GPIO_MASK(pin) (1 << pin)
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_i2c.c
b/hw/mcu/nordic/nrf52xxx/src/hal_i2c.c
index 40d9c5c..77ca5f5 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_i2c.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_i2c.c
@@ -29,6 +29,11 @@
#include <nrf.h>
+#if defined(NRF52810_XXAA) || defined(NRF52811_XXAA)
+#define PSELSCL PSEL.SCL
+#define PSELSDA PSEL.SDA
+#endif
+
#define NRF52_HAL_I2C_MAX (2)
#define NRF52_SCL_PIN_CONF \
diff --git a/hw/mcu/nordic/nrf52xxx/src/system_nrf52.c
b/hw/mcu/nordic/nrf52xxx/src/system_nrf52.c
index c43cf36..902d164 100644
--- a/hw/mcu/nordic/nrf52xxx/src/system_nrf52.c
+++ b/hw/mcu/nordic/nrf52xxx/src/system_nrf52.c
@@ -41,6 +41,14 @@
#include "system_nrf52.h"
#endif
+#ifdef NRF52810_XXAA
+#include "system_nrf52810.h"
+#endif
+
+#ifdef NRF52811_XXAA
+#include "system_nrf52811.h"
+#endif
+
/*lint ++flb "Enter library region" */
#define __SYSTEM_CLOCK_64M (64000000UL)
@@ -65,6 +73,23 @@ static bool errata_66(void);
static bool errata_108(void);
#endif
+#ifdef NRF52810_XXAA
+static bool errata_31(void);
+static bool errata_36(void);
+static bool errata_66(void);
+static bool errata_103(void);
+static bool errata_108(void);
+static bool errata_136(void);
+#endif
+
+#ifdef NRF52811_XXAA
+static bool errata_31(void);
+static bool errata_36(void);
+static bool errata_66(void);
+static bool errata_108(void);
+static bool errata_136(void);
+#endif
+
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#elif defined ( __ICCARM__ )
@@ -213,6 +238,154 @@ void SystemInit(void)
#endif
#endif
+#ifdef NRF52810_XXAA
+ /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly
loaded from FICR at reset" found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_31()){
+ *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244)
& 0x0000E000) >> 13;
+ }
+
+ /* Workaround for Errata 36 "CLOCK: Some registers are not reset when
expected" found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_36()){
+ NRF_CLOCK->EVENTS_DONE = 0;
+ NRF_CLOCK->EVENTS_CTTO = 0;
+ NRF_CLOCK->CTIV = 0;
+ }
+
+ /* Workaround for Errata 66 "TEMP: Linearity specification not met with
default settings" found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_66()){
+ NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
+ NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
+ NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
+ NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
+ NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
+ NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
+ NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
+ NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
+ NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
+ NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
+ NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
+ NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
+ NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
+ NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
+ NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
+ NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
+ NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
+ }
+
+ /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE"
found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_103()){
+ NRF_CCM->MAXPACKETSIZE = 0xFBul;
+ }
+
+ /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon
waking up from System ON Idle or System OFF mode" found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_108()){
+ *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 &
0x0000004F;
+ }
+
+ /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they
should not be" found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_136()){
+ if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
+ NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
+ }
+ }
+
+ /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities
desired. If CONFIG_GPIO_AS_PINRESET is not
+ defined, pin reset will not be available. One GPIO (see Product
Specification to see which one) will then be
+ reserved for PinReset and not available as normal GPIO. */
+ #if defined (CONFIG_GPIO_AS_PINRESET)
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
(UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) !=
(UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[0] = 21;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[1] = 21;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NVIC_SystemReset();
+ }
+ #endif
+#endif
+
+#ifdef NRF52811_XXAA
+ /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly
loaded from FICR at reset" found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_31()){
+ *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244)
& 0x0000E000) >> 13;
+ }
+
+ /* Workaround for Errata 36 "CLOCK: Some registers are not reset when
expected" found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_36()){
+ NRF_CLOCK->EVENTS_DONE = 0;
+ NRF_CLOCK->EVENTS_CTTO = 0;
+ NRF_CLOCK->CTIV = 0;
+ }
+
+ /* Workaround for Errata 66 "TEMP: Linearity specification not met with
default settings" found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_66()){
+ NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
+ NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
+ NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
+ NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
+ NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
+ NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
+ NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
+ NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
+ NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
+ NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
+ NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
+ NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
+ NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
+ NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
+ NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
+ NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
+ NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
+ }
+
+ /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon
waking up from System ON Idle or System OFF mode" found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_108()){
+ *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 &
0x0000004F;
+ }
+
+ /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they
should not be" found at the Errata document
+ for your device located at https://www.nordicsemi.com/DocLib */
+ if (errata_136()){
+ if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
+ NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
+ }
+ }
+
+ /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities
desired. If CONFIG_GPIO_AS_PINRESET is not
+ defined, pin reset will not be available. One GPIO (see Product
Specification to see which one) will then be
+ reserved for PinReset and not available as normal GPIO. */
+ #if defined (CONFIG_GPIO_AS_PINRESET)
+ #define RESET_PIN 21
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
(UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) !=
(UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[0] = RESET_PIN;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[1] = RESET_PIN;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NVIC_SystemReset();
+ }
+ #endif
+
+#endif
+
#ifdef NRF52840_XXAA
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when
expected" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
@@ -428,6 +601,160 @@ static bool errata_108(void)
}
#endif
+#ifdef NRF52810_XXAA
+static bool errata_31(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_36(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_66(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_103(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static bool errata_108(void)
+{
+ if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t
*)0xF0000FE4) & 0x0000000F) == 0x0)){
+ if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
+ return true;
+ }
+ if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
+ return true;
+ }
+ if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static bool errata_136(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+#endif
+
+#ifdef NRF52811_XXAA
+static bool errata_31(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xEul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_36(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xEul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_66(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xEul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_108(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xEul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_136(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xEul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+#endif
+
#ifdef NRF52840_XXAA
static bool errata_36(void)
{
diff --git a/hw/mcu/nordic/nrf52xxx/syscfg.yml
b/hw/mcu/nordic/nrf52xxx/syscfg.yml
index f3d7288..6773bd6 100644
--- a/hw/mcu/nordic/nrf52xxx/syscfg.yml
+++ b/hw/mcu/nordic/nrf52xxx/syscfg.yml
@@ -24,6 +24,8 @@ syscfg.defs:
restrictions:
- $notnull
choices:
+ - nRF52810
+ - nRF52811
- nRF52832
- nRF52840
@@ -449,6 +451,10 @@ syscfg.defs:
- "!XTAL_RC"
deprecated: 1
+syscfg.vals.MCU_NRF52810:
+ MCU_TARGET: nRF52810
+syscfg.vals.MCU_NRF52811:
+ MCU_TARGET: nRF52811
syscfg.vals.MCU_NRF52832:
MCU_TARGET: nRF52832
syscfg.vals.MCU_NRF52840:
diff --git a/hw/mcu/nordic/pkg.yml b/hw/mcu/nordic/pkg.yml
index 8c94b9c..2234d7b 100644
--- a/hw/mcu/nordic/pkg.yml
+++ b/hw/mcu/nordic/pkg.yml
@@ -36,6 +36,10 @@ pkg.ign_files.BSP_NRF52810:
- "nrfx_power.c"
- "nrfx_power_clock.c"
+pkg.ign_files.BSP_NRF52811:
+ - "nrfx_power.c"
+ - "nrfx_power_clock.c"
+
pkg.ign_files.BSP_NRF52840:
- "nrfx_power.c"
- "nrfx_power_clock.c"
